Real-time Deep Learning at the Edge for Scalable Reliability Modeling of Si-MOSFET Power Electronics Converters

Babak Parkhideh; Hamed Tabkhi; Mehrdad Biglarbegian; Mohammadreza Baharani

REVIEW 3 major objections 5 minor 36 references

Real-time Deep Learning at the Edge for Scalable Reliability Modeling of Si-MOSFET Power Electronics Converters

T0 review · 3 major / 5 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read A stacked LSTM trained on four MOSFETs' resistance histories can predict a fifth device's degradation trajectory with about 9% error at the 0.05-ohm warning threshold, running in 26 ms on an embedded edge board.

desk verdict A useful edge-reliability application, but the headline accuracy is compromised by test-set-based model selection in Algorithm 1. read the letter →

arxiv 1908.01244 v1 pith:VWHGQRNA submitted 2019-08-03 cs.LG eess.SP

Mohammadreza Baharani , Mehrdad Biglarbegian , Babak Parkhideh , Hamed Tabkhi This is my paper · ORCID

classification cs.LGeess.SP

keywords powerMOSFETreliabilitystackedLSTMedgecomputingprognosticsandhealthmanagementremainingusefullifepredictionon-stateresistancedegradationcloud-edgeIoTacceleratedagingdata

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that a deep recurrent network can learn a degradation model shared across power MOSFETs of the same type, then predict the resistance-wear trajectory of a device it has never seen. The proposed system, Deep RACE, trains a stacked LSTM in the cloud on aggregated $\Delta R_{\mathrm{ds(on)}}$ histories and runs inference on an embedded edge node next to the converter. In leave-one-device-out tests on five accelerated-aging trajectories, the network reaches about $8.9\%$ absolute average error at the $0.05\,\Omega$ warning threshold, roughly 1.98 times better than a Kalman filter and 1.77 times better than a particle filter, while taking 26 ms and about 1.87 W on the edge board. If correct, this makes fleet-learned, real-time reliability awareness practical for high-frequency converters.

What carries the argument

The load-bearing mechanism is a stacked LSTM: four LSTM layers with 64 hidden units each, followed by a dense layer that maps the normalized hidden state $h_t$ back to physical $\Delta R_{\mathrm{ds(on)}}$ values. Training batches are three-dimensional tensors built from randomly selected sequences of length $\tau + n = 21 + 104$ from each of $m$ devices, so every gradient update sees multiple devices' degradation patterns. The input size is $k=1$: only the resistance trajectory, not voltage, current, or temperature, is fed to the network. The same computation graph is trained on the cloud and then shipped to the edge node, where inference evaluates the LSTM equations on the embedded processor.

What would settle it

Run Deep RACE on resistance histories collected from MOSFETs in a high-frequency converter under varying load and temperature. If the average absolute error at the 0.05 ohm threshold exceeds 8.93%, or if feeding voltage, current, and temperature as additional inputs materially reduces the error, then the single-input collective-training claim is not general.

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Extended reading notes

Core claim

The paper's central claim is that aggregating degradation knowledge across many devices of the same underlying physics, rather than fitting each device in isolation, is what makes accurate unseen-device prediction possible. For each test, the network is trained from scratch on four devices' $\Delta R_{\mathrm{ds(on)}}$ sequences and asked to forecast 104 future resistance samples of the fifth device from the last 21 observed samples. The resulting predictions track the measured trajectories, with the error-distribution plots showing average maximum error below 0.9% and the 0.05-$\Omega$ detection point showing $8.93\%$ absolute error. The paper also reports that increasing the number of devices in each training batch lowers prediction MSE at an exponential rate, and that the trained inference runs in real time on a low-power embedded processor.

Load-bearing premise

The claimed accuracy rests on the premise that the resistance trajectory alone encodes enough degradation information, and that the accelerated-aging trajectories used for training behave like real converter duty cycles; if either fails, the leave-one-device numbers will not transfer to the field.

Editorial extensions

If this is right

A converter entering service can receive a reliability model trained on its predecessors before it accumulates any failure data of its own.
As edge nodes are added and their resistance histories join the training pool, prediction error should keep falling, since the paper measures an exponential drop in MSE with more devices per batch.
The 0.05 ohm detection point can be used as an early-warning threshold to trigger load sharing or maintenance before resistance wear becomes critical.
The same cloud-training/edge-inference structure applies to other semiconductor families as long as a measurable degradation precursor time series exists.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

Beyond the paper: the evaluation uses only resistance sequences from an accelerated-aging campaign, so in the field, where load, thermal, and environmental histories vary, the single-input model may need voltage, current, or temperature channels to hold its 8.93% error; a direct field trial is the natural next test.
If resistance history alone suffices, edge nodes could upload only $\Delta R_{\mathrm{ds(on)}}$ samples instead of raw multi-channel telemetry, sharply reducing cloud bandwidth.
The exponential improvement with fleet size suggests a continual-learning loop: each edge device's later measurements could be recycled as training data to retrain the shared model, making the fleet collectively smarter over its lifetime.
The same edge-cloud contract could be transferred to IGBT or GaN devices by swapping in their precursor signals, though the paper demonstrates only Si-MOSFETs.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Colleague,

Short version: this is a legitimate engineering application of stacked LSTMs to MOSFET degradation forecasting, with a real edge deployment on a TX2, but the headline generalization claim is not supported as reported. The stress-test note is correct: Algorithm 1 selects the saved network using the held-out device's test batch (lines 12-18). That makes the 8.93% figure an in-sample selection result, not an unbiased forecast of an unseen device. The Kalman and Particle filter baselines don't get that advantage, so the 1.98x/1.77x improvement claims are not fairly established as stated.

What's genuinely new: applying collective leave-one-device training to the NASA MOSFET resistance dataset, and demonstrating a working cloud-edge system with 26ms inference at 1.87W on an embedded board. The paper ships code, which helps reproducibility, and the system integration is described concretely. For a five-device dataset, the idea of training on four and predicting the fifth is a reasonable test of unit-to-unit generalization. The learning curve in Fig. 12 (MSE decreasing with more devices per batch) is a nice demonstration of the scalability argument, though it's also affected by the same test-selection issue.

Soft spots, in order: (1) The test-based model selection is load-bearing and needs to be fixed. A proper evaluation would hold out the test device entirely, select the model on training/validation from the four training devices, and only then evaluate on the fifth. (2) No error bars over random initializations. Table 4 gives single numbers. Given only five devices and one initialization per scenario, the 8.93% could easily be the lucky draw. (3) Baselines are thin: the Kalman and Particle filter results are cited from prior work, but the protocol is not fully described here, and it's unclear if they were given the same training data or the same prediction window. (4) The model uses only the resistance trajectory as input (k=1), despite the system monitoring voltage, current, and temperature. The claim that resistance history alone encodes degradation might be true for this dataset, but it's an assumption that should be stated and ideally tested.

This is not a desk-reject paper. The engineering is real, the application is relevant, and the evaluation flaw is correctable. A serious referee should be assigned, with the request to have the authors redo the leave-one-device evaluation with a clean held-out protocol and report variance over seeds. As it stands, cite with caution; the accuracy number is not yet trustworthy.

Referee Report

3 major / 5 minor

Summary. The paper presents Deep RACE, a cloud-edge system for real-time reliability modeling of Si-MOSFET power converters. The algorithm side is a stacked LSTM trained in the cloud on aggregated delta-Rds(on) trajectories from multiple devices, with inference deployed on an NVIDIA TX2 edge node. The authors evaluate the approach on five NASA accelerated-aging MOSFET datasets in a leave-one-device-out protocol, reporting a miss-prediction error of 8.93% at the 0.05-ohm detection point, improvements of 1.98x and 1.77x over Kalman Filter and Particle Filter baselines, and measured edge inference cost of 26 ms and 1.87 W. The paper also describes scalability of the aggregated training and a prototype hardware setup.

Significance. If the reported accuracy holds under a clean evaluation protocol, the work would be a useful demonstration of collective deep-learning-based prognostics for power semiconductors, and the measured edge deployment figures (26 ms, 1.87 W) provide concrete evidence of feasibility. The open-source availability of the code is also a strength. However, the central quantitative claim is compromised by a test-set model-selection step in the training algorithm, so the significance of the result depends on whether the evaluation can be corrected and the conclusions re-established.

major comments (3)

[Algorithm 1, Section 4.2.1] Algorithm 1, lines 12-18, uses the held-out device's Xtest and Ytest inside the training loop to select and save the network with the minimum test error. This is test-set-based model selection: the reported Tables 3 and 4 are produced from a checkpoint chosen using the labels of the supposedly unseen device. Because the Kalman Filter and Particle Filter baselines receive no such selection advantage, the claimed 1.98x and 1.77x improvements are not fairly established. The evaluation must be changed so that the test device contributes no information to training or model selection; for example, use a validation set drawn from the training devices for checkpoint selection, or use nested cross-validation.
[Section 5.3, Table 4] Table 4 reports a single miss-prediction number per method, with no variance, error bars, or repeated-run statistics. Given the LSTM's random initialization (Algorithm 1, line 5) and the small five-device sample, a single run cannot support the claim of superiority. Report the mean and standard deviation over multiple random seeds and, ideally, a paired statistical comparison with the baselines.
[Section 5.3, Fig. 10] The text describes the leave-one-device experiment as predicting a 'completely new and unknown device,' but the algorithm actually uses the test device's full trajectory for model selection at every iteration. This contradicts the generalization claim. The experimental protocol must be revised so that no information from the test device reaches the training or model-selection pipeline; otherwise the 8.93% figure is an optimistic in-sample selection result, not an unbiased forecast.

minor comments (5)

[Abstract and Section 5.3] The abstract reports '8.9%' while Table 4 reports '8.93%'; unify the rounding for consistency.
[Section 5.3, Eq. (15)] The notation in Eq. (15), especially the subscript/superscript 'mt5%', is not defined clearly; please define m, t5%, and the meaning of the superscript in the equation or its caption.
[Section 3.1 and Section 4.1.2] There are several language errors, such as 'infertile' in Section 3.1 (should likely be 'ineffective') and 'patriarchy' in Section 4.1.2 (should be 'hierarchy'). A careful proofreading pass is needed.
[Section 4.2.2 and Table 1] Section 4.2.2 states that the edge node continuously monitors voltage, current, and temperature, but the LSTM input size is k=1 (Table 1), so only delta Rds(on) is used. Clarify whether the other signals are used by the reliability model or only by the controller for other purposes.
[Section 5.3, Fig. 12] The y-axis of Fig. 12 is labeled log(MSE) with negative values; clarify whether the plotted quantity is log10(MSE) and describe the Monte-Carlo averaging procedure more precisely.

Circularity Check

1 steps flagged · score 6.0 of 10

Algorithm 1 selects the saved checkpoint by minimizing loss on the held-out device, making the headline 8.93% error and 1.98x/1.77x gains test-selected rather than clean predictions.

fitted input called prediction [Section 4.2.1 (Algorithm 1, lines 12-18); reported in Section 5.3, Table 4]
"In order to prevent the over-ﬁtting problem, we have created a test batch (xtest,ytest) to predict ∆Rds(on) of the test device based on the updated network model. Next, the test batcherror will be compared against the previous error values and if it has the minimum value, the network model will be saved."

The saved model is the one whose loss on Xtest/Ytest is minimal during training, because Algorithm 1 feeds the held-out device's data into the checkpoint-selection loop (lines 12-18). Tables 3-4 then report errors from this test-selected model as predictions for a 'completely new and unknown device.' The held-out trajectory is therefore an input to the reported prediction: the 8.93% endpoint error is an in-sample minimum over checkpoints, not an unbiased leave-one-device generalization estimate, and the Kalman/Particle baselines are not shown to receive the same selection advantage.

full rationale

The paper's modeling chain is otherwise self-contained: the LSTM equations (7)-(12) are standard, the stacked architecture and dense de-normalization are clearly specified, and the NASA dataset is external. The only self-citation, [35], is used merely to note that design-space exploration is possible and is not load-bearing. The central circularity risk is the training protocol: Algorithm 1 evaluates the loss on Xtest,Ytest inside the training loop and saves the network whenever that test loss is a new minimum. Consequently, the weights that produce Tables 3-4 are a function of the held-out device's trajectory, so the reported 'unseen device' accuracy and the factor-of-1.98/1.77 improvements over Kalman/Particle filters are optimistic in-sample selection results rather than clean forecasts. Because this affects the paper's central quantitative claim, the score is 6. If this test-set model selection were replaced by a proper validation split, the remaining derivation would contain no significant circularity.

Assumptions & free parameters 8 free parameters · 5 assumptions · 0 invented entities

The central claim rests on the NASA dataset being representative, on delta Rds(on) being a sufficient precursor, and on hyperparameters chosen by hand. The LSTM math itself is standard and not the source of novelty or risk.

free parameters (8)

Number of hidden units = 64
Network capacity chosen by hand in Table 1; no sensitivity analysis is reported.
Number of stacked layers = 4
Architecture depth chosen by hand in Table 1.
Input sequence length tau = 21
Window length chosen by hand in Table 1.
Output sequence length n = 104
Prediction horizon chosen by hand in Table 1.
Maximum iterations = 1000
Training stopping bound chosen by hand in Table 1.
Error threshold = 0.00005
Training stopping threshold chosen by hand in Table 1.
Adam learning rate = not reported
The optimizer is named as Adam in Section 5.1, but the learning rate is not given; the default TensorFlow value likely applies.
Number of devices per batch m = 4
The batch tensor uses m=4 training devices; the scalability claim in Fig. 12 varies this parameter.

assumptions (5)

standard math LSTM equations and backpropagation through time are assumed correct and trainable.
Equations 7-12 are standard LSTM definitions; no formal verification is provided.
domain assumption Delta Rds(on) is a valid precursor for MOSFET degradation.
Section 2.2 cites standards and prior work for this choice; the entire learning target depends on it.
domain assumption The NASA IRF520NPbf accelerated-aging dataset is representative of real converter degradation.
Section 5.1 uses only this dataset; no field data is presented, so transferability is assumed.
domain assumption Five same-part devices share enough underlying physics for leave-one-device generalization.
Section 5.3 uses leave-one-out across five devices; if device behavior is idiosyncratic, the aggregation benefit may not generalize.
domain assumption Random window sampling and truncated normal initialization give unbiased training.
Algorithm 1 relies on these choices, but no seed or variance analysis is reported.

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Cite this review

Pith. "Pith review of Real-time Deep Learning at the Edge for Scalable Reliability Modeling of Si-MOSFET Power Electronics Converters." pith.science (2026). https://pith.science/paper/VWHGQRNA

@misc{pith2026190801244,
  author       = {Pith},
  title        = {Pith review of: Real-time Deep Learning at the Edge for Scalable Reliability Modeling of Si-MOSFET Power Electronics Converters},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/VWHGQRNA}},
  note         = {Machine review of arXiv:1908.01244}
}

abstract

With the significant growth of advanced high-frequency power converters, on-line monitoring and active reliability assessment of power electronic devices are extremely crucial. This article presents a transformative approach, named Deep Learning Reliability Awareness of Converters at the Edge (Deep RACE), for real-time reliability modeling and prediction of high-frequency MOSFET power electronic converters. Deep RACE offers a holistic solution which comprises algorithm advances, and full system integration (from the cloud down to the edge node) to create a near real-time reliability awareness. On the algorithm side, this paper proposes a deep learning algorithmic solution based on stacked LSTM for collective reliability training and inference across collective MOSFET converters based on device resistance changes. Deep RACE also proposes an integrative edge-to-cloud solution to offer a scalable decentralized devices-specific reliability monitoring, awareness, and modeling. The MOSFET convertors are IoT devices which have been empowered with edge real-time deep learning processing capabilities. The proposed Deep RACE solution has been prototyped and implemented through learning from MOSFET data set provided by NASA. Our experimental results show an average miss prediction of $8.9\%$ over five different devices which is a much higher accuracy compared to well-known classical approaches (Kalman Filter, and Particle Filter). Deep RACE only requires $26ms$ processing time and $1.87W$ computing power on Edge IoT device.

Figures

Figures reproduced from arXiv: 1908.01244 by the authors.

**Figure 1.** MOSFET ∆Rds(on) Precursor Identifier: The trajectory Rds(on) for five different MOSFET devices. and parameters. These techniques require an accurate failure model of a system to estimate the unknown mathematical parameters associated with a specific failure test; however, for new technologies, these methods cannot be effective due to the lack of precise failure model in the component as well as system level [15]. Th… view at source ↗

**Figure 2.** Recurrent Neural Networks: The schematic of standard RNN cell and its unrolling version for four input time sequence of RNN learning is to minimize the cost function. This goal can be formalized by (6), which minimizes the introduced loss function by altering θ, where θ is a network vector model which is described as: θ = [Wi Wc Wo bi bo c0]. L(Z, Y ) = Xτ t=1 L(zt, yt), (5) argmin θ L(z(θ), Y ). (6) Backpropagation… view at source ↗

**Figure 3.** A single LSTM cell: Inside of an LSTM cell consisting of three gates and the state of the cell is preserved by variable ct. one means the gate is open. Moreover, the cell state (memory) is preserved by C as a candidate. The information of new candidates, which should be stored in the cell state, represented as c˜. it = σ(Wivt + bi), (7) ft = σ(Wf vt + bf ), (8) ot = σ(Wovt + bo), (9) c˜t = tanh(Wcvt + bc), (10) ct =… view at source ↗

Figures from the paper (9 more)

**Figure 4.** Figure 4: Batch tensor configuration: Three dimensional batch tensor with a characterized vector Rk mt. For designing of deep LSTM network, we need to also consider number of hidden layers. The number of hidden layer is the dimension of vectors generated in equations (7)-(12). T…

**Figure 5.** Figure 5: The stacked LSTM: An unrolled LSTM cell predicts the next n samples of ∆Rds(on) based on last sensed data. At the same time, building a very deep LSTM network is not a viable solution due to lack of large data-set to trained all LSTM cells once at the same time. The BP…

**Figure 6.** Figure 6: The proposed deep LSTM network model: A dense layer is added to the deep stacked LSTM to map ht to on-line measured ∆Rds(on) at time t. 4.2 Proposed IoT Framework In this subsection, we explained the system integration to realize the proposed LSTM reliability modeling …

**Figure 7.** Figure 7: The Deep RACE Framework: The proposed solution accumulates the knowledge of power transistor degradation model on the cloud-side by training the LSTM network, while real-time prediction and inference is accomplished on the edge side. In this context, the edge nodes and…

**Figure 8.** Figure 8 [PITH_FULL_IMAGE:figures/full_fig_p010_8.png]

**Figure 9.** Figure 9: shows the prototype of Deep RACE hardware realization at the edge. In this system, µ-controller controls the power converter, and the voltage, and current of the power semiconductor are captured and then transfered to the TX2 board for edge analysis. For the safety pur…

**Figure 10.** Figure 10: illustrates the Deep RACE prediction performance for defined five scenarios and clarifies the scalability of the proposed algorithm. Although the apparatus behavior of each power device degradation looks similar, the microscopic observation of the transistors is diffe…

**Figure 11.** Figure 11: Error distribution: The box-whisker plots of prediction error for five power modules. then the average of whole test sets is picked. These results indicate that our proposed approach can improve the prediction accuracy exponentially by increasing the edge node and pow…

**Figure 12.** Figure 12: Aggregated training: The ∆Rds(on) prediction error is decreased exponentially by increasing the training device per each batch. This aggrigated training will help the Deep RACE to generalize the different transistor degradation behavior. The region of ∆Rds(on) < 0.02Ω…

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