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REVIEW 4 major objections 6 minor 99 references

A Review on Quantum Computing: Qubits, Cryogenic Electronics and Cryogenic MOSFET Physics

T0 review · 4 major / 6 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read This review argues that silicon qubits co-integrated with cryogenic CMOS control electronics are the credible route to scalable quantum computing, and that the missing physics for that route is band-tail tunneling in MOSFETs at 4 K.

desk verdict A readable review of silicon qubits and cryo-CMOS with one genuinely new kink-effect datapoint; the CNOT typo and unquantified scalability claims need fixing before it can be trusted. read the letter →

arxiv 1908.02656 v1 pith:DPLWWW4S submitted 2019-08-07 quant-ph physics.app-ph

Farzan Jazaeri , Arnout Beckers , Armin Tajalli , Jean-Michel Sallese This is my paper · ORCID
classification quant-phphysics.app-ph
keywords quantumcomputingsiliconqubitscryo-CMOScryogenicMOSFETmodelingsubthresholdswingsaturationband-tailtunnelingintegratedcircuitsdilutionrefrigerator
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper reviews the case for building scalable quantum computers on the silicon platform. It argues that the main obstacle is not the qubits themselves but the wiring: each qubit needs its own control line into a dilution refrigerator, and room-temperature electronics add latency, heat, and capacitance. The proposed fix is to move control and readout electronics inside the fridge using CMOS circuits operating at 4 K, and ultimately to co-integrate qubits and electronics on one chip as quantum integrated circuits. The review also claims that standard MOS transistor models fail below about 50 K and identifies the missing physics: a band-tail tunneling current that sets a new lower limit on the subthreshold swing. This points to silicon as a credible path to large-scale quantum computing built on the semiconductor industry's existing toolchain.

What carries the argument

The load-bearing object is the quantum integrated circuit (QIC): silicon qubits and their FET-based control and readout electronics sharing the same CMOS platform, with the electronics lifted from room temperature to the 4.2-K stage of the dilution refrigerator. The MOSFET physics that carries the argument rests on two pieces: Poisson-Boltzmann electrostatics corrected for incomplete ionization of body dopants, which keeps the Maxwell-Boltzmann approximation valid and lowers the threshold voltage compared with the freezeout picture, and a band-tail tunneling (hopping) current in weak inversion that runs parallel to drift-diffusion. Its quantitative core is the revised subthreshold-swing identity $SS = mW_t \ln 10$, where $W_t$ is the characteristic exponential band-tail extension in eV and $m$ is the slope factor including interface-trap density; this replaces the thermal limit $(k_BT/q)\ln 10$ below about 50 K.

What would settle it

Run a multi-qubit silicon array with cryo-CMOS front-end electronics at 4.2 K and measure both gate fidelity and total dissipated heat as qubits are added; if fidelity falls below the error-correction threshold once room-temperature wiring is eliminated, or if the electronics exceed the fridge's cooling power, the co-integration claim fails. For the MOSFET sub-claim, engineer devices with different band-tail widths and check whether the 4.2-K subthreshold swing follows $SS = mW_t \ln 10$ rather than the Boltzmann limit $(k_BT/q)\ln 10$.

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Extended reading notes

Core claim

On the paper's own terms, the central claim is that the silicon-based quantum-computing platform, built on CMOS-compatible spin qubits and deep-cryogenic FET electronics, is a credible route to the scale-up that superconducting platforms currently lack. The immediate obstacle is wiring: each qubit needs a dedicated control line from room temperature, and those lines bring thermal noise, capacitance, and latency. Moving the front-end electronics to the 4.2-K stage, and ultimately co-integrating qubits and transistors on one chip, would turn that obstacle into an integration problem that the semiconductor industry already knows how to solve. The review's specific physics claim is that MOSFETs at deep cryogenic temperatures cannot be modeled by simply extending room-temperature compact models: a band-tail tunneling (hopping) current flowing in parallel with drift-diffusion sets a new subthreshold-swing floor $SS = mW_t \ln 10$, and dopant freezeout in the channel is not what raises the threshold voltage. This is what a sympathetic reader would take the paper to be establishing.

Load-bearing premise

The entire quantum-integrated-circuit vision rests on the assumption that CMOS control and readout circuits can operate at 4 K inside a dilution refrigerator within its cooling-power budget while preserving qubit fidelity above error-correction thresholds.

Editorial extensions

If this is right

  • If the co-integration vision is right, the wiring bottleneck disappears: control and readout electronics sit centimeters from the qubits, cutting latency and accumulated capacitance that otherwise cap algorithm complexity.
  • Cryogenic MOSFET models must be rebuilt rather than extrapolated, because industry compact models that work at 77 K fail at 4.2 K, and QIC design needs DC, AC, RF, and noise models that include the cryogenic mechanisms.
  • Qubits could move from the roughly 10-mK stage to 4.2 K, where cooling power is orders of magnitude higher, letting more electronic functionality live near the qubits.
  • MOS-gate-only control via electric dipole spin resonance, especially with hole spin qubits, removes per-qubit wires and is a necessary step toward one-chip quantum integrated circuits.
  • Because silicon qubits are fabricated in CMOS-compatible processes, the existing semiconductor manufacturing toolchain can be leveraged directly, lowering the barrier to producing many qubits.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The review does not provide a system-level power budget, heat-load calculation, or yield analysis for a quantum integrated circuit, so the scalability claim should be read as a research direction rather than a demonstrated engineering result.
  • If band-tail tunneling is the true floor for the subthreshold swing, the same limit should appear in other disordered-channel transistor technologies at deep cryogenic temperatures, and a cross-technology measurement would test the mechanism beyond silicon.
  • A natural next experiment is a full cryo-CMOS-controlled multi-qubit array that measures gate fidelity and total dissipated power together, since both must clear the error-correction and cooling thresholds simultaneously.
  • The threshold-voltage argument, that freezeout does not explain the rise in $V_{th}$, suggests simple corrections to existing compact models rather than a completely new transport model for strong inversion.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. This invited review surveys silicon-based quantum computing, covering the basics of qubits and quantum gates (Section III), a comparison of qubit implementations with emphasis on silicon and CMOS-compatible qubits (Section IV), the concept of cryo-CMOS front-end electronics co-integrated with qubits to address the wiring bottleneck (Section V), and the device physics of MOSFETs at deep cryogenic temperatures (Section VI). The paper's thesis is that silicon qubits combined with cryogenic CMOS control and readout electronics form a credible path toward scalable quantum integrated circuits. It also reports, as a new observation, the kink effect in the output characteristics of a 28-nm bulk CMOS technology below 110 K (Figure 10).

Significance. If the co-integration vision in Section V is correct, the silicon/CMOS route offers a plausible industrial-scale path to quantum computing, and cryogenic MOSFET modeling becomes a critical enabling technology. The review usefully collects recent cryogenic device physics results, including the threshold-voltage behavior and the subthreshold-swing saturation explained by band-tail tunneling, and it provides a practical alert about the kink effect in advanced CMOS nodes. The strengths are the breadth of the survey and the explicit connection between qubit scaling and cryogenic electronics. However, the central scalability claim is not backed by quantitative system analysis, and the reliability of the cryogenic physics section rests largely on the authors' own prior publications without independent benchmarking. The new kink observation also lacks experimental detail. These gaps limit the review's current value as an authoritative assessment.

major comments (4)
  1. [Section III-E2, Eq. (2)] The CNOT matrix in Eq. (2) has an erroneous prefactor 1/sqrt(2); the correct CNOT gate is the 4x4 permutation matrix with a single 1 in each row and column and no prefactor, which is unitary. The printed matrix is not unitary and is therefore not a valid quantum gate. This is a fundamental error in a review whose purpose is to introduce quantum logic gates to readers, and it must be corrected.
  2. [Section V, Figure 5] The central scalability claim that cryo-CMOS front-end electronics can be integrated in the 4.2-K stage to resolve the wiring bottleneck is asserted but not supported by any system-level power or thermal analysis. The text cites prototype demonstrations [23]-[30], but it does not quantify the total dissipated power of the AWG, mixers, multiplexers, and LNAs, the heat load added by cabling, the available cooling power at 4.2 K (typically of order 1 W), or the thermal isolation between the 4.2-K and 10-mK stages. The proposal to raise qubit operating temperature to 4.2 K is made without citing a demonstration of high-fidelity silicon qubit operation at that temperature. Because the abstract and Section V present co-integration as the paper's core promise, this missing analysis is a load-bearing gap.
  3. [Section VI, Figures 6-9] The physical explanations of threshold-voltage increase and subthreshold-swing saturation are presented as established results, but they derive almost entirely from the authors' own references [53], [62], [79], and [81], with Figures 6-9 adapted from those works. No independent measurement or benchmark is provided in this review, and the text does not explicitly state that these are recent, still-debated results rather than settled textbook physics. For a review, reliance on the authors' own body of work is acceptable only if clearly framed as such; the current presentation risks overstating the consensus status of these cryogenic MOSFET models.
  4. [Section VI, Figure 10] The kink effect in 28-nm bulk CMOS at deep cryogenic temperatures is claimed as a first-time observation ('shown for the first time here in Fig. 10'), but no measurement protocol, device dimensions, number of devices tested, temperature steps, or error bars are reported. Without these details, the claim cannot be independently assessed, and the subsequent design advice to limit bias voltage around the kink lacks quantitative grounding. The authors should either provide measurement details or explicitly label this as a preliminary observation from ongoing work.
minor comments (6)
  1. [Section II] The phrase 'to factorize a number of N' should read 'to factorize a number N'.
  2. [Section IV-E] The duplicated phrase 'RF reflectometry technique RF reflectometry technique' should be reduced to a single instance.
  3. [Section IV-E] The sentence 'we have to different situations' should be 'we have two different situations'.
  4. [Section V] The word 'monolothically' is a typo for 'monolithically'.
  5. [Introduction] The word 'nefast' is non-standard English; use 'detrimental' or 'harmful'.
  6. [Section III-D] The statement that a π/2-pulse time is t = π/(2ω), with ω the driving-field angular frequency, conflates the driving frequency with the Rabi frequency; the pulse length depends on the Rabi frequency. This is a simplification that should be clarified or corrected.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the paper is a review that attributes its physics explanations to prior external publications, including self-authored but independently falsifiable works, and its one new result is an observation, not a prediction derived from fitted inputs.

full rationale

The manuscript is a review, not a closed derivation. Section VI's claims about Maxwell-Boltzmann validity, threshold-voltage enhancement, and subthreshold-swing saturation are explicitly attributed to prior works ([53], [62], [79], [81]) and are presented as summaries of external derivations and measurements, not as predictions generated from parameters fitted in this paper. The cited self-authored works are not shown to include the review's conclusions as inputs; no equation in this paper is shown to reduce to its own input by construction. The only new experimental content, the 28-nm kink effect in Fig. 10, is an observation ('shown for the first time here'), with no fitted parameter renamed as a prediction. The scalability vision in Section V is an architectural proposal supported by citations to prototype demonstrations, and while the power-budget issue is not analyzed, that is a completeness/correctness concern, not circularity. No self-definitional, fitted-input-as-prediction, ansatz-smuggling, or uniqueness-imported step is identifiable from the text.

Assumptions & free parameters 1 free parameters · 4 assumptions · 0 invented entities

The paper is a review, so the central thesis rests mostly on cited literature rather than on derivations in this manuscript. The main assumptions are the validity of Boltzmann statistics at cryogenic temperatures, complete ionization of source/drain dopants, the band-tail hopping explanation for subthreshold swing saturation, and the feasibility of cryo-CMOS co-integration. The only explicit parameter used in a presented formula is the band-tail energy Wt.

free parameters (1)
  • Wt (band-tail characteristic energy) = a couple of meV (typical, from ref [82])
    Used in the presented subthreshold-swing saturation limit SS = m Wt ln 10 in Section VI; its value is adopted from cited measurements, not derived in this paper.
assumptions (4)
  • domain assumption The Maxwell-Boltzmann approximation of Fermi-Dirac statistics remains valid for non-degenerate doping at deep-cryogenic temperatures.
    Invoked in Section VI to justify the Poisson-Boltzmann equation as the basis for cryogenic MOSFET electrostatics; cited to self-ref [53].
  • domain assumption Source and drain dopants are completely ionized at all temperatures due to heavy doping effects.
    Assumed in Section VI for the cryogenic MOSFET model; cited to refs [59], [60].
  • domain assumption The saturation of the subthreshold swing at deep-cryogenic temperatures is caused by an additional band-tail hopping current in parallel with drift-diffusion current.
    Presented in Section VI as the explanation for Delta-SS, based on self-cited ref [81]; no independent experimental confirmation is cited in this review.
  • domain assumption Cryogenic CMOS front-end electronics can be co-integrated with qubits at 4 K within the thermal and power budget of a dilution refrigerator.
    Underlies the scalability thesis in Section V; the review points to prototypes (e.g., [30]) but provides no system-level thermal or power analysis.

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Cite this review

Pith. "Pith review of A Review on Quantum Computing: Qubits, Cryogenic Electronics and Cryogenic MOSFET Physics." pith.science (2026). https://pith.science/paper/DPLWWW4S

@misc{pith2026190802656,
  author       = {Pith},
  title        = {Pith review of: A Review on Quantum Computing: Qubits, Cryogenic Electronics and Cryogenic MOSFET Physics},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/DPLWWW4S}},
  note         = {Machine review of arXiv:1908.02656}
}
read the original abstract

Quantum computing (QC) has already entered the industrial landscape and several multinational corporations have initiated their own research efforts. So far, many of these efforts have been focusing on superconducting qubits, whose industrial progress is currently way ahead of all other qubit implementations. This paper briefly reviews the progress made on the silicon-based QC platform, which is highly promising to meet the scale-up challenges by leveraging the semiconductor industry. We look at different types of qubits, the advantages of silicon, and techniques for qubit manipulation in the solid state. Finally, we discuss the possibility of co-integrating silicon qubits with FET-based, cooled front-end electronics, and review the device physics of MOSFETs at deep cryogenic temperatures.

Figures

Figures reproduced from arXiv: 1908.02656 by the authors.

Figure 1
Figure 1. The basic unit of information in a QC is the quantum bit (qubit) [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. The Bloch sphere provides a useful means of visualizing the state of a [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Schematic of a double quantum dot system. From Corna [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (6 more)
Figure 4
Figure 4. Figure 4: Network of tunnel resistors and capacitors representing two quantum [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 5
Figure 5. Figure 5: Simplified schematic showing the front-end electronic circuits required for controlling (‘writing’) and measuring (‘reading’) spin qubits. [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]
Figure 6
Figure 6. Figure 6: Fermi level position in the bandgap at cryogenic temperatures for silicon MOSFET with a [PITH_FULL_IMAGE:figures/full_fig_p007_6.png]
Figure 8
Figure 8. Figure 8: Low-temperature measurement results in a minimum-length device of [PITH_FULL_IMAGE:figures/full_fig_p008_8.png]
Figure 9
Figure 9. Figure 9: MOSFET band diagrams at 4.2 K (a) flatband, (b) weak inversion. Adapted from [62]. [PITH_FULL_IMAGE:figures/full_fig_p009_9.png]
Figure 10
Figure 10. Figure 10: The kink effect sets in below T = 110 K and above VDB = 0.9 V in the output characteristics of a commercial 28-nm bulk CMOS technology. REFERENCES [1] https://ai.google/research/teams/applied-science/quantum-ai/. [2] https://cloudblogs.microsoft.com/quantum/2018/06/06…

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Pith tools

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