Practical Active Disturbance Rejection Control: Bumpless Transfer, Rate Limitation and Incremental Algorithm

Gernot Herbst

REVIEW 1 major objections 5 minor 22 references

Practical Active Disturbance Rejection Control: Bumpless Transfer, Rate Limitation and Incremental Algorithm

T0 review · 1 major / 5 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read This paper gives step-by-step ADRC implementations that switch control modes without signal bumps and survive magnitude and rate limits.

desk verdict Useful practical ADRC implementation paper with a real hole in the bumpless b0-change recipe for non-transformed variants. read the letter →

arxiv 1908.04610 v1 pith:YRJ6CP42 submitted 2019-08-13 eess.SY cs.SY

Gernot Herbst This is my paper · ORCID

classification eess.SYcs.SY

keywords activedisturbancerejectioncontrolADRCincrementalalgorithmbumplesstransferratelimitationanti-windupextendedstateobserverdiscrete-time

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Active disturbance rejection control (ADRC) is attractive because it treats model error and real disturbances as one generalized disturbance to be estimated and cancelled. The paper's claim is that ADRC can be made fully practical: it gives a discrete-time recipe in which the controller can be run in incremental form, its output can be limited in magnitude and rate without windup, and it can be switched on, switched between controllers, or have its parameters changed without jumps in the control signal. The three load-bearing additions are an incremental ADRC update law, a carry-over term in the incremental limiter, and a set of state-reinitialisation formulas for bumpless parameter changes. The paper demonstrates all of it on a simulated current-mode buck converter.

What carries the argument

The machinery is the discrete-time extended state observer (ESO), which estimates output, derivatives, and the generalised disturbance in one update, plus a controller that uses the estimated states to cancel that disturbance. On top of this, the paper builds an incremental variant in which the controller outputs an increment of the control signal, and a magnitude/rate limiter that clips both the absolute level and the step size of that increment. The load-bearing part is the carry-over term in Eq. (22), $\Delta u(k-1) - \Delta u_{\mathrm{lim}}(k-1)$, which feeds the clipped control effort back into the next increment so the controller keeps aiming at the value it would have chosen without the limiter. Bumpless transfer is carried by the state initialisation and parameter rescaling formulas in Sect. V.

What would settle it

Let the incremental ADRC from Eq. (22) act on a plant with a known pole at the origin, drive the reference so that the rate limiter stays active for many closed-loop time constants, and record the accumulated carry-over term: if $|\Delta u(k-1)-\Delta u_{\mathrm{lim}}(k-1)|$ grows without bound or the output shows a limit cycle, the anti-windup claim fails. Equivalently, an analytical stability test of the saturated loop with the carry-over term would settle the question.

Watch

Extended reading notes

Core claim

The central claim is a complete implementation scheme for discrete-time ADRC with the practical features an industrial loop needs. For the incremental form, Eq. (22) adds the difference between the desired and the actually applied control increment at the previous step to the current increment, so the forgotten control effort is not lost when saturation or rate limiting clips the command. For bumpless transfer, the paper gives explicit formulas: initialise the observer state from the measured output and last control value (Sect. V-A), initialise the incremental term from the previous reference and limited control value when enabling the controller (Sect. V-B), and rescale the state vector and observer matrices according to the changed controller, observer, or plant-model parameter (Sect. V-C). With these steps, switching modes or changing parameters at steady state produces no visible bump in output or control signal, as the simulations in Sect. VI confirm.

Load-bearing premise

The anti-windup and bumpless behaviour rests on the assumption that feeding the limited control signal back into the observer keeps the observer's internal model consistent with the real plant, and that the carry-over term in Eq. (22) stays bounded and does not destabilise the loop during prolonged saturation; this is shown in simulation, not proven analytically.

Editorial extensions

If this is right

A practitioner can implement ADRC in either non-incremental or incremental form, with or without magnitude and rate limiting, using only the equations collected in the paper.
Rate limiting becomes a practical tool for ADRC: it bounds how fast the control signal can rise after reference or disturbance steps and also attenuates measurement noise in the control signal.
Incremental ADRC can share a common limiting integrator with other incremental controllers, so switching between, say, incremental PI control and incremental ADRC is done without jumps.
Controller and observer parameters can be changed online while the loop is running, provided the state vector is rescaled according to Sect. V-C and the change is made at steady state with $r = y$.
The anti-windup property of feeding the limited control signal into the observer is preserved for both magnitude and rate limits.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The promise of bumpless parameter changes is stated for steady state with $r = y$; a natural extension the author leaves implicit is a formal derivation of the state rescaling for changes during transients, where the formulas would need to account for the current tracking error.
The carry-over term in Eq. (22) is an integral-like memory of clipped control effort; this suggests the incremental ADRC with limiter has a natural connection to classical conditional-integration anti-windup schemes, and could be compared against them on the same benchmark.
A hardware test on a real converter or servo drive would be the next step beyond simulation; the paper's noise example already hints that rate limiting can double as a noise filter, which is worth quantifying separately.
One could test whether the same bumpless formulas extend to adaptive or nonlinear ADRC variants, since the observer-state rescaling logic does not depend on the linear bandwidth parameterisation.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Short version: this is a genuinely useful practical paper, and the incremental ADRC plus the carry-over term are real contributions. But the bumpless b0-change recipe for the non-transformed variants has a hole that the paper's own conclusion overstates.

The incremental formulation in Sect. III is a clean algebraic repackaging of the observer/controller equations, and Eq. (22) is a sensible anti-windup carry-over for the incremental case. The paper is also honest about its assumptions: steady state at transfer time, no formal stability proof for the limited loop. For what it claims to be—implementation guidelines for drives and power electronics—it is largely sound. The simulations are simple but support the qualitative claims. The citation pattern is reasonable; [17] is the right source for the lag-reduced form.

The soft spot is Sect. V-C.3. For the transformed/lag-reduced variants the recipe works because the state transform absorbs b0 and w stays all-ones. For the standard non-transformed variants of Sect. II-B/C, the control law (9) uses w^T=(Kp,1)/b0 (or (Kp,Kd,1)/b0). When b0 changes, the text rescales B_d, B_ESO, and the last observer state, but never says to recompute w (or the Kp/b0 feedforward term) with the new b0. Following the instructions literally, a stationary-state calculation gives the control signal scaled by b0_new/b0_old immediately after the change—exactly the bump the section is supposed to prevent. The incremental variants partly dodge this because (27) is recomputed with the updated b0 and w, but the non-incremental standard variant is left incomplete. That is a genuine gap, and it is in one of the three headline contributions, not a side remark.

Is it fatal? No. It is a missing line in an otherwise careful recipe, and the fix is obvious: recompute w and the feedforward coefficient with the new b0 before applying (31). The observer rescaling logic is otherwise consistent. The paper's central claim—'all steps are described for all four implementations'—is too strong as written, but the core material is worthwhile.

I'd send it to a serious referee; the incremental form and the carry-over term deserve scrutiny, and a referee can flag the b0 recipe. It is not a desk reject. But the author should be asked to fix V-C.3 before final.

Referee Report

1 major / 5 minor

Summary. The paper presents practical implementation recipes for discrete-time active disturbance rejection control (ADRC), covering an incremental formulation, magnitude and rate limiting, and bumpless transfer between manual/automatic modes and during parameter changes. The new contributions are the incremental ADRC equations (16)-(19), the carry-over term in Eq. (22) for limited incremental control, and the bumpless parameter-change formulas in Section V-C. The claims are supported by a buck-converter simulation study in Section VI.

Significance. If the recipes are correct, the paper fills a genuine gap for practitioners by turning standard ADRC into an implementation-oriented package with explicit step-by-step instructions, including the rarely treated rate limiting. The incremental formulation and the carry-over term are plausibly new and practically useful. The derivations are largely algebraic and consistent with established anti-windup practice (Aström and Rundqvist, Ref. [20]). However, the completeness claim that 'all steps are described' for all four ADRC variants is weakened by an omission in the b0-change recipe for the non-lag-reduced variants.

major comments (1)

[Sect. V-C.3, Eqs. (29)-(31)] The recipe for changing b0 does not state that the control-law gain vector w^T in Eq. (5)/(9) must be recomputed for the non-transformed (standard) ADRC variants. Since w^T contains an explicit 1/b0 factor, following the text literally leaves w with the old b0. In a stationary state with r=y, the control signal after the change scales as u' = (b0_new/b0_old) * u_old, producing a jump whenever b0 changes, which contradicts the paper's bumpless-transfer claim. The transformed/lag-reduced variant avoids this through the rescaling in Eq. (30), but the non-transformed non-incremental and incremental variants are left incomplete. The fix is a one-sentence instruction to recompute w^T with the new b0, and similarly to use the new w in Eq. (27) when reinitializing Δu(k-1); as written, the paper's strongest claim is not met for these variants.

minor comments (5)

[Sect. VI-D] The simulation study does not include an example of a b0 change as described in Sect. V-C.3, despite b0 changes being one of the three parameter-change categories; adding such an example would increase confidence in the recipe.
[Sect. V-C.3] The sentence 'changing b0 only results in a scaling factor (T^{-1} · T_old = b0_old / b0)' is easy to misread; the intended factor is the ratio b0^old/b0, and the notation should be made explicit, e.g., using a superscript 'old' throughout.
[References] Ref. [20] spells the second author's name 'Rundqwist'; the correct spelling is 'Rundqvist'.
[Fig. 14 caption] The phrase '400 % increased closed-loop settling time' is ambiguous; it should state the old and new settling times explicitly (e.g., 'from 2 ms to 10 ms').
[Sect. IV, Eq. (22)] A brief intuitive explanation of why the carry-over term prevents stationary error during limiting would be helpful; currently the anti-windup rationale is implicit.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: incremental and bumpless-transfer equations are algebraic implementation identities, not fitted predictions.

full rationale

The paper's derivations are algebraic implementation recipes rather than empirical predictions. The incremental ADRC equations (16)-(19) are obtained by direct substitution into the standard discrete-time observer and control law: (17) is substituted into (7) to get (16), and (19) is substituted into (9) to get (18). This is an identity transformation, not a fitted input called a prediction. The carry-over term in Eq. (22) is introduced as a design mechanism to preserve the desired control signal during limitation; it is not derived from data and does not smuggle in the target result. The bumpless-transfer initialization (27) sets the previous increment so that the first enabled control output matches the manual value; this is by construction, but as an implementation recipe and not as a circular proof of a separate claim. The lag-reduced form and the windup discussion are cited from the author's prior work [17], but the central new contributions (incremental formulation, rate limitation, bumpless parameter changes) do not reduce to that citation; the lag-reduced variant is presented as an optional alternative, and the paper's own equations for the non-lag-reduced variants stand independently. The skeptic's noted gap in Sect. V-C.3, where the control-law gain w is not explicitly recomputed after a b0 change in the non-transformed variants, is a completeness or correctness concern, not a circularity. No fitted parameters appear, and no prediction is equivalent to its own input. Overall, the derivation chain is self-contained apart from ordinary background citations, so the circularity score is 0.

Assumptions & free parameters 0 free parameters · 4 assumptions · 0 invented entities

No free parameters are fitted to data; the controller gains and observer gains are set by standard pole-placement design rules. The paper introduces no new physical entities. Its contributions rely on standard control assumptions and one explicit stationarity assumption for bumpless transfer.

assumptions (4)

domain assumption The plant can be represented as a low-order integrator chain with a generalized disturbance f(t) that the extended state observer can estimate.
This is the foundation of ADRC (Sect. II-A) and is assumed without proof; it limits the applicability to plants dominated by low-order dynamics.
domain assumption Feeding the limited control signal into the observer prevents integral windup (Sect. IV, citing [20]).
This is a standard anti-windup technique applied to ADRC; the paper relies on it for the non-incremental and incremental limiter designs.
domain assumption Bumpless transfer guidelines assume stationary state with r=y (Sect. V).
The paper states this assumption explicitly; parameter changes and enabling are proven to be bumpless only under this condition.
standard math Zero-order hold discretization of the continuous-time plant matrices is valid.
Standard discretization method (Sect. II-B) that is conventional for digital control.

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Cite this review

Pith. "Pith review of Practical Active Disturbance Rejection Control: Bumpless Transfer, Rate Limitation and Incremental Algorithm." pith.science (2026). https://pith.science/paper/YRJ6CP42

@misc{pith2026190804610,
  author       = {Pith},
  title        = {Pith review of: Practical Active Disturbance Rejection Control: Bumpless Transfer, Rate Limitation and Incremental Algorithm},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/YRJ6CP42}},
  note         = {Machine review of arXiv:1908.04610}
}

read the original abstract

Practical applications of controllers often impose further requirements on the implementation beyond the actual control performance, such as the ability to switch between manual and automatic control or between different control laws or controller parameter settings, known as bumpless transfer. Another common requirement is to limit the control signal in magnitude and/or rate. This article examines and extends several discrete-time variants of active disturbance rejection control (ADRC), which is increasingly being applied especially in the field of power electronics and drives, in this regard. Detailed guidelines for practical ADRC implementations with these abilities are presented, and all features are being demonstrated with the help of simulation examples.

Figures

Figures reproduced from arXiv: 1908.04610 by the authors.

**Figure 3.** Discrete-time control law as given in (9). [PITH_FULL_IMAGE:figures/full_fig_p002_3.png] view at source ↗

**Figure 5.** Discrete-time extended state observer with incremental output as given [PITH_FULL_IMAGE:figures/full_fig_p003_5.png] view at source ↗

Figures from the paper (6 more)

**Figure 6.** Figure 6: Discrete-time magnitude and rate limiter. [PITH_FULL_IMAGE:figures/full_fig_p004_6.png]

**Figure 9.** Figure 9: Discrete-time control law (22) with incremental output and feedback [PITH_FULL_IMAGE:figures/full_fig_p004_9.png]

**Figure 10.** Figure 10: Structure and implementation of a control loop based on discrete-time [PITH_FULL_IMAGE:figures/full_fig_p005_10.png]

**Figure 11.** Figure 11: Example A: Rate limitation of the control signal [PITH_FULL_IMAGE:figures/full_fig_p006_11.png]

**Figure 12.** Figure 12: Example B: Bumpless transfers from manual mode (in stationary [PITH_FULL_IMAGE:figures/full_fig_p007_12.png]

**Figure 14.** Figure 14: Example D: Performing bumpless parameter changes according [PITH_FULL_IMAGE:figures/full_fig_p008_14.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

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Pith tools

Reviewed August 14, 2026 · model on record in the stance chip above.

[1] [17]

A simulative study on active disturbance rejection control (ADRC) as a control tool for practitioners,

G. Herbst, “A simulative study on active disturbance rejection control (ADRC) as a control tool for practitioners,” Electronics, vol. 2, no. 3, pp. 246–279, 2013

work page 2013

[2] [20]

Integrator windup and how to avoid it,

K. J. ˚Astr¨om and L. Rundqwist, “Integrator windup and how to avoid it,” in American Control Conference , 1989, pp. 1693–1698

work page 1989

[3] [1]

From PID to active disturbance rejection control,

J. Han, “From PID to active disturbance rejection control,” IEEE Transactions on Industrial Electronics, vol. 56, no. 3, pp. 900–906, 2009

work page 2009

[4] [2]

Active disturbance rejection control: A paradigm shift in feedback control system design,

Z. Gao, “Active disturbance rejection control: A paradigm shift in feedback control system design,” in Proceedings of the 2006 American Control Conference, 2006, pp. 2399–2405

work page 2006

[5] [3]

On the centrality of disturbance rejection in automatic control,

——, “On the centrality of disturbance rejection in automatic control,” ISA Transactions, vol. 53, no. 4, pp. 850–857, 2014

work page 2014

[6] [4]

Tuning method for second-order active disturbance rejection control,

X. Chen, D. Li, Z. Gao, and C. Wang, “Tuning method for second-order active disturbance rejection control,” in Proceedings of the 30th Chinese Control Conference, 2011, pp. 6322–6327

work page 2011

[7] [5]

Modiﬁed active disturbance rejection control for time-delay systems,

S. Zhao and Z. Gao, “Modiﬁed active disturbance rejection control for time-delay systems,” ISA Transactions , vol. 53, no. 4, pp. 882–888, 2014

work page 2014

[8] [6]

On active disturbance rejection control: Stability analysis and applications in disturbance decoupling control,

Q. Zheng, “On active disturbance rejection control: Stability analysis and applications in disturbance decoupling control,” Ph.D. dissertation, Cleveland State University, Department of Electrical and Computer Engineering, 2009

work page 2009