MobiSR: Efficient On-Device Super-Resolution through Heterogeneous Mobile Processors

{\L}ukasz Dudziak; Nicholas D. Lane; Royson Lee; Sourav Bhattacharya; Stylianos I. Venieris

REVIEW 3 major objections 3 minor 66 references

MobiSR: Efficient On-Device Super-Resolution through Heterogeneous Mobile Processors

T0 review · 3 major / 3 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read MobiSR claims that a difficulty-aware scheduler using total variation can cut on-device super-resolution latency by 2.13x to 4.79x while staying within a user-specified PSNR drop.

desk verdict MobiSR is a genuinely useful mobile SR scheduling system, but the abstract's 2.13x/4.79x speedups are unconstrained averages; the equal-quality speedups in Fig. 10 are at most ~1.94x. read the letter →

arxiv 1908.07985 v1 pith:DGU2ZZOT submitted 2019-08-21 cs.CV cs.DC

Royson Lee , Stylianos I. Venieris , {L}ukasz Dudziak , Sourav Bhattacharya , Nicholas D. Lane This is my paper · ORCID

classification cs.CVcs.DC

keywords super-resolutionon-deviceinferenceheterogeneousmobileprocessorsdifficulty-awareschedulingtotalvariationmodelcompressionPSNR-latencytrade-offdesignspaceexploration

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

MobiSR sets out to show that on-device super-resolution can be made much faster by treating image patches differently: easy patches go to a large, accurate model, while hard patches go to a compact, low-precision model. The paper's central assertion is that a patch's total variation is a usable run-time proxy for its upscaling difficulty, so a simple threshold can dispatch patches without exceeding a user-set average PSNR budget. The framework automatically searches compressed variants of a supplied super-resolution network, prunes to Pareto-optimal models per compute engine, and tunes the threshold to minimize latency subject to the error tolerance. On a mobile SoC with CPU, GPU, and DSP, the resulting two-model designs achieve an average speedup of 2.13x over parallel difficulty-unaware mappings and 4.79x over single compute engine implementations. If right, this gives mobile zoom and image-upscaling applications a practical path to local processing with bounded quality loss.

What carries the argument

The load-bearing mechanism is the total-variation threshold scheduler. Total variation (TV) is the sum of absolute intensity differences between neighboring pixels in a patch, and the scheduler computes it per patch at run time; if $TV(p) \le TV_{\mathrm{thr}}$ the patch is sent to the larger model on the PSNR-preserving engines (CPU/GPU), otherwise to the compact model on the low-precision engine (DSP), with load balancing across engines and an overflow rule that lets hard patches fall back to the large model when the DSP is busy. The threshold $TV_{\mathrm{thr}}$ is not hand-set: a calibration set is used to estimate the domain's TV range, and the optimization over model pairs and thresholds is driven by an analytical performance model that estimates per-engine latency from measured per-patch execution times. The design space itself is generated by model transformations—residual bottlenecks, group, depthwise-separable, and separable convolutions, inverted residuals, channel shuffle, and channel split—which are pruned per engine to the Pareto front.

What would settle it

Run both candidate models on every patch of a held-out dataset that differs from the calibration set, compute per-patch PSNR against the full-precision large model, and count high-TV patches where the compact model's PSNR drop exceeds the user tolerance; if this fraction is large, the TV-threshold scheduler cannot meet its quality constraint, and the reported speedup at fixed quality would not transfer.

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Extended reading notes

Core claim

The discovery is that image patches differ systematically in how much a large super-resolution model outperforms a compact one, and that this difference tracks total variation. For low-TV (easy) patches the large model wins by a meaningful margin, so those patches should be sent to it; for high-TV (hard) patches the two models are nearly equally weak, so sending them to a fast compact model costs little quality and saves time. MobiSR turns this into a deployable system: it generates a family of compressed models from a user-supplied network, measures their latency on each compute engine, keeps only Pareto-optimal (model, engine) pairs, and then selects two models and a TV threshold that minimize estimated latency while keeping average PSNR within a user-specified drop. The quantitative claim is an average speedup of 2.13x over highly optimized parallel difficulty-unaware mappings and 4.79x over highly optimized single-engine implementations, measured on one mobile SoC.

Load-bearing premise

Total variation of a patch is a reliable run-time proxy for how hard that patch is to upscale, and on hard patches the compact model's quality loss is small enough that the user's average PSNR budget is still met.

Editorial extensions

If this is right

For a fixed error tolerance, an on-device SR system can run faster by splitting the image by difficulty rather than running one model on all patches.
The framework's reported speedups are 2.13x over parallel difficulty-unaware mappings and 4.79x over single-engine implementations, with larger speedups as the allowed PSNR drop increases.
Because the optimization is parametrized by the target SoC's compute engines, the same procedure applies to newer chips with neural accelerators, not only to CPU/GPU/DSP designs.
The Pareto-front pruning and the constraint that the fast model be more compact than the accurate model keep the design search small enough to be exhaustive.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

Beyond the paper: the scheduler's quality guarantee is average PSNR, not per-patch or worst-case quality; applications sensitive to artifacts in individual patches would need a stricter dispatch rule.
Beyond the paper: the measured speedups come from one mobile SoC; on newer heterogeneous chips the relative latencies of CPU, GPU, and DSP change, so the optimal model pair and threshold would shift, though the search and scheduling procedure should transfer.
Beyond the paper: a natural testable extension is to make the threshold content-adaptive per image or to learn it from a small labeled calibration set instead of a single global value, which could improve the quality-latency frontier.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Two things to know before you read: the system is real and well-engineered, and the headline numbers are not the equal-quality numbers. The core idea—a two-model heterogeneous schedule (accurate model on CPU/GPU, compact model on DSP) with a TV-based patch difficulty predictor—is a legitimate contribution. The design-space search over compressed models is coherent, the Eq. (12) optimization is properly formulated, and the evaluation is genuine: SNPE measurements on a Snapdragon 845, four standard SR datasets, latency and PSNR both reported. The image-level TV correlation in Figs. 3–5 is reasonable evidence for the proxy, and the paper is honest about the scheduler's load-balancing behavior.

The soft spot is the performance claim. The 2.13x/4.79x averages in Table 3 and the abstract are computed without enforcing the PSNR constraint that Eq. (12) is supposed to enforce. They are averaged over TV thresholds, including operating points that violate the user's error budget. When the PSNR budget is actually held fixed (Fig. 10), the speedups drop to at most 1.47x on Set5, 1.78x on Set14, 1.94x on B100, and 1.29x on Urban100. That is still a useful gain—especially for a fully on-device system—but it is not 4.79x. A revised abstract should lead with the equal-quality numbers.

Two smaller issues. First, the TV threshold selection is not clearly held out from the test benchmarks; the paper mentions a calibration set but never shows the calibration split or the sensitivity of the chosen threshold. Second, the baselines are all variants of their own models in single-engine or unconstrained parallel mode. They do not compare against CARN-M or FSRCNN, which are the relevant efficient SR baselines. The citation pattern otherwise looks solid, and the related-work positioning against cascades and early-exit classifiers is fair.

Bottom line: this deserves a serious referee and probably acceptance after revision. The framework is sound, the evaluation is extensive, and the central mechanism holds up. What needs fixing is the reporting: separate the unconstrained speedup from the equal-quality speedup, provide the calibration protocol, and add at least one external efficient SR baseline. I would bring it to a reading group and cite it if I worked on mobile SR systems.

Referee Report

3 major / 3 minor

Summary. The paper presents MobiSR, a framework for on-device super-resolution that combines two compressed SR models with a runtime scheduler. The scheduler uses the total variation (TV) of each image patch as a proxy for upscaling difficulty, dispatching easy patches to a larger, more accurate model on the CPU/GPU and hard patches to a compact, quantized model on the DSP, with load balancing. Offline, the framework explores model compression transformations and selects a model pair and a TV threshold to minimize latency subject to a user-specified PSNR drop constraint, formalized as the optimization problem in Eq. (12). The authors report average speedups of 2.13x over optimized parallel difficulty-unaware mappings and 4.79x over single-engine implementations on a Snapdragon 845 board, with additional measurements across Set5, Set14, B100, and Urban100.

Significance. The paper addresses a practically relevant systems problem: efficient on-device super-resolution under a quality constraint. Its strengths are concrete: the evaluation uses real measurements on the Snapdragon 845 via SNPE, the design-space exploration with compression transformations is clearly described, and Fig. 10 honestly reports speedups as a function of allowed PSNR degradation. If the central speedup claim is properly connected to the quality constraint, the work would be a useful contribution to mobile systems and embedded deep learning. However, the headline numbers in the abstract and Table 3 are not computed under the equal-quality protocol used in Fig. 10, and the TV-based difficulty proxy is validated only at the image level while being applied at the patch level. These issues affect the central claim and require revision.

major comments (3)

[Abstract; Table 3; Section 4.4, Fig. 10] The headline speedups of 2.13x and 4.79x are not supported by the equal-quality evaluation. Table 3 reports speedup ranges and averages over TV threshold values without reporting the PSNR drop at each operating point, so the averages mix configurations that violate the Eq. (12) constraint with those that satisfy it. In contrast, Fig. 10, which compares systems at the same PSNR drop, shows maximum speedups of 47%, 78%, 94%, and 29% on Set5, Set14, B100, and Urban100, respectively. The abstract should either report speedups under the PSNR constraint or clearly label the Table 3 numbers as unconstrained operating points.
[Section 3.3, Eq. (9), Fig. 4] The TV-based difficulty criterion is validated at the image level on DIV2K, but the scheduler operates on individual patches. The paper does not provide patch-level evidence that high-TV patches are indeed nearly equally hard for the large and compact models, nor does it describe a held-out calibration protocol for selecting TV_thr. Because the scheduler's quality guarantee depends on this transfer, the authors should add a patch-level analysis (e.g., PSNR difference vs. TV for patches) and an explicit calibration/validation split for threshold selection.
[Section 3.4, Eq. (11); Algorithm 1] The performance model in Eq. (11) assumes that patches are assigned to m1 or m2 solely by the TV threshold, but Algorithm 1 allows hard patches to be processed by m1 when the DSP is oversubscribed. This means the analytic latency estimate can understate the running time by assuming more DSP utilization than the scheduler actually provides. The authors should either incorporate the load-balancing policy into the performance model or justify that the discrepancy is negligible for the evaluated configurations.

minor comments (3)

[Fig. 9 caption] The caption reads 'SDM854' but the platform is Snapdragon 845 (SDM845); this typo should be corrected.
[Section 4.4, Fig. 10] The x-axis of Fig. 10 is described only as 'error degradation'; the exact PSNR drop values used for each interval are not stated in the text, making it hard to assess which operating points are of practical interest.
[Table 3] The table would be easier to interpret if it also reported the PSNR drop of each configuration at the listed speedups, or if the speedups were restricted to configurations satisfying the Eq. (12) constraint.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity; MobiSR is an empirically benchmarked systems paper with an independently measured central claim.

full rationale

MobiSR is an empirical systems paper, not a derivation: the central speedup claim is measured on-device against external SR datasets and baselines, and the TV-based difficulty proxy is validated with DIV2K scatter plots rather than assumed from the target result. The optimizer in Eq. (12) tunes the TV threshold to meet a user-specified PSNR error tolerance, and Fig. 10 compares MobiSR against single-model baselines under matched PSNR-drop budgets, so the equal-quality comparison is not definitionally tied to the fitted threshold. The reader and skeptic concerns about Table 3 averaging speedups over thresholds without enforcing the PSNR constraint are validity or reporting concerns, not circularity: no equation or fitted parameter is renamed as a prediction. Self-citations such as [2] and [52] are background references and are not load-bearing for the paper's main claim. No load-bearing step reduces by construction to its own input, and no uniqueness or ansatz is imported via self-citation.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

The paper introduces no new physical or mathematical entities. The free parameters are the TV threshold, compression ratios, and patch size; the central speedup claim depends on these choices. The load-bearing assumptions are empirical correlations between total variation and SR quality, which are plausible but only shown at image level on DIV2K.

free parameters (3)

TV_thr (total-variation threshold) = Per-dataset values not reported numerically; shown as sweeps in Fig. 9 and Table 3
The scheduler's hard/easy cutoff is selected to meet the PSNR budget; it is a fitted design parameter of the optimization in Eq. (12).
Compression hyperparameters (r, g, e) = r=2, r=4, g=4, g=16, e=2
The candidate model space is generated by hand-chosen ratios from the compression literature (Table 4), so the final selected pair and the reported speedups depend on this manually chosen candidate set.
Patch size = 90x160
Patch dimensions are fixed by hand in Section 4.1 and affect both TV calculations and load-balancing granularity.

assumptions (4)

domain assumption Total variation is a reliable proxy for upscaling difficulty.
Section 3.3, Eq. (9) and Figs. 3 and 5: used to classify patches as easy or hard; the supporting plot is image-level, on DIV2K.
domain assumption For hard-to-upscale patches, the large and compact models have similar PSNR, so the compact model can serve hard patches without breaking the average PSNR budget.
Section 3.3, Fig. 4: this empirical observation justifies sending hard patches to the weaker model; it is dataset-specific and not independently validated.
domain assumption Image-level TV-PSNR behavior transfers to individual patches at run time.
Algorithm 1 applies the TV criterion per patch, but the paper validates the relationship only at image level on DIV2K.
domain assumption SNPE latency measurements on the Open-Q 845 board are representative of the target mobile platform class.
Section 4.1: all latency numbers come from one SDK version and one development board; generalization to other SoCs is asserted, not measured.

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Cite this review

Pith. "Pith review of MobiSR: Efficient On-Device Super-Resolution through Heterogeneous Mobile Processors." pith.science (2026). https://pith.science/paper/DGU2ZZOT

@misc{pith2026190807985,
  author       = {Pith},
  title        = {Pith review of: MobiSR: Efficient On-Device Super-Resolution through Heterogeneous Mobile Processors},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/DGU2ZZOT}},
  note         = {Machine review of arXiv:1908.07985}
}

read the original abstract

In recent years, convolutional networks have demonstrated unprecedented performance in the image restoration task of super-resolution (SR). SR entails the upscaling of a single low-resolution image in order to meet application-specific image quality demands and plays a key role in mobile devices. To comply with privacy regulations and reduce the overhead of cloud computing, executing SR models locally on-device constitutes a key alternative approach. Nevertheless, the excessive compute and memory requirements of SR workloads pose a challenge in mapping SR networks on resource-constrained mobile platforms. This work presents MobiSR, a novel framework for performing efficient super-resolution on-device. Given a target mobile platform, the proposed framework considers popular model compression techniques and traverses the design space to reach the highest performing trade-off between image quality and processing speed. At run time, a novel scheduler dispatches incoming image patches to the appropriate model-engine pair based on the patch's estimated upscaling difficulty in order to meet the required image quality with minimum processing latency. Quantitative evaluation shows that the proposed framework yields on-device SR designs that achieve an average speedup of 2.13x over highly-optimized parallel difficulty-unaware mappings and 4.79x over highly-optimized single compute engine implementations.

Figures

Figures reproduced from arXiv: 1908.07985 by the authors.

**Figure 2.** MobiSR’s processing flow. optimizations, but also on the model and the level of quantization involved. Therefore, a key challenge in accelerating SR models is selecting appropriate convolution-approximation techniques based on both their impact on the accuracy of the given model and their efficient mapping on the available compute engines. 3 MobiSR In this section, we present the high-level flow of MobiSR followed … view at source ↗

**Figure 2.** The framework is supplied with a high-level descrip [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗

**Figure 3.** Low-resolution images along with their TV [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗

Figures from the paper (5 more)

**Figure 5.** Figure 5: TV of low-resolution images from the DIV2K [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]

**Figure 6.** Figure 6: We reduce the number of feature maps in RCAN to improve processing speed. Conv(S,D,K) is a K×K convolution with S input and D output feature maps. Implementation Details. All SR designs presented in this section were run on SDM845 using the high-performance profile of …

**Figure 7.** Figure 7: PSNR vs CPU latency of MobiSR-generated models on SDM845 (×4 upscaling on Urban100). model,mref, as RCAN yields the state-of-the-art performance based on PSNR/SSIM among large-scale SR models. In order for RCAN to be comparable to existing state-of-the-art mobile SR m…

**Figure 9.** Figure 9: Achieved PSNR and measured performance as a function of TV on SDM854. [PITH_FULL_IMAGE:figures/full_fig_p010_9.png]

**Figure 10.** Figure 10: MobiSR’s speedup as a function of error degradation. [PITH_FULL_IMAGE:figures/full_fig_p012_10.png]

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