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Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking

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arxiv 2006.06806 v1 pith:DNXLKE4R submitted 2020-06-11 cs.CR

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking

classification cs.CR
keywords hardwarelockinglogicsecuritybenchmarkingdeficienciesevaluationfrontier
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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Integrated circuits (ICs) are the foundation of all computing systems. They comprise high-value hardware intellectual property (IP) that are at risk of piracy, reverse-engineering, and modifications while making their way through the geographically-distributed IC supply chain. On the frontier of hardware security are various design-for-trust techniques that claim to protect designs from untrusted entities across the design flow. Logic locking is one technique that promises protection from the gamut of threats in IC manufacturing. In this work, we perform a critical review of logic locking techniques in the literature, and expose several shortcomings. Taking inspiration from other cybersecurity competitions, we devise a community-led benchmarking exercise to address the evaluation deficiencies. In reflecting on this process, we shed new light on deficiencies in evaluation of logic locking and reveal important future directions. The lessons learned can guide future endeavors in other areas of hardware security.

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