REVIEW 4 major objections 5 minor 2 cited by
Performance benefits of increased qubit connectivity in quantum annealing 3-dimensional spin glasses
T0 review · 4 major / 5 minor · reviewed 2026-08-27 · deepseek-v4-flash
Pith's one-line read A comparison of two quantum annealing processors shows that increased qubit connectivity, which shortens minor-embedding chains from four qubits to two, yields a clear time-to-solution scaling advantage on 3D spin glasses.
desk verdict Useful but under-verified hardware benchmark: ADV beats 2KQ on 3D spin glasses, yet the TTS target is not classically confirmed and the hardest L=8 instances are dropped. read the letter →
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
What carries the argument
The load-bearing object is the ferromagnetic chain used in minor embedding: each logical lattice spin is mapped to a cluster of physical qubits forced to align by strong couplings. In the Chimera graph, each logical spin in a 3D lattice requires a four-qubit chain; in the Pegasus graph it requires a two-qubit chain, halving the chain length while keeping the same algebraic chain strength of $2$. With logical couplings set to $\pm 1$ and chain couplings to $-2$, the embedded classical problem is guaranteed to have a chain-unbroken ground state. The paper's measurements identify this chain-length reduction as the primary driver of the improved scaling and consistency.
What would settle it
Construct 3D spin-glass instances with planted, independently known ground states, embed them on both processors, and measure time to solution against the planted state; if the ADV-over-2KQ scaling advantage shrinks or vanishes, the reported result depends on the machines' self-consistent 'presumed ground state' convention rather than on connectivity.
Extended reading notes
Core claim
The central claim is that, for the embedded 3D spin-glass instances studied ($L=5$ to $10$, open boundaries), the ADV system has a clear scaling advantage over the 2KQ system in time to solution, and that the advantage is largest for the hardest instances. The evidence is a median-TTS scaling comparison, an instance-by-instance comparison at $L=8$ in which ADV is up to $800\times$ faster and 2KQ fails on three instances, and a consistency measurement over the 48 cube isometries in which ADV shows much smaller spreads. Because ADV also has a $22\%$ lower energy-scale crossing and a higher noise profile than 2KQ, the authors take the result as strong evidence that chain length, not raw energy scale or noise, is the dominant performance factor.
Load-bearing premise
The benchmark defines the target as the 'presumed ground state' — the best energy found by the machines themselves (Section I.C) — with no classical verification that it is the true minimum, so the measured time to solution may be time to find a particular low-energy state rather than the true ground state.
Editorial extensions
If this is right
- For the $L=5$ to $10$ instances studied, median time to solution scales better on ADV, and at $L=8$ ADV is up to $800\times$ faster, with three instances that 2KQ never solved.
- Because the Pegasus graph needs fewer physical qubits per logical spin, the same embedding method extends to lattices larger than the Chimera graph can hold ($L>8$).
- The advantage concentrates in the hardest instances, so increased connectivity matters most where optimization problems are most difficult.
- The authors expect the benefit to carry over to other minor-embedded problems, specifically predicting that quantum simulation experiments on 2D frustrated lattices using four-qubit chains will improve if run with two-qubit chains.
Reading between the lines
- A classical verification pass that replaces the machines' 'presumed ground state' with an independently confirmed minimum would reveal whether the scaling advantage concerns true ground states or merely a shared low-energy target.
- The chain-length explanation could be tested directly by embedding the same $L\le 8$ instances in ADV with deliberately lengthened chains, holding energy scale and noise fixed.
- If chain length is the dominant term, then each future topology that again halves chain length should yield comparable time-to-solution gains, making chain length an explicit design target for annealing hardware.
Signed reviews
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The paper presents an experimental comparison of two generations of D-Wave quantum annealing hardware on random three-dimensional spin-glass instances. The authors minor-embed L×L×L lattices for L=5..10 into the Chimera-based 2000Q (four-qubit chains) and the Pegasus-based Advantage (two-qubit chains), measure time-to-solution (TTS) defined by the probability of finding a 'presumed ground state', and report a scaling advantage for Advantage, larger speedups on the hardest L=8 instances, and improved consistency over the 48 cube isometries. They attribute the improvement primarily to shorter chains.
Significance. If the quantitative claims survive closer scrutiny, this is a valuable experimental datapoint linking qubit connectivity to practical performance on embedded optimization problems. The paper's strengths are its clean problem family (3D spin glasses), use of the standard TTS metric, reuse of the same problem instances across processors for L≤8, and the cube-isometry consistency check, which is a clever way to probe embedding distortion. The main threats are the lack of classical verification of the target ground state, the exclusion of three L=8 instances, and an apparent typo in the definition of the optimal anneal time. These issues are load-bearing because the central claim is a scaling comparison based on TTS.
major comments (4)
- [Section I.C, Eq. (2)] The TTS target is the 'presumed ground state' found by the machines themselves, and no classical verification establishes that this state is the true Ising ground state. Equation (2) therefore measures time to a hardware-defined target, not time to solution of the optimization problem. If the two processors saturate at different local minima, the relative TTS can reflect where each annealer gets stuck rather than a genuine scaling advantage for finding ground states. This concern is concretely visible in the L=8 comparison (Fig. 2 bottom), where three instances are dropped because 2KQ never reached ADV's best energy. The authors should verify the presumed ground states for at least the smaller sizes (e.g., using an exact or high-quality classical solver), or redefine the target to a common energy threshold, and should include all instances rather than excluding failures.
- [Section I.C, paragraph on topt] The text states that the optimal anneal time topt is 'the one that minimizes pGS(ta)'. Taken literally, this selects the anneal time with the smallest success probability, which would maximize rather than minimize TTS in Eq. (2). The correct optimal choice should maximize pGS(ta) or directly minimize TTS(ta). Because the reported TTS values are the basis of all scaling and consistency claims, this methodological definition needs to be corrected and the computation checked.
- [Section II.A and Fig. 2] The exclusion of three of 100 L=8 instances because '2KQ never found the best energy found by ADV' is a selection bias. Dropping these instances from the median and from the 'hardest problems' analysis changes the measured distribution and inflates the apparent advantage of ADV. At minimum, these instances should be counted as failures (TTS set to infinity or censored at the experimental maximum), and the analysis should be repeated under that convention. The conclusion that ADV is up to 800× faster on the remaining 97 instances does not characterize the full instance set.
- [Sections III and II.B] The attribution of the improvement 'primarily to the reduction in chain length' is not directly supported by the data. The two processors differ in many respects beyond chain length: energy scale (1.91 GHz vs 1.50 GHz crossing), noise profile, calibration, qubit count, and working graph size. The cube-isometry consistency result (Fig. 3) shows lower embedding distortion for ADV, but it does not isolate chain length from these other differences. To support the causal claim in the title and conclusions, the authors would need a control experiment (e.g., varying chain length on the same processor) or a more explicit argument separating these factors. As written, the paper demonstrates a performance difference but not that increased connectivity is the cause.
minor comments (5)
- [Section I.B] The sentence 'for L > 8 the problems are only embeddable in 2KQ' appears to be a typo: earlier in the same section it is stated that 2KQ can embed lattices only if all dimensions are ≤8, while ADV can embed up to 15×15×12. The text should read 'only embeddable in ADV'.
- [Section I.C, Eq. (2)] The displayed formula is missing the division operator: TTS should be t_a log(0.01)/log(1−pGS(ta)), not t_a log(0.01) log(1−pGS(ta)). There is also a missing closing parenthesis after pGS(ta).
- [Section II.A, Fig. 2] The caption mentions a 'log-log fit line' but no fit parameters or confidence intervals are reported. Reporting the fitted exponent and its uncertainty would strengthen the scaling claim.
- [Section I.C] The yield statistics are reported only for L=5,6 and L=10; the defect counts for L=7,8,9 are not stated. Since the same logical lattice graph is used for each size and processor, a full table of yields would help assess whether differences in defects affect the comparison.
- [General] The phrase 'for each system size we use the same subgraph ... with missing spins and couplers corresponding to inoperable qubits' should clarify whether the same defect pattern was used on both processors or whether each processor's working graph led to different subgraphs. The text implies the former, but the discrepancy between 2041 and 5510 qubits makes this nontrivial.
Circularity Check
No circular derivation: the paper is an empirical benchmark using the standard external TTS metric, with the unverified 'presumed ground state' as a benchmark-validity caveat rather than a circular input.
full rationale
The paper contains no mathematical derivation chain whose conclusions could reduce to its inputs. Its central measure, TTS in Eq. (2), is the standard time-to-solution definition taken from Rønnow et al. [14], and the reported quantities are measured from processor runs rather than derived from a fitted or self-referential construction. The use of a 'presumed ground state' is a methodological limitation: because that state is not classically verified, TTS measures time to reach the hardware's best-found state, and for the three excluded L=8 instances the target is explicitly the best energy found by ADV rather than a verified optimum. However, this is a benchmark-validity concern about whether the comparison targets the true ground state, not circularity in the paper's reasoning; the paper is transparent about the presumption, and the TTS formula itself would still be an independent external metric if the presumed states were verified. Self-citations to prior D-Wave work appear in contextual roles, such as chain calibration and topology description, and are not used as the load-bearing justification for the main empirical scaling claim. Therefore no specific circular step meeting the evidence standard can be identified.
Assumptions & free parameters
free parameters (2)
- chain_strength =
-2
- flux_bias_offset =
average magnetization zero
assumptions (4)
- standard math The TTS formula (Eq. 2) from Rønnow et al. is a valid measure of time to 99% success.
- domain assumption The D-Wave processors implement the transverse-field Ising Hamiltonian (Eq. 1) with known energy scales and noise.
- domain assumption The minor embeddings preserve the logical spin-glass ground state when chain strength is set to twice the maximum logical coupling.
- domain assumption The 'presumed ground state' found by the hardware is the true ground state of the logical problem.
Cite this review
Pith. "Pith review of Performance benefits of increased qubit connectivity in quantum annealing 3-dimensional spin glasses." pith.science (2026). https://pith.science/paper/C5CGHFZS
@misc{pith2026200912479,
author = {Pith},
title = {Pith review of: Performance benefits of increased qubit connectivity in quantum annealing 3-dimensional spin glasses},
year = {2026},
howpublished = {\url{https://pith.science/paper/C5CGHFZS}},
note = {Machine review of arXiv:2009.12479}
}
read the original abstract
An important challenge in superconducting quantum computing is the need to physically couple many devices using quasi-two-dimensional fabrication processes. Recent advances in the design and fabrication of quantum annealing processors have enabled an increase in pairwise connectivity among thousands of qubits. One benefit of this is the ability to minor-embed optimization problems using fewer physical qubits for each logical spin. Here we demonstrate the benefit of this progress in the problem of minimizing the energy of three-dimensional spin glasses. Comparing the previous generation D-Wave 2000Q system to the new Advantage system, we observe improved scaling of solution time and improved consistency over multiple graph embeddings.
Figures
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Reference graph
Works this paper leans on
-
[1]
M. W. Johnson, M. H. Amin, S. Gildert, T. Lanting, F. Hamze, et al. , Nature 473, 194 (2011)
work page 2011
- [2]
-
[3]
Farhi, J
E. Farhi, J. Goldstone, S. Gutmann, J. Lapan, A. Lund- gren, and D. Preda, Science 292, 472 (2001)
2001
-
[4]
Kadowaki and H
T. Kadowaki and H. Nishimori, Physical Review E 58, 5355 (1998)
1998
- [5]
-
[6]
G. E. Santoro, R. Marton´ ak, E. Tosatti, and R. Car, Science 295, 2427 (2002)
work page 2002
-
[7]
Barahona, Journal of Physics A: Mathematical and General 15, 3241 (1982)
F. Barahona, Journal of Physics A: Mathematical and General 15, 3241 (1982)
1982
-
[8]
H. G. Katzgraber, F. Hamze, and R. S. Andrist, Physical Review X 4, 021008 (2014)
work page 2014
Show all 26 references
-
[9]
A. D. King, J. Carrasquilla, J. Raymond, I. Ozfidan, E. Andriyash, et al. , Nature 560, 456 (2018)
2018
-
[10]
Next- Generation Topology of D-Wave Quantum Processors,
K. Boothby, P. Bunyk, J. Raymond, and A. Roy, “Next- Generation Topology of D-Wave Quantum Processors,” 5 (2020), arXiv:2003.00133
2020 arXiv
-
[11]
Choi, Quantum Information Processing 7, 193 (2008)
V. Choi, Quantum Information Processing 7, 193 (2008)
2008
-
[12]
Since z-couplings are split across two physical couplers, each will be given a value of ± 1 2
-
[13]
7 and related methods in [9], and a similar approach in Appendix B of [26]
This is recommended when using chains; see for example Extended Data Fig. 7 and related methods in [9], and a similar approach in Appendix B of [26]
-
[14]
T. F. Rønnow, Z. Wang, J. Job, S. Boixo, S. V. Isakov, D. Wecker, J. M. Martinis, D. A. Lidar, and M. Troyer, Science 345, 420 (2014)
2014
-
[15]
Search range in experi- mental quantum annealing,
N. Chancellor and V. Kendon, “Search range in experi- mental quantum annealing,” (2020), arXiv:2008.11054
2020 arXiv
-
[16]
Improving performance of logical qubits by param- eter tuning and topology compensation,
J. Raymond, N. Ndiaye, G. Rayaprolu, and A. King, “Improving performance of logical qubits by param- eter tuning and topology compensation,” (2020), arXiv:2006.04913
2020 arXiv
-
[17]
The D-Wave Advantage Sys- tem: An Overview,
C. McGeoch and P. Farr´ e, “The D-Wave Advantage Sys- tem: An Overview,” (2020)
2020
-
[18]
Houdayer, The European Physical Journal B 22, 479 (2001)
J. Houdayer, The European Physical Journal B 22, 479 (2001)
2001
-
[19]
Moessner and S
R. Moessner and S. L. Sondhi, Physical Review B 63, 1 (2001)
2001
-
[20]
S. V. Isakov and R. Moessner, Physical Review B 68, 104409 (2003)
2003
-
[21]
Quantum Artificial Spin Ice,
A. D. King, C. Nisoli, E. D. Dahl, G. Poulin-Lamarre, and A. Lopez-Bezanilla, “Quantum Artificial Spin Ice,” (2020), arXiv:2007.10555
2020 arXiv
-
[22]
Simulating the Shastry-Sutherland Ising Model using Quantum Anneal- ing,
P. Kairys, A. D. King, I. Ozfidan, K. Boothby, J. Ray- mond, A. Banerjee, and T. S. Humble, “Simulating the Shastry-Sutherland Ising Model using Quantum Anneal- ing,” (2020), arXiv:2003.01019
2020 arXiv
-
[23]
Scaling advantage in quantum sim- ulation of geometrically frustrated magnets,
A. D. King, J. Raymond, T. Lanting, S. V. Isakov, M. Mohseni, et al. , “Scaling advantage in quantum sim- ulation of geometrically frustrated magnets,” (2019), arXiv:1911.03446
2019 arXiv
-
[24]
Chamon, D
C. Chamon, D. Green, and Z.-C. Yang, Physical Review Letters 125, 067203 (2020)
2020
-
[25]
Build- ing and Probing Spin Liquids in a Programmable Quan- tum Device,
S. Zhou, D. Green, E. D. Dahl, and C. Chamon, “Build- ing and Probing Spin Liquids in a Programmable Quan- tum Device,” (2020), arXiv:2009.07853
2020 arXiv
-
[26]
Griffiths-McCoy singularity on the diluted Chimera graph: Monte Carlo simulations and experiments on the quantum hardware,
K. Nishimura, H. Nishimori, and H. G. Katzgraber, “Griffiths-McCoy singularity on the diluted Chimera graph: Monte Carlo simulations and experiments on the quantum hardware,” (2020), arXiv:2006.16219
2020 arXiv
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