Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
A matrix math facility for Power ISA(TM) processors
As of 23 July 2026, this Paper Citation Record lists 0 of 0 outbound references and 2 inbound Pith citation observations for arXiv:2104.03142.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-07-22T06:31:00.163083+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-06-28T12:11:38.789928Z
A source-named dated measurement, never combined with another source.
Source: arxiv_reference, observed 2026-07-02T01:16:25.115832Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation e6ebe236-58a0-47fa-964f-c5d2b5b2f5bf · inbound
CUTEv2: Unified and Configurable Matrix Extension for Diverse CPU Architectures with Minimal Design Overhead cites this paper.
CUTEv2: Unified and Configurable Matrix Extension for Diverse CPU Architectures with Minimal Design Overhead A matrix math facility for Power ISA(TM) processors
Reference 26
- Resolution
- verified exact
- arxiv_id, observed 2026-05-11T11:26:01.564606Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-07-22T06:31:00.163083+00:00.
Observation b7440612-4b7f-4ad4-9c7f-0ab12b3112f4 · inbound
O-POPE: High-Frequency Pipelined Outer Product based GEMM acceleration with minimal buffering overhead cites this paper.
O-POPE: High-Frequency Pipelined Outer Product based GEMM acceleration with minimal buffering overhead A matrix math facility for Power ISA(TM) processors
Reference 15
- Resolution
- verified exact
- arxiv_id, observed 2026-07-02T01:16:25.117479Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-07-22T06:31:00.163083+00:00.