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DeepRT: A Soft Real Time Scheduler for Computer Vision Applications on the Edge

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arxiv 2105.01803 v1 pith:QWKUO3HW submitted 2021-05-05 cs.DC cs.CV

DeepRT: A Soft Real Time Scheduler for Computer Vision Applications on the Edge

classification cs.DC cs.CV
keywords deeprtrequestsapplicationsedgelatencyrealsoftthroughput
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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The ubiquity of smartphone cameras and IoT cameras, together with the recent boom of deep learning and deep neural networks, proliferate various computer vision driven mobile and IoT applications deployed on the edge. This paper focuses on applications which make soft real time requests to perform inference on their data - they desire prompt responses within designated deadlines, but occasional deadline misses are acceptable. Supporting soft real time applications on a multi-tenant edge server is not easy, since the requests sharing the limited GPU computing resources of an edge server interfere with each other. In order to tackle this problem, we comprehensively evaluate how latency and throughput respond to different GPU execution plans. Based on this analysis, we propose a GPU scheduler, DeepRT, which provides latency guarantee to the requests while maintaining high overall system throughput. The key component of DeepRT, DisBatcher, batches data from different requests as much as possible while it is proven to provide latency guarantee for requests admitted by an Admission Control Module. DeepRT also includes an Adaptation Module which tackles overruns. Our evaluation results show that DeepRT outperforms state-of-the-art works in terms of the number of deadline misses and throughput.

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Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. Edge-Inference Governors Need Memory-Clock State

    cs.PF 2026-06 accept novelty 6.0

    EMC-blind GPU-only latency fits miss 25–28% of tight deadlines on Jetson Orin; an EMC-aware two-cell refit holds misses ≤1.3% under a 2% QoS budget and selects a budget-feasible clock.

  2. Edge-Inference Governors Need Memory-Clock State

    cs.PF 2026-06 unverdicted novelty 5.0

    EMC state is required in latency models for edge inference governors; EMC-blind CPU/GPU fits miss 25-28% deadlines while EMC-aware refits limit misses to 1.3% and identify feasible energy points across vision and LLM ...