Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
Hardware-Efficient Quantum Random Access Memory Design with a Native Gate Set on Superconducting Platforms
As of 6 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 2 inbound Pith citation observations for arXiv:2306.10250.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-06T06:34:29.942622+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-05T05:41:47.885556Z
A source-named dated measurement, never combined with another source.
Source: arxiv_reference, observed 2026-05-19T00:16:55.187066Z
Reference resolution
0 of 0 outbound references displayed
- verified exact0
- verified fuzzy0
- unresolved0
- parse uncertain0
- malformed identifier0
- metadata mismatch0
External citation measurements
No source-named external measurement is stored.
Outbound references
No outbound reference observations are available for this paper version.
Pith citing papers
Observation 8ab6ae51-9676-41d0-ae49-1964ee8c14ea · inbound
A resource-efficient quantum-walker Quantum RAM cites this paper.
A resource-efficient quantum-walker Quantum RAM Hardware-Efficient Quantum Random Access Memory Design with a Native Gate Set on Superconducting Platforms
Reference 29
- Resolution
- verified exact
- arxiv_id, observed 2026-05-19T00:16:55.189051Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-06T06:34:29.942622+00:00.
Observation 6483e0c8-f153-48ad-bf54-52e04aa70f04 · inbound
Practical Fidelity Limits of Toffoli Gates in Superconducting Quantum Processors cites this paper.
Practical Fidelity Limits of Toffoli Gates in Superconducting Quantum Processors Hardware-Efficient Quantum Random Access Memory Design with a Native Gate Set on Superconducting Platforms
Reference 109
- Resolution
- unresolved
- no resolver link, observed 2026-08-05T05:41:47.885556Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.