Wiring surface loss of a superconducting transmon qubit

Quantum processors using superconducting qubits suffer from dielectric loss leading to noise and dissipation. Qubits are usually designed as large capacitor pads connected to a non-linear Josephson junction (or SQUID) by a superconducting thin metal wiring. Here, we report on finite-element simulation and experimental results confirming that more than 50% of surface loss in transmon qubits can originated from Josephson junctions wiring and can limit qubit relaxation time. Extracting dielectric loss tangents capacitor pads and wiring based on their participation ratios, we show dominant surface loss of wiring can occur for real qubits designs. Then, we simulate a qubit coupled to a bath of individual TLS defects and show that only a small fraction (~18%) of coupled defects is located within the wiring interfaces, however, their coupling strength is much higher due to stronger electromagnetic field. Finally, we fabricate six tunable floating transmon qubits and experimentally demonstrate up to 20% improvement in qubit quality factor by wiring design optimization.