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A Hardware Evaluation Framework for Large Language Model Inference

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arxiv 2312.03134 v1 pith:XSETP5XA submitted 2023-12-05 cs.AR cs.DCcs.LG

A Hardware Evaluation Framework for Large Language Model Inference

classification cs.AR cs.DCcs.LG
keywords hardwarellmcompassdesignsinferencecostlargea100average
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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The past year has witnessed the increasing popularity of Large Language Models (LLMs). Their unprecedented scale and associated high hardware cost have impeded their broader adoption, calling for efficient hardware designs. With the large hardware needed to simply run LLM inference, evaluating different hardware designs becomes a new bottleneck. This work introduces LLMCompass, a hardware evaluation framework for LLM inference workloads. LLMCompass is fast, accurate, versatile, and able to describe and evaluate different hardware designs. LLMCompass includes a mapper to automatically find performance-optimal mapping and scheduling. It also incorporates an area-based cost model to help architects reason about their design choices. Compared to real-world hardware, LLMCompass' estimated latency achieves an average 10.4% error rate across various operators with various input sizes and an average 4.1% error rate for LLM inference. With LLMCompass, simulating a 4-NVIDIA A100 GPU node running GPT-3 175B inference can be done within 16 minutes on commodity hardware, including 26,400 rounds of the mapper's parameter search. With the aid of LLMCompass, this work draws architectural implications and explores new cost-effective hardware designs. By reducing the compute capability or replacing High Bandwidth Memory (HBM) with traditional DRAM, these new designs can achieve as much as 3.41x improvement in performance/cost compared to an NVIDIA A100, making them promising choices for democratizing LLMs. LLMCompass is planned to be fully open-source.

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Cited by 6 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. MIST: A Co-Design Framework for Heterogeneous, Multi-Stage LLM Inference

    cs.AR 2025-04 unverdicted novelty 7.0

    MIST is a new simulator for heterogeneous multi-stage LLM inference that combines hardware traces with analytical models to explore configuration trade-offs in hybrid CPU-accelerator systems.

  2. Think Before You Grid-Search: Floor-First Triage for LLM Serving

    cs.PF 2026-07 conditional novelty 6.0

    A five-dimensional resource-vector floor model computes latency bounds and capacity walls for LLM serving, predicting when TP16 or EP16+DP attention layouts dominate based on operating point.

  3. Think Before You Grid-Search: Floor-First Triage for LLM Serving

    cs.PF 2026-07 conditional novelty 6.0

    LLM serving should triage by five-resource analytical floors and wall ordering, not grid search; on 16×H20, TP16 is capacity-capped at ~70 while EP+DP attention reaches ~644 concurrent 8K requests.

  4. Sim-FA: A GPGPU Simulator Framework for Fine-Grained Asynchronous Pipeline Analysis

    cs.AR 2026-05 unverdicted novelty 6.0

    Sim-FA is a new simulator that instruments FlashAttention-3 for cycle-accurate GPGPU analysis, achieving 5.7% average error on H800 while explaining inaccuracies in existing DRAM traffic models.

  5. Sim-FA: A GPGPU Simulator Framework for Fine-Grained Asynchronous Pipeline Analysis

    cs.AR 2026-05 conditional novelty 6.0

    A trace-driven simulator models Hopper TMA/WGMMA pipelines at WarpGroup granularity, matching H800 FlashAttention-3 latency to 5.7% MAPE, and its analytical model explains GenZ's long-sequence DRAM underestimation.

  6. MemExplorer: Navigating the Heterogeneous Memory Design Space for Agentic Inference NPUs

    cs.AR 2026-04 unverdicted novelty 6.0

    MemExplorer optimizes heterogeneous memory systems for agentic LLM inference on NPUs and reports up to 2.3x higher energy efficiency than baselines under fixed power budgets.