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arxiv: 2401.05753 · v1 · submitted 2024-01-11 · 💻 cs.SE · cs.CR

BEC: Bit-Level Static Analysis for Reliability against Soft Errors

Yousun Ko , Bernd Burgstaller This is my paper

Pith reviewed 2026-05-24 04:25 UTC · model grok-4.3

classification 💻 cs.SE cs.CR
keywords soft errorsbit-level analysisstatic program analysisfault injectionreliabilityinstruction schedulingcompiler optimizationRISC-V
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The pith

A static bit-level analysis classifies the semantic effect of each register bit corruption at compile time to support reliability against soft errors.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents a compile-time method that follows individual bit corruptions through the register file and determines whether each one would alter program semantics. This classification supports two practical uses: removing many unnecessary experiments from exhaustive fault-injection campaigns and reordering instructions to avoid vulnerable bit patterns. A reader would care because soft errors from radiation or interference can silently corrupt results in any digital system, and a compiler technique that reduces testing cost or error exposure without adding runtime checks would lower the barrier to building more resilient software.

Core claim

The BEC analysis tracks each bit corruption in the register file and classifies the effect of the corruption by its semantics at compile time. Experimental results show that bit-level analysis pruned up to 30.04% of exhaustive fault injection campaigns without loss of accuracy and reduced program vulnerability by up to 13.11% through bit-level vulnerability-aware instruction scheduling. The analysis is implemented within LLVM and evaluated on the RISC-V architecture, and is presented as the first bit-level compiler analysis for program reliability against soft errors.

What carries the argument

Bit-level error coalescing (BEC) static program analysis, which follows bit corruptions in the register file and classifies their semantic effects at compile time.

If this is right

  • Exhaustive fault injection campaigns can be reduced by up to 30.04 percent (13.71 percent on average) with no loss of accuracy.
  • Bit-level vulnerability-aware instruction scheduling can lower program vulnerability by up to 13.11 percent (4.94 percent on average).
  • The same classification technique applies to any computer architecture, not only RISC-V.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The classification could be reused inside other compiler passes that already reason about register liveness or dataflow.
  • Results obtained on RISC-V suggest the approach may transfer directly to embedded processors that share similar register-file designs.
  • If the classification proves stable across compiler versions, it could become a standard static check reported alongside conventional warnings.

Load-bearing premise

The semantic classification assigned to each bit corruption at compile time matches the actual effect that a soft error would produce when the program runs on real hardware.

What would settle it

Execute the same programs under both full exhaustive fault injection and the pruned campaigns produced by BEC, then compare whether any errors appear only in the full set.

Figures

Figures reproduced from arXiv: 2401.05753 by Bernd Burgstaller, Yousun Ko.

Figure 1
Figure 1. Figure 1: Motivating example to count the number of years that ar [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: (a) CFG and (b) fault sites of the motivating example fr [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Bit-level analysis: (a) lattice representation of b [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Iterative fault index coalescing of a fork-after-jo [PITH_FULL_IMAGE:figures/full_fig_p008_4.png] view at source ↗
read the original abstract

Soft errors are a type of transient digital signal corruption that occurs in digital hardware components such as the internal flip-flops of CPU pipelines, the register file, memory cells, and even internal communication buses. Soft errors are caused by environmental radioactivity, magnetic interference, lasers, and temperature fluctuations, either unintentionally, or as part of a deliberate attempt to compromise a system and expose confidential data. We propose a bit-level error coalescing (BEC) static program analysis and its two use cases to understand and improve program reliability against soft errors. The BEC analysis tracks each bit corruption in the register file and classifies the effect of the corruption by its semantics at compile time. The usefulness of the proposed analysis is demonstrated in two scenarios, fault injection campaign pruning, and reliability-aware program transformation. Experimental results show that bit-level analysis pruned up to 30.04 % of exhaustive fault injection campaigns (13.71 % on average), without loss of accuracy. Program vulnerability was reduced by up to 13.11 % (4.94 % on average) through bit-level vulnerability-aware instruction scheduling. The analysis has been implemented within LLVM and evaluated on the RISC-V architecture. To the best of our knowledge, the proposed BEC analysis is the first bit-level compiler analysis for program reliability against soft errors. The proposed method is generic and not limited to a specific computer architecture.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper proposes BEC, a bit-level static analysis implemented in LLVM for the RISC-V architecture. BEC tracks individual bit corruptions in the register file and classifies their semantic effects at compile time using LLVM IR. It is applied to two tasks: pruning exhaustive fault-injection campaigns (claimed up to 30.04% reduction, 13.71% average, with no loss of accuracy) and bit-level vulnerability-aware instruction scheduling (claimed vulnerability reduction up to 13.11%, 4.94% average). The work positions itself as the first bit-level compiler analysis for soft-error reliability and asserts generality across architectures.

Significance. If the static IR-level classification is shown to faithfully model hardware-level soft-error propagation, the approach would offer a practical, compile-time method to reduce the cost of fault-injection campaigns and to guide reliability-oriented code transformations. The LLVM implementation and concrete RISC-V numbers constitute a reproducible starting point for further compiler-reliability research. The absence of dynamic cross-validation, however, leaves the accuracy claims unanchored.

major comments (2)
  1. [Abstract and Experimental Results section] Abstract and Experimental Results section: the claim that pruning occurs 'without loss of accuracy' (30.04% maximum) is load-bearing for both use-cases, yet the manuscript provides no description of how pruning accuracy was verified (e.g., comparison against full FI results or cycle-accurate simulation) and supplies no information on benchmark selection or statistical significance of the reported averages.
  2. [BEC analysis and fault model section] § on BEC analysis and fault model: the central assumption that LLVM IR bit-semantics classification matches the actual runtime impact of soft errors on the RISC-V pipeline and register file is not supported by any dynamic cross-check (FPGA injection, RTL simulation, or hardware measurement); any systematic mismatch would invalidate both the pruning percentages and the scheduling improvements.
minor comments (2)
  1. [Abstract] The abstract and experimental section should state the number of benchmarks, their characteristics, and the exact procedure used to compute 'no loss of accuracy.'
  2. A small example or figure illustrating how a single bit corruption is classified by BEC would improve readability of the core algorithm.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for the constructive comments on our manuscript. Below we respond point-by-point to the major comments, indicating where revisions will be made.

read point-by-point responses

  1. Referee: [Abstract and Experimental Results section] Abstract and Experimental Results section: the claim that pruning occurs 'without loss of accuracy' (30.04% maximum) is load-bearing for both use-cases, yet the manuscript provides no description of how pruning accuracy was verified (e.g., comparison against full FI results or cycle-accurate simulation) and supplies no information on benchmark selection or statistical significance of the reported averages.

    Authors: We agree that the manuscript should have included an explicit description of the verification process supporting the 'without loss of accuracy' claim, as well as details on benchmark selection and statistical measures. The pruning decision is derived from a sound static classification: any bit corruption classified as non-critical is guaranteed (under the IR fault model) to produce an identical program outcome, so the reduced campaign yields the same vulnerability estimate as the exhaustive one. In the revised version we will add a dedicated paragraph in the Experimental Results section that (i) describes the verification procedure (comparison of vulnerability estimates obtained from pruned versus full campaigns on the same LLVM-based simulator), (ii) lists the concrete benchmark programs used, and (iii) reports standard deviation alongside the reported averages to convey statistical significance. revision: yes

  2. Referee: [BEC analysis and fault model section] § on BEC analysis and fault model: the central assumption that LLVM IR bit-semantics classification matches the actual runtime impact of soft errors on the RISC-V pipeline and register file is not supported by any dynamic cross-check (FPGA injection, RTL simulation, or hardware measurement); any systematic mismatch would invalidate both the pruning percentages and the scheduling improvements.

    Authors: The BEC analysis classifies bit corruptions according to their observable semantic effect at the LLVM IR level, which is the same abstraction used by the compiler for code generation. This design choice deliberately stays within the compiler's own model rather than attempting to replicate micro-architectural timing or pipeline forwarding. We acknowledge that the absence of a hardware-level cross-validation leaves open the possibility of systematic divergence between IR semantics and actual silicon behavior. In the revised manuscript we will insert a limitations paragraph in the BEC analysis section that explicitly states this modeling assumption and its implications for the reported numbers. revision: partial

standing simulated objections not resolved
  • Dynamic cross-validation (FPGA injection, RTL simulation, or hardware measurement) confirming that the LLVM-IR bit classification faithfully reproduces the runtime impact of soft errors on the RISC-V pipeline and register file.

Circularity Check

0 steps flagged

No circularity; analysis and results are experimentally self-contained

full rationale

The paper introduces a new LLVM-based static analysis (BEC) that classifies bit corruptions via IR semantics and reports pruning/vulnerability numbers as direct outcomes of fault-injection experiments and scheduling transformations on RISC-V. No equations, fitted parameters, or self-citation chains are used to derive the central claims; the percentages (30.04 % pruning, 13.11 % vulnerability reduction) are presented as measured results rather than quantities forced by construction or prior author work. The derivation chain therefore remains independent of its own inputs.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only review; no free parameters, axioms, or invented entities are identifiable from the provided text.

pith-pipeline@v0.9.0 · 5771 in / 1119 out tokens · 16484 ms · 2026-05-24T04:25:24.824381+00:00 · methodology

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Reference graph

Works this paper leans on

44 extracted references · 44 canonical work pages

  1. [1]

    Alpha-particle-induced soft e rrors in dynamic memories,

    T. C. May and M. H. Woods, “Alpha-particle-induced soft e rrors in dynamic memories,” IEEE Transactions on Electron Devices , vol. 26, no. 1, pp. 2–9, 1979. doi: 10.1109/T-ED.1979.19370

    work page doi:10.1109/t-ed.1979.19370 1979

  2. [2]

    Soft errors in advanced computer systems,

    R. Baumann, “Soft errors in advanced computer systems,” IEEE De- sign Test of Computers , vol. 22, no. 3, pp. 258–266, 2005. doi: 10.1109/MDT.2005.69

    work page doi:10.1109/mdt.2005.69 2005

  3. [3]

    Char acterisation of microcontroller susceptibility to radio frequency inte rference,

    S. Baffreau, S. Bendhia, M. Ramdani, and E. Sicard, “Char acterisation of microcontroller susceptibility to radio frequency inte rference,” in Proceedings of the F ourth IEEE International Caracas Confe rence on Devices, Circuits and Systems (Cat. No.02TH8611) , 2002, pp. I031–I031. doi: 10.1109/ICCDCS.2002.1004088

    work page doi:10.1109/iccdcs.2002.1004088 2002

  4. [4]

    Temperature depen dence of soft error rate in flip-flop designs,

    S. Jagannathan, Z. Diggins, N. Mahatme, T. D. Loveless, B . L. Bhuva, S.-J. Wen, R. Wong, and L. W. Massengill, “Temperature depen dence of soft error rate in flip-flop designs,” in 2012 IEEE International Reliability Physics Symposium (IRPS) , 2012, pp. SE.2.1–SE.2.6. doi: 10.1109/IRPS.2012.6241927

    work page doi:10.1109/irps.2012.6241927 2012

  5. [5]

    Error Detection in SRAM (Rev. A),

    T. Instruments, “Error Detection in SRAM (Rev. A),” Nov 2 020. [Online]. Available: https://www.ti.com/lit/pdf/spracc0

    work page

  6. [6]

    DRAM errors in the wild: A large-scale field study,

    B. Schroeder, E. Pinheiro, and W.-D. Weber, “DRAM errors in the wild: A large-scale field study,” Commun. ACM , vol. 54, no. 2, p. 100–107, feb 2011. doi: 10.1145/1897816.1897844

    work page doi:10.1145/1897816.1897844 2011

  7. [7]

    Single event upset investigations on the “flying laptop

    C. Noeldeke, M. Boettcher, U. Mohr, S. Gaisser, M. Alvare z Rua, J. Eickhoff, M. Leslie, M. V on Thun, S. Klinkner, and R. V arat harajoo, “Single event upset investigations on the “flying laptop” sa tellite mission,” Advances in Space Research , vol. 67, no. 6, pp. 2000–2009,

    work page 2000

  8. [8]

    doi: 10.1016/j.asr.2020.12.032

    work page doi:10.1016/j.asr.2020.12.032 2020

  9. [9]

    Fault attacks on secure embedded software: Threats, design, and evaluation,

    B. Y uce, P . Schaumont, and M. Witteman, “Fault attacks on secure embedded software: Threats, design, and evaluation,” Journal of Hardware and Systems Security , vol. 2, no. 2, pp. 111–130, Jun 2018. doi: 10.1007/s41635-018-0038-1

    work page doi:10.1007/s41635-018-0038-1 2018

  10. [10]

    The RISC-V In- struction Set Manual, V olume I: User-Level ISA,

    A. Waterman and K. Asanovic, “The RISC-V In- struction Set Manual, V olume I: User-Level ISA,” https://five-embeddev.com/riscv-isa-manual/latest/riscv-spec.html, March 2019

    work page 2019

  11. [11]

    BEC analysis GitHub repository,

    Y . Ko, “BEC analysis GitHub repository,” https://github.com/yousunko/BEC, 2023

    work page 2023

  12. [12]

    A. V . Aho, M. S. Lam, R. Sethi, and J. D. Ullman, Compilers: Principles, Techniques, and Tools (2nd Edition) . USA: Addison-Wesley Longman Publishing Co., Inc., 2006

    work page 2006

  13. [13]

    S. S. Muchnick, Advanced Compiler Design and Implementation . San Francisco, CA, USA: Morgan Kaufmann Publishers Inc., 1998

    work page 1998

  14. [14]

    Efficiently computing static single assignment form and th e control dependence graph,

    R. Cytron, J. Ferrante, B. K. Rosen, M. N. Wegman, and F. K . Zadeck, “Efficiently computing static single assignment form and th e control dependence graph,” ACM Trans. Program. Lang. Syst. , vol. 13, no. 4, p. 451–490, Oct 1991. doi: 10.1145/115372.115320

    work page doi:10.1145/115372.115320 1991

  15. [15]

    Abstract interpretation: A un ified lattice model for static analysis of programs by construction or app roximation of fixpoints,

    P . Cousot and R. Cousot, “Abstract interpretation: A un ified lattice model for static analysis of programs by construction or app roximation of fixpoints,” in Proceedings of the 4th ACM SIGACT-SIGPLAN Symposium on Principles of Programming Languages , ser. POPL ’77. New Y ork, NY , USA: Association for Computing Machinery, 197 7, p. 238–252. doi: 10.1145/...

    work page doi:10.1145/512950.512973

  16. [16]

    The BSD packet filter: A new a rchitec- ture for user-level packet capture,

    S. McCanne and V . Jacobson, “The BSD packet filter: A new a rchitec- ture for user-level packet capture,” in Proceedings of the USENIX Winter 1993 Conference Proceedings on USENIX Winter 1993 Conferen ce Proceedings, ser. USENIX’93. USA: USENIX Association, 1993, p. 2

    work page 1993

  17. [17]

    Trends from ten years of soft error experimentation,

    A. Dixit, R. Heald, and A. Wood, “Trends from ten years of soft error experimentation,” Proc. 2009 IEEE W orkshop on Silicon Errors in Logic-System Effects (SELSE), March , 2009. [Online]. Available: https://cir.nii.ac.jp/crid/1574231875991217152

    work page arXiv 2009

  18. [18]

    Feng Shui of supercomputer memory: Positio nal effects in DRAM and SRAM faults,

    V . Sridharan, J. Stearley, N. DeBardeleben, S. Blancha rd, and S. Gurumurthi, “Feng Shui of supercomputer memory: Positio nal effects in DRAM and SRAM faults,” in Proceedings of the International Conference on High Performance Computing, N etworking, Storage and Analysis , ser. SC ’13. New Y ork, NY , USA: Association for Computing Machinery, 2013. doi: ...

    work page doi:10.1145/2503210.2503257 2013

  19. [19]

    Avoiding pitfalls in fault- injection based comparison of program susceptibility to so ft errors,

    H. Schirmeier, C. Borchert, and O. Spinczyk, “Avoiding pitfalls in fault- injection based comparison of program susceptibility to so ft errors,” in Proceedings of the 2015 45th Annual IEEE/IFIP Internationa l Conference on Dependable Systems and Networks , ser. DSN ’15. USA: IEEE Computer Society, 2015, p. 319–330. doi: 10.1109/DSN.2015.44

    work page doi:10.1109/dsn.2015.44 2015

  20. [20]

    New techniques for speeding-up f ault- injection campaigns,

    L. Berrojo, I. G´ onz´ alez, F. Corno, M. Sonza Reorda, G. Squillero, L. Entrena, and C. L ´ opez, “New techniques for speeding-up f ault- injection campaigns,” in Proceedings of the Conference on Design, Automation and Test in Europe , ser. DA TE ’02. USA: IEEE Computer Society, 2002, p. 847. doi: 10.1109/DA TE.2002.998398

    work page doi:10.1109/da 2002

  21. [21]

    A comparison of inject-on-read and inject-on-write in ISA-l evel fault injection,

    B. Sangchoolie, F. Ayatolahi, R. Johansson, and J. Karl sson, “A comparison of inject-on-read and inject-on-write in ISA-l evel fault injection,” in Proceedings of the 2015 11th European Dependable Computing Conference (EDCC), ser. EDCC ’15. USA: IEEE Computer Society, 2015, p. 178–189. doi: 10.1109/EDCC.2015.24

    work page doi:10.1109/edcc.2015.24 2015

  22. [22]

    Defining functions on equivalence class es,

    L. C. Paulson, “Defining functions on equivalence class es,” ACM Trans. Comput. Logic , vol. 7, no. 4, p. 658–675, oct 2006. doi: 10.1145/1183278.1183280

    work page doi:10.1145/1183278.1183280 2006

  23. [23]

    Constant propagation wit h conditional branches,

    M. N. Wegman and F. K. Zadeck, “Constant propagation wit h conditional branches,” ACM Trans. Program. Lang. Syst. , vol. 13, no. 2, p. 181–210, Apr 1991. doi: 10.1145/103135.103136

    work page doi:10.1145/103135.103136 1991

  24. [24]

    Khedker, A

    U. Khedker, A. Sanyal, and B. Karkare, Data Flow Analysis: Theory and Practice , 1st ed. USA: CRC Press, Inc., 2009

    work page 2009

  25. [25]

    Theory of equivalence relations,

    O. Ore, “Theory of equivalence relations,” Duke Math. J. , vol. 9, no. 1, pp. 573–627, 1942. [Online]. Available: http://dml.mathdoc.fr/item/1077493381

    work page arXiv 1942

  26. [26]

    Monotone data flow analysis fr ameworks,

    J. B. Kam and J. D. Ullman, “Monotone data flow analysis fr ameworks,” Acta Inf., vol. 7, no. 3, p. 305–317, sep 1977. doi: 10.1007/BF00290339

    work page doi:10.1007/bf00290339 1977

  27. [27]

    A fast and usually linear alg orithm for global flow analysis,

    S. L. Graham and M. Wegman, “A fast and usually linear alg orithm for global flow analysis,” in Proceedings of the 2nd ACM SIGACT- SIGPLAN Symposium on Principles of Programming Languages , ser. POPL ’75. New Y ork, NY , USA: Association for Computing Machinery, 1975, p. 22–34. doi: 10.1145/512976.512979

    work page doi:10.1145/512976.512979 1975

  28. [28]

    Spike RISC-V ISA simulator Git Hub repository,

    RISC-V International, “Spike RISC-V ISA simulator Git Hub repository,” https://github.com/riscv/riscv-isa-sim, 2019

    work page 2019

  29. [29]

    Forma l framework for reasoning about the precision of dynamic analysis,

    M. Dalla Preda, R. Giacobazzi, and N. Marastoni, “Forma l framework for reasoning about the precision of dynamic analysis,” in Static Analysis: 27th International Symposium, SAS 2020, Virtual Event, November 18–20, 2020, Proceedings . Berlin, Heidelberg: Springer- V erlag, 2020, p. 178–199. doi: 10.1007/978-3-030-65474-0˙9

    work page doi:10.1007/978-3-030-65474-0 2020

  30. [30]

    Towards a unifying framework for tuning an alysis precision by program transformation,

    M. D. Preda, “Towards a unifying framework for tuning an alysis precision by program transformation,” in Recent Developments in the Design and Implementation of Programming Languages , ser. OpenAccess Series in Informatics (OASIcs), F. S. de Boer and J. Mauro, Eds., vol. 86. Dagstuhl, Germany: Schloss Dagstuhl–Leibni z-Zentrum f¨ ur Informatik, 2020, pp. ...

    work page doi:10.4230/oasics.gabbrielli.4 2020

  31. [31]

    FISSC: A fault injection and simulation sec ure col- lection,

    L. Dureuil, G. Petiot, M.-L. Potet, T.-H. Le, A. Crohen, and P . de Choudens, “FISSC: A fault injection and simulation sec ure col- lection,” in Proceedings of the 35th International Conference on Com- puter Safety, Reliability, and Security, SAFECOMP 2016 , A. Skavhaug, J. Guiochet, and F. Bitsch, Eds. Cham: Springer Internation al Publish- ing, 2016, pp...

    work page doi:10.1007/978-3-319-45477-1 2016

  32. [32]

    MiBench: A free, commercially representat ive embedded benchmark suite,

    M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T . Mudge, and R. B. Brown, “MiBench: A free, commercially representat ive embedded benchmark suite,” in Proceedings of the F ourth Annual IEEE International W orkshop on W orkload Characterization. WWC -4 (Cat. No.01EX538), ser. WWC ’01. USA: IEEE Computer Society, 2001, p. 3–14. doi: 10.1109/WWC.2...

    work page doi:10.1109/wwc.2001.990739 2001

  33. [33]

    [Online]

    Intel Corporation, Intel 64 and IA-32 Architectures Soft- ware Developer’s Manual , June 2023. [Online]. Available: https://cdrdv2.intel.com/v1/dl/getContent/671436

    work page 2023

  34. [34]

    List scheduling revisited,

    J. Schutten, “List scheduling revisited,” Operations Research Letters , vol. 18, no. 4, pp. 167–170, 1996. doi: 10.1016/0167-6377(95)00057-7

    work page doi:10.1016/0167-6377(95)00057-7 1996

  35. [35]

    Cross-layer fault-space pruning for hardware-assisted f ault injection,

    C. Dietrich, A. Schmider, O. Pusz, G. P . V ay´ a, and D. Loh mann, “Cross-layer fault-space pruning for hardware-assisted f ault injection,” in Proceedings of the 55th Annual Design Automation Conferenc e, ser. DAC ’18. New Y ork, NY , USA: Association for Computing Machinery, 2018. doi: 10.1145/3195970.3196019

    work page doi:10.1145/3195970.3196019 2018

  36. [36]

    Data-flow-sensit ive fault-space pruning for the injection of transient hardware faults,

    O. Pusz, C. Dietrich, and D. Lohmann, “Data-flow-sensit ive fault-space pruning for the injection of transient hardware faults,” in Proceedings of the 22nd ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems , ser. LCTES

    work page

  37. [37]

    New Y ork, NY , USA: Association for Computing Machiner y, 2021, p. 97–109. doi: 10.1145/3461648.3463851

    work page doi:10.1145/3461648.3463851 2021

  38. [38]

    A meth od to determine equivalent fault classes for permanent and trans ient faults,

    D. Smith, B. Johnson, J. Profeta, and D. Bozzolo, “A meth od to determine equivalent fault classes for permanent and trans ient faults,” in Annual Reliability and Maintainability Symposium 1995 Pro ceedings, 1995, pp. 418–424. doi: 10.1109/RAMS.1995.513278

    work page doi:10.1109/rams.1995.513278 1995

  39. [39]

    Tra ce-and- brace (TAB): Bespoke software countermeasures against sof t errors,

    Y . Ko, A. Bradbury, B. Burgstaller, and R. Mullins, “Tra ce-and- brace (TAB): Bespoke software countermeasures against sof t errors,” in Proceedings of the 23rd ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, ser. LCTES 2022. New Y ork, NY , USA: Association for Computin g Machinery, 2022, p. 73–85. do...

    work page doi:10.1145/3519941.3535070 2022

  40. [40]

    Instruction sche duling for reliability-aware compilation,

    S. Rehman, M. Shafique, and J. Henkel, “Instruction sche duling for reliability-aware compilation,” in Proceedings of the 49th Annual Design Automation Conference , ser. DAC ’12. New Y ork, NY , USA: Association for Computing Machinery, 2012, p. 1292–13 00. doi: 10.1145/2228360.2228601

    work page doi:10.1145/2228360.2228601 2012

  41. [41]

    Scheduling instructions for soft errors in register files,

    J. Xu, Q. Tan, and H. Zhou, “Scheduling instructions for soft errors in register files,” in Proceedings of the 2011 IEEE Ninth International Conference on Dependable, Autonomic and Secure Computing , ser. DASC ’11. USA: IEEE Computer Society, 2011, p. 305–312. doi: 10.1109/DASC.2011.69

    work page doi:10.1109/dasc.2011.69 2011

  42. [42]

    Compiler-guided register reliabi lity improvement against soft errors,

    J. Y an and W. Zhang, “Compiler-guided register reliabi lity improvement against soft errors,” in Proceedings of the 5th ACM International Conference on Embedded Software , ser. EMSOFT ’05. New Y ork, NY , USA: Association for Computing Machinery, 2005, p. 203– 209. doi: 10.1145/1086228.1086266

    work page doi:10.1145/1086228.1086266 2005

  43. [43]

    The instruction scheduling f or soft errors based on data flow analysis,

    J. Xu, Q. Tan, and R. Shen, “The instruction scheduling f or soft errors based on data flow analysis,” in Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computin g, ser. PRDC ’09. USA: IEEE Computer Society, 2009, p. 372–378. doi: 10.1109/PRDC.2009.65

    work page doi:10.1109/prdc.2009.65 2009

  44. [44]

    kinematic fitting

    Y . Ko, “BEC analysis Zenodo archive,” 2023. doi: 10.5281/zen- odo.10317898

    work page doi:10.5281/zen- 2023