Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
Paper Citation Record · LEDGER
As of 8 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 8 inbound Pith citation observations for arXiv:2403.11671.
A citation records a reference. It does not transfer a finding from one paper to another.
Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-08T06:32:00.761636+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-07T14:11:57.275703Z
A source-named dated measurement, never combined with another source.
Source: arxiv_reference, observed 2026-06-29T18:53:51.249643Z
0 of 0 outbound references displayed
External citation measurements
No source-named external measurement is stored.
No outbound reference observations are available for this paper version.
Observation 8aa321b0-182e-4229-be0a-99dba0eb4ebf · inbound
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification HDLdebugger: Streamlining HDL debugging with Large Language Models
Reference 31
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation 92678aa1-b9ed-472e-8007-06f4deb640b1 · inbound
ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection HDLdebugger: Streamlining HDL debugging with Large Language Models
Reference 33
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 7d801361-ec76-4f30-beaf-ac4523e28112 · inbound
SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models HDLdebugger: Streamlining HDL debugging with Large Language Models
Reference 72
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 8401bb39-20f6-4c61-9cda-33d689e90ab2 · inbound
ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning HDLdebugger: Streamlining HDL debugging with Large Language Models
Reference 30
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation 77b36558-44ef-4312-80e1-243e94660b8f · inbound
RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs HDLdebugger: Streamlining HDL debugging with Large Language Models
Reference 21
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 4e03cc3f-6a8a-481c-aa5d-05f889901df3 · inbound
HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions HDLdebugger: Streamlining HDL debugging with Large Language Models
Reference 9
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation a19b3676-e523-469e-b58d-daf5829a4a36 · inbound
Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protection HDLdebugger: Streamlining HDL debugging with Large Language Models
Reference 10
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.
Observation d29dd144-f887-4dd8-bc2f-4e4ad8d163e9 · inbound
Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation HDLdebugger: Streamlining HDL debugging with Large Language Models
Reference 14
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-08T06:32:00.761636+00:00.