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arxiv: 2403.16958 · v6 · submitted 2024-03-25 · 💻 cs.CV

TwinLiteNet+: An Enhanced Multi-Task Segmentation Model for Autonomous Driving

Quang-Huy Che , Duc-Tri Le , Minh-Quan Pham , Vinh-Tiep Nguyen , Duc-Khai Lam This is my paper

Pith reviewed 2026-05-24 03:21 UTC · model grok-4.3

classification 💻 cs.CV
keywords semantic segmentationautonomous drivingdrivable area segmentationlane segmentationlightweight neural networkmulti-task learningBDD100Kembedded inference
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The pith

TwinLiteNet+ achieves higher drivable area and lane segmentation accuracy than prior models while using 11 times fewer operations.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents TwinLiteNet+ as a family of lightweight multi-task models for segmenting drivable areas and lane markings in autonomous driving images. It builds a hybrid encoder from stride-based dilated convolutions and depthwise separable dilated convolutions, then adds two new upsampling blocks and a partial class activation attention module to improve decoding precision. On the BDD100K dataset the largest version records 92.9 percent mean intersection-over-union for drivable areas and 34.2 percent intersection-over-union for lanes, exceeding published baselines while cutting floating-point operations by a factor of eleven. The work also reports fast quantized inference and low energy use on embedded hardware, directly addressing the requirement for real-time perception on vehicle-grade chips with limited compute and power budgets.

Core claim

TwinLiteNet+ employs a hybrid encoder architecture that integrates stride-based dilated convolutions and depthwise separable dilated convolutions, balancing representational capacity and computational cost. To improve task-specific decoding, it introduces two lightweight upsampling modules—Upper Convolution Block (UCB) and Upper Simple Block (USB)—alongside a Partial Class Activation Attention (PCAA) mechanism. The model family ranges from 34K parameters in the Nano variant to 1.94M parameters in the Large variant. On the BDD100K dataset, TwinLiteNet+_Large reaches 92.9 percent mIoU for drivable area segmentation and 34.2 percent IoU for lane segmentation while requiring 11 times fewer FLOPs

What carries the argument

Hybrid encoder that combines stride-based dilated convolutions with depthwise separable dilated convolutions to maintain feature quality at low computational cost for simultaneous drivable-area and lane segmentation.

If this is right

  • The four size variants allow direct trade-offs between accuracy and parameter count for different hardware budgets.
  • Quantization to INT8 and FP16 preserves performance, enabling deployment on typical embedded accelerators.
  • Measured inference speed and energy consumption on embedded devices exceed those of heavier models.
  • Simultaneous drivable-area and lane outputs support downstream path planning without separate networks.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the same modules transfer to other segmentation backbones, the approach could reduce compute for additional driving perception tasks such as object detection.
  • The partial class activation attention may improve boundary accuracy on narrow structures like lane markings when applied to different datasets.
  • Ultra-small variants could enable on-device segmentation for low-power microcontrollers in consumer robotics.
  • Combining the encoder with temporal fusion across video frames might further raise lane-segmentation IoU without added parameters.

Load-bearing premise

The accuracy and efficiency gains are produced by the hybrid encoder, UCB, USB, and PCAA modules rather than by differences in training schedule, data augmentation, or hyperparameter choices relative to the baselines.

What would settle it

Retrain the compared state-of-the-art models on the identical BDD100K splits, augmentation pipeline, optimizer schedule, and hyperparameters used for TwinLiteNet+ and check whether the reported accuracy and FLOP gaps remain.

Figures

Figures reproduced from arXiv: 2403.16958 by Duc-Khai Lam, Duc-Tri Le, Minh-Quan Pham, Quang-Huy Che, Vinh-Tiep Nguyen.

Figure 1
Figure 1. Figure 1: Comparison of evaluation metrics mIoU (%) (for Drivable Area Segmentation) - IoU (%) (for Lane [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: The TwinLiteNet+ architecture comprises two phases. During the Encode phase, the input image passes through an Encoder block followed by a Partial Class Activation Attention mechanism. In the Decode phase, the output from the Encoder is channeled through two identical yet independent Decoder blocks, transforming the feature maps into two separate segmentation maps. Despite significant progress, achieving a… view at source ↗
Figure 3
Figure 3. Figure 3: This figure presents variants of ESP blocks within the Encoder. The convolutional layers are designated as [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Comprehensive schematic of the Encoder in TwinLiteNet [PITH_FULL_IMAGE:figures/full_fig_p008_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Decoder Block Design in TwinLiteNet+. This illustrates the implementation of Upper Convolution Block (UCB) and Upper Simple Block (USB) within the decoder, specifically tailored for upsampling to generate segment maps for diverse tasks. blocks. These blocks independently handle the segmentation of distinct regions and drivable lanes. Our decoder effectively reduces the depth of the feature map and employs … view at source ↗
Figure 6
Figure 6. Figure 6: Qualitative results of TwinLiteNet and TwinLiteNet [PITH_FULL_IMAGE:figures/full_fig_p017_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Qualitative results of TwinLiteNet and TwinLiteNet [PITH_FULL_IMAGE:figures/full_fig_p018_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Qualitative results of TwinLiteNet and TwinLiteNet [PITH_FULL_IMAGE:figures/full_fig_p019_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Examples of Ground truth visualization for Directly & Alternative Area segmentation task. [PITH_FULL_IMAGE:figures/full_fig_p022_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Results visualization of TwinLiteNet+ D&A for Directly & Alternative Area segmentation. Red regions are directly drivable area, the blue ones are alternative and the lanes are green [PITH_FULL_IMAGE:figures/full_fig_p023_10.png] view at source ↗
read the original abstract

Semantic segmentation is a fundamental perception task in autonomous driving, particularly for identifying drivable areas and lane markings to enable safe navigation. However, most state-of-the-art (SOTA) models are computationally intensive and unsuitable for real-time deployment on resource-constrained embedded devices. In this paper, we introduce TwinLiteNet+, an enhanced multi-task segmentation model designed for real-time drivable area and lane segmentation with high efficiency. TwinLiteNet+ employs a hybrid encoder architecture that integrates stride-based dilated convolutions and depthwise separable dilated convolutions, balancing representational capacity and computational cost. To improve task-specific decoding, we propose two lightweight upsampling modules-Upper Convolution Block (UCB) and Upper Simple Block (USB)-alongside a Partial Class Activation Attention (PCAA) mechanism that enhances segmentation precision. The model is available in four configurations, ranging from the ultra-compact TwinLiteNet+_{Nano} (34K parameters) to the high-performance TwinLiteNet+_{Large} (1.94M parameters). On the BDD100K dataset, TwinLiteNet+_{Large} achieves 92.9% mIoU for drivable area segmentation and 34.2% IoU for lane segmentation-surpassing existing state-of-the-art models while requiring 11x fewer floating-point operations (FLOPs) for computation. Extensive evaluations on embedded devices demonstrate superior inference speed, quantization robustness (INT8/FP16), and energy efficiency, validating TwinLiteNet+ as a compelling solution for real-world autonomous driving systems. Code is available at https://github.com/chequanghuy/TwinLiteNetPlus.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript introduces TwinLiteNet+, a multi-task segmentation architecture for simultaneous drivable-area and lane-marking segmentation aimed at real-time autonomous driving. It proposes a hybrid encoder that mixes stride-based dilated convolutions with depthwise-separable dilated convolutions, two lightweight up-sampling blocks (UCB and USB), and a Partial Class Activation Attention (PCAA) module. Four model scales are defined (Nano at 34 K parameters to Large at 1.94 M parameters). On BDD100K the Large variant is reported to reach 92.9 % mIoU on drivable area and 34.2 % IoU on lanes while using 11× fewer FLOPs than prior SOTA models; additional embedded-device measurements for latency, INT8/FP16 quantization, and energy are provided. Public code is released.

Significance. If the performance numbers are shown to result from the architectural contributions rather than training-protocol differences, the work would supply a practical, low-FLOP family of models suitable for embedded real-time perception in autonomous driving. The public code release is a clear positive for reproducibility.

major comments (2)
  1. [Experiments section] Experiments section / results tables: the central claim that the hybrid encoder, UCB, USB and PCAA produce the reported 92.9 % mIoU / 34.2 % IoU and 11× FLOPs reduction is load-bearing, yet the manuscript supplies no statement that the cited SOTA baselines were re-trained under an identical data-augmentation schedule, loss weighting, optimizer, or number of epochs. Without this control the attribution of gains to the proposed modules cannot be verified.
  2. [Experiments section] Experiments section: no ablation tables isolate the incremental contribution of the hybrid encoder versus the UCB/USB blocks versus PCAA. Because the headline numbers rest on the joint effect of these modules, the absence of controlled ablations leaves the source of the improvement unclear.
minor comments (1)
  1. The abstract states four model configurations but does not list the exact parameter counts or FLOPs for each; adding a compact table row in the abstract or §3 would improve readability.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback. The two major comments correctly identify gaps in experimental controls and analysis. We address each point below and will revise the manuscript accordingly.

read point-by-point responses

  1. Referee: [Experiments section] Experiments section / results tables: the central claim that the hybrid encoder, UCB, USB and PCAA produce the reported 92.9 % mIoU / 34.2 % IoU and 11× FLOPs reduction is load-bearing, yet the manuscript supplies no statement that the cited SOTA baselines were re-trained under an identical data-augmentation schedule, loss weighting, optimizer, or number of epochs. Without this control the attribution of gains to the proposed modules cannot be verified.

    Authors: We agree that the manuscript does not state whether baselines were re-trained under identical conditions; the numbers are taken from the original publications. This is a limitation for direct attribution. In revision we will add an explicit statement in the Experiments section noting that comparisons use reported figures and discussing possible protocol differences. We will also re-train one key baseline under our exact schedule to provide a controlled reference point. revision: yes

  2. Referee: [Experiments section] Experiments section: no ablation tables isolate the incremental contribution of the hybrid encoder versus the UCB/USB blocks versus PCAA. Because the headline numbers rest on the joint effect of these modules, the absence of controlled ablations leaves the source of the improvement unclear.

    Authors: We acknowledge the lack of component-wise ablations. The revised manuscript will include new ablation tables that evaluate the hybrid encoder, UCB, USB, and PCAA in isolation and in combination, using the same training protocol. These results will be placed in the Experiments section to clarify the contribution of each module. revision: yes

Circularity Check

0 steps flagged

No circularity: results are direct empirical measurements on public BDD100K dataset

full rationale

The paper proposes an architecture (hybrid encoder, UCB, USB, PCAA) and reports mIoU/IoU/FLOPs numbers obtained by training and evaluating on the public BDD100K benchmark. No equations, fitted parameters, or self-citations are used to derive the headline metrics; they are measured outputs. No self-definitional loops, fitted-input predictions, or load-bearing self-citations appear in the provided text. The derivation chain is therefore self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 0 invented entities

The performance claims rest on empirical training and evaluation of the proposed architecture on the BDD100K dataset; the new modules constitute the primary addition beyond prior literature.

free parameters (1)
  • model size configurations
    The four variants (Nano to Large) involve manual choices of channel widths and depths to trade off parameters against accuracy.
axioms (1)
  • domain assumption BDD100K provides reliable ground-truth annotations for drivable area and lane classes.
    All quantitative claims depend on this standard benchmark being correctly labeled and representative.

pith-pipeline@v0.9.0 · 5842 in / 1350 out tokens · 35665 ms · 2026-05-24T03:21:22.924430+00:00 · methodology

discussion (0)

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