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Low-power Rapid Planar Superconducting Logic Devices
Superconductivity · Submitted 28 May 2024
abstract compiled · 2026-09-23 · no language-model review
The authors' main claim The competitive performance of planar RSFQ logic circuits renders them for promising CMOS substitutes, especially in the supercomputational realm.
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The abstract, sentence by sentence
The rapid-pace growing demand for high-performance computation and big-data manipulation entails substantial increase in global power consumption, and challenging thermal management. Thus, there is a need in allocating competitive alternatives for complementary metal-oxide-semiconductor (CMOS) technologies. Superconducting platforms, such as rapid single flux quantum (RSFQ) lack electric resistance and excel in power efficiency and time performance. However, traditional RSFQs require 3D geometry for their Josephson junctions (JJs) imposing a large footprint, and hence preventing device miniaturization and increasing processing time. Here, we demonstrate that RSFQ logic circuits of planar geometry with weak-link bridges are scalable, relatively easy to process and are CMOS-compatible on a Si chip. Universal logic gates, as well as combinational arithmetic circuiting that are based on these devices are demonstrated. The power consumption and processing time of these logic circuits were as low as 0.8 nW and 13 ps, an order of magnitude improvement with respect to the equivalent traditional-RSFQ logic circuits and two orders of magnitude with respect to CMOS. The competitive performance of planar RSFQ logic circuits renders them for promising CMOS substitutes, especially in the supercomputational realm.
background contribution method result interpretation main claim
| # | sentence | role | the authors' own work | states the main conclusion | strength |
|---|---|---|---|---|---|
| s0 | The rapid-pace growing demand for high-performance computation and big-data manipulation entails substantial increase in global power consumption, and challenging thermal management. | background 1.00 | 0.05 | 0.02 | asserted 1.00 |
| s1 | Thus, there is a need in allocating competitive alternatives for complementary metal-oxide-semiconductor (CMOS) technologies. | background 0.90 | 0.04 | 0.03 | asserted 0.98 |
| s2 | Superconducting platforms, such as rapid single flux quantum (RSFQ) lack electric resistance and excel in power efficiency and time performance. | background 1.00 | 0.05 | 0.03 | asserted 1.00 |
| s3 | However, traditional RSFQs require 3D geometry for their Josephson junctions (JJs) imposing a large footprint, and hence preventing device miniaturization and increasing processing time. | background 0.61 | 0.05 | 0.03 | asserted 1.00 |
| s4 | Here, we demonstrate that RSFQ logic circuits of planar geometry with weak-link bridges are scalable, relatively easy to process and are CMOS-compatible on a Si chip. | contribution 1.00 | 0.94 | 0.46 | asserted 1.00 |
| s5 | Universal logic gates, as well as combinational arithmetic circuiting that are based on these devices are demonstrated. | contribution 0.82 | 0.92 | 0.08 | asserted 1.00 |
| s6 | The power consumption and processing time of these logic circuits were as low as 0.8 nW and 13 ps, an order of magnitude improvement with respect to the equivalent traditional-RSFQ logic circuits and two orders of magnitude with respect to CMOS. | result 1.00 | 0.94 | 0.37 | asserted 1.00 |
| s7 | The competitive performance of planar RSFQ logic circuits renders them for promising CMOS substitutes, especially in the supercomputational realm. | interpretation 1.00 | 0.37 | 0.80 | asserted 0.61 |
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The paper
Original abstract
The rapid-pace growing demand for high-performance computation and big-data manipulation entails substantial increase in global power consumption, and challenging thermal management. Thus, there is a need in allocating competitive alternatives for complementary metal-oxide-semiconductor (CMOS) technologies. Superconducting platforms, such as rapid single flux quantum (RSFQ) lack electric resistance and excel in power efficiency and time performance. However, traditional RSFQs require 3D geometry for their Josephson junctions (JJs) imposing a large footprint, and hence preventing device miniaturization and increasing processing time. Here, we demonstrate that RSFQ logic circuits of planar geometry with weak-link bridges are scalable, relatively easy to process and are CMOS-compatible on a Si chip. Universal logic gates, as well as combinational arithmetic circuiting that are based on these devices are demonstrated. The power consumption and processing time of these logic circuits were as low as 0.8 nW and 13 ps, an order of magnitude improvement with respect to the equivalent traditional-RSFQ logic circuits and two orders of magnitude with respect to CMOS. The competitive performance of planar RSFQ logic circuits renders them for promising CMOS substitutes, especially in the supercomputational realm.
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