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arxiv: 2409.17902 · v1 · submitted 2024-09-26 · 💻 cs.CR · cs.LG

Designing Short-Stage CDC-XPUFs: Balancing Reliability, Cost, and Security in IoT Devices

Pith reviewed 2026-05-23 21:01 UTC · model grok-4.3

classification 💻 cs.CR cs.LG
keywords CDC-XPUFPhysically Unclonable FunctionIoT securitymachine learning attacksreliability attackspre-selection strategyhardware overhead
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The pith

Optimized short-stage CDC-XPUFs with pre-selection lower hardware overhead while resisting ML and reliability attacks on IoT devices.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper examines Component-Differentially Challenged XOR-PUFs as an alternative to traditional arbiter PUFs that fall to machine learning and reliability attacks. It introduces a design that adds a pre-selection step to improve response reliability and uses a short-stage lightweight architecture to cut hardware costs. Rigorous testing of this combination shows reduced resource consumption, retained resistance to modeling attacks, and higher reliability that blocks reliability-based attacks. These properties position the design as a practical option for generating unique keys inside power- and area-limited IoT hardware.

Core claim

An optimized CDC-XPUF that incorporates pre-selection and a novel short-stage architecture significantly lowers resource consumption, maintains strong resistance to machine learning attacks, and improves reliability, thereby mitigating reliability-based attacks.

What carries the argument

The pre-selection strategy applied to short-stage Component-Differentially Challenged XOR-PUFs, which filters for reliable challenge-response pairs while keeping the overall circuit compact.

If this is right

  • The design supports key generation in resource-constrained IoT nodes without the overhead of longer-stage XOR-PUFs.
  • Resistance to both modeling and reliability attacks is retained after the optimizations.
  • Reliability improvements directly reduce the success rate of attacks that exploit unstable responses.
  • The approach balances the three goals of security, reliability, and cost in a single PUF instance.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same pre-selection idea could be tested on other PUF families to see whether similar overhead reductions appear.
  • If the short-stage structure scales to larger challenge spaces, it might support higher-entropy keys without proportional area growth.
  • Deployment would still require side-channel analysis to confirm that the added selection logic does not create timing or power leaks.

Load-bearing premise

The pre-selection strategy and short-stage architecture can be implemented without introducing new attack surfaces or unacceptable area trade-offs.

What would settle it

An independent hardware implementation that either exceeds the claimed resource savings or allows an ML model to predict responses with accuracy above the paper's reported thresholds.

Figures

Figures reproduced from arXiv: 2409.17902 by Gaoxiang Li, Yu Zhuang.

Figure 1
Figure 1. Figure 1: showcases a simple representation of an Arbiter PUF. An n-bit Arbiter PUF consists of n stages, each contain￾ing two multiplexers (MUXs). Upon receiving a rising signal, the signal enters the Arbiter PUF at stage one and splits into two paths. These signals traverse through gates at each stage, with their propagation paths being determined by the challenge [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: An XOR-PUF with 3 sub-stream and n bits of each stream [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Implementation of the pre-selection strategy in an Arbiter PUF, illustrating the conditional path adjustments for enhancing response reliability. [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
read the original abstract

The rapid expansion of Internet of Things (IoT) devices demands robust and resource-efficient security solutions. Physically Unclonable Functions (PUFs), which generate unique cryptographic keys from inherent hardware variations, offer a promising approach. However, traditional PUFs like Arbiter PUFs (APUFs) and XOR Arbiter PUFs (XOR-PUFs) are susceptible to machine learning (ML) and reliability-based attacks. In this study, we investigate Component-Differentially Challenged XOR-PUFs (CDC-XPUFs), a less explored variant, to address these vulnerabilities. We propose an optimized CDC-XPUF design that incorporates a pre-selection strategy to enhance reliability and introduces a novel lightweight architecture to reduce hardware overhead. Rigorous testing demonstrates that our design significantly lowers resource consumption, maintains strong resistance to ML attacks, and improves reliability, effectively mitigating reliability-based attacks. These results highlight the potential of CDC-XPUFs as a secure and efficient candidate for widespread deployment in resource-constrained IoT systems.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 0 minor

Summary. The paper proposes an optimized short-stage Component-Differentially Challenged XOR-PUF (CDC-XPUF) design incorporating a pre-selection strategy for improved reliability and a novel lightweight architecture to reduce hardware overhead. It claims that rigorous empirical testing shows the design lowers resource consumption while maintaining strong resistance to machine learning attacks and mitigating reliability-based attacks, positioning CDC-XPUFs as suitable for resource-constrained IoT devices.

Significance. If the empirical claims hold with supporting data, the work would be significant for PUF-based security in IoT by addressing vulnerabilities in traditional APUFs and XOR-PUFs through a less-explored variant, potentially offering a practical balance of reliability, cost, and security.

major comments (1)
  1. [Abstract] Abstract: The central empirical claim that 'rigorous testing demonstrates that our design significantly lowers resource consumption, maintains strong resistance to ML attacks, and improves reliability' is load-bearing but unsupported, as the manuscript supplies no quantitative metrics, tables, figures, attack models, experimental setup details, or results to allow verification of the asserted gains.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive feedback. We address the concern regarding unsupported empirical claims below.

read point-by-point responses
  1. Referee: [Abstract] Abstract: The central empirical claim that 'rigorous testing demonstrates that our design significantly lowers resource consumption, maintains strong resistance to ML attacks, and improves reliability' is load-bearing but unsupported, as the manuscript supplies no quantitative metrics, tables, figures, attack models, experimental setup details, or results to allow verification of the asserted gains.

    Authors: We agree with the referee that the current manuscript version does not supply the quantitative metrics, tables, figures, attack models, experimental setup details, or results needed to support the abstract's claims. This is a substantive gap. In the revised manuscript we will add a complete experimental section that details the attack models, experimental setups, and quantitative results (with tables and figures) on resource consumption, ML-attack resistance, and reliability improvements, thereby allowing verification of the asserted gains. We will also revise the abstract to align precisely with the new data presented. revision: yes

Circularity Check

0 steps flagged

No significant circularity; claims rest on empirical testing

full rationale

The paper presents a hardware design proposal for short-stage CDC-XPUFs using pre-selection and lightweight architecture. Central claims (lower resource use, ML resistance, improved reliability) are supported by statements of 'rigorous testing' rather than any mathematical derivation, fitted parameters renamed as predictions, or self-citation chains. No equations, uniqueness theorems, or ansatzes appear in the provided abstract or described structure. The design choices are presented as engineering optimizations validated externally by experiments, with no reduction of outputs to inputs by construction. This matches the default expectation for non-circular empirical design papers.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

Abstract-only review; no free parameters, axioms, or invented entities are identifiable.

pith-pipeline@v0.9.0 · 5710 in / 1035 out tokens · 22338 ms · 2026-05-23T21:01:23.050518+00:00 · methodology

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Reference graph

Works this paper leans on

33 extracted references · 33 canonical work pages

  1. [1]

    Controlled phys- ical random functions,

    B. Gassend, D. Clarke, M. Van Dijk, and S. Devadas, “Controlled phys- ical random functions,” in 18th Annual Computer Security Applications Conference, 2002. Proceedings. IEEE, 2002, pp. 149–160

  2. [2]

    Silicon physical random functions,

    ——, “Silicon physical random functions,” in Proceedings of the 9th ACM Conference on Computer and Communications Security, 2002, pp. 148–160

  3. [3]

    A technique to build a secret key in integrated circuits for identification and authentication applications,

    J. W. Lee, D. Lim, B. Gassend, G. E. Suh, M. Van Dijk, and S. Devadas, “A technique to build a secret key in integrated circuits for identification and authentication applications,” in 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No. 04CH37525) . IEEE, 2004, pp. 176–179

  4. [4]

    Physical unclonable functions for device authentication and secret key generation,

    G. E. Suh and S. Devadas, “Physical unclonable functions for device authentication and secret key generation,” in 2007 44th ACM/IEEE Design Automation Conference . IEEE, 2007, pp. 9–14

  5. [5]

    Physical unclon- able functions and applications: A tutorial,

    C. Herder, M.-D. Yu, F. Koushanfar, and S. Devadas, “Physical unclon- able functions and applications: A tutorial,” Proceedings of the IEEE , vol. 102, no. 8, pp. 1126–1141, 2014

  6. [6]

    On the pitfalls of using arbiter-pufs as building blocks,

    G. T. Becker, “On the pitfalls of using arbiter-pufs as building blocks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 8, pp. 1295–1307, 2015

  7. [7]

    Internet of things: Vision, applications and research challenges,

    D. Miorandi, S. Sicari, F. De Pellegrini, and I. Chlamtac, “Internet of things: Vision, applications and research challenges,” Ad hoc networks , vol. 10, no. 7, pp. 1497–1516, 2012

  8. [8]

    A lockdown technique to prevent machine learning on pufs for lightweight authentication,

    M.-D. Yu, M. Hiller, J. Delvaux, R. Sowell, S. Devadas, and I. Ver- bauwhede, “A lockdown technique to prevent machine learning on pufs for lightweight authentication,” IEEE Transactions on Multi-Scale Computing Systems, vol. 2, no. 3, pp. 146–159, 2016

  9. [9]

    Puf modeling attacks on simulated and silicon data,

    U. R ¨uhrmair, J. S ¨olter, F. Sehnke, X. Xu, A. Mahmoud, V . Stoyanova, G. Dror, J. Schmidhuber, W. Burleson, and S. Devadas, “Puf modeling attacks on simulated and silicon data,” IEEE transactions on information forensics and security , vol. 8, no. 11, pp. 1876–1891, 2013

  10. [10]

    Modeling attacks on physical unclonable functions,

    U. R ¨uhrmair, F. Sehnke, J. S¨olter, G. Dror, S. Devadas, and J. Schmidhu- ber, “Modeling attacks on physical unclonable functions,” in Proceed- ings of the 17th ACM conference on Computer and communications security, 2010, pp. 237–249

  11. [11]

    Why attackers win: on the learnability of xor arbiter pufs,

    F. Ganji, S. Tajik, and J.-P. Seifert, “Why attackers win: on the learnability of xor arbiter pufs,” in International Conference on Trust and Trustworthy Computing . Springer, 2015, pp. 22–39

  12. [12]

    Towards fast and accurate machine learning attacks of feed-forward arbiter pufs,

    M. S. Alkatheiri and Y . Zhuang, “Towards fast and accurate machine learning attacks of feed-forward arbiter pufs,” in 2017 IEEE Conference on Dependable and Secure Computing . IEEE, 2017, pp. 181–187

  13. [13]

    An experimental study of the state-of-the-art pufs implemented on fpgas,

    M. S. Alkatheiri, Y . Zhuang, M. Korobkov, and A. R. Sangi, “An experimental study of the state-of-the-art pufs implemented on fpgas,” in 2017 IEEE Conference on Dependable and Secure Computing . IEEE, 2017, pp. 174–180

  14. [14]

    A machine learning- based security vulnerability study on xor pufs for resource-constraint internet of things,

    A. O. Aseeri, Y . Zhuang, and M. S. Alkatheiri, “A machine learning- based security vulnerability study on xor pufs for resource-constraint internet of things,” in 2018 IEEE International Congress on Internet of Things (ICIOT). IEEE, 2018, pp. 49–56

  15. [15]

    A fast deep learning method for security vulnerability study of xor pufs,

    K. T. Mursi, B. Thapaliya, Y . Zhuang, A. O. Aseeri, and M. S. Alkatheiri, “A fast deep learning method for security vulnerability study of xor pufs,” Electronics, vol. 9, no. 10, p. 1715, 2020

  16. [16]

    Why attackers lose: Design and security analysis of arbi- trarily large xor arbiter pufs

    N. Wisiol, C. Graebnitz, M. Margraf, M. Oswald, T. Soroceanu, and B. Zengin, “Why attackers lose: Design and security analysis of arbi- trarily large xor arbiter pufs.”

  17. [17]

    The gap between promise and reality: On the insecurity of xor arbiter pufs,

    G. T. Becker, “The gap between promise and reality: On the insecurity of xor arbiter pufs,” inInternational Workshop on Cryptographic Hardware and Embedded Systems . Springer, 2015, pp. 535–555

  18. [18]

    Side channel modeling attacks on 65nm arbiter pufs exploiting cmos device noise,

    J. Delvaux and I. Verbauwhede, “Side channel modeling attacks on 65nm arbiter pufs exploiting cmos device noise,” in 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) , 2013, pp. 137–142

  19. [19]

    Breaking the lightweight secure puf: Understanding the relation of input transformations and machine learning resistance,

    N. Wisiol, G. T. Becker, M. Margraf, T. A. Soroceanu, J. Tobisch, and B. Zengin, “Breaking the lightweight secure puf: Understanding the relation of input transformations and machine learning resistance,” in International Conference on Smart Card Research and Advanced Applications. Springer, 2019, pp. 40–54

  20. [20]

    A subspace pre-learning approach to fast high-accuracy machine learning of large xor pufs with component-differential challenges,

    A. O. Aseeri, Y . Zhuang, and M. S. Alkatheiri, “A subspace pre-learning approach to fast high-accuracy machine learning of large xor pufs with component-differential challenges,” in 2018 IEEE International Conference on Big Data (Big Data) . IEEE, 2018, pp. 1563–1568

  21. [21]

    Experimental examination of component- differentially-challenged xor puf circuits,

    K. T. Mursi and Y . Zhuang, “Experimental examination of component- differentially-challenged xor puf circuits,” in Journal of Physics: Con- ference Series, vol. 1729, no. 1. IOP Publishing, 2021, p. 012006

  22. [22]

    A new security boundary of component differentially challenged xor pufs against machine learning modeling attacks,

    G. Li, K. Mursi, Y . Zhuang, A. Aseeri, and M. Alkatheiri, “A new security boundary of component differentially challenged xor pufs against machine learning modeling attacks,” International Journal of Computer Networks and Communications , 06 2022

  23. [23]

    Extracting secret keys from integrated circuits in master thesis,

    D. Lim, “Extracting secret keys from integrated circuits in master thesis,” Massachusetts Institute of Technology , 2004

  24. [24]

    Deep learning based model building attacks on arbiter puf compositions,

    P. Santikellur, A. Bhattacharyay, and R. S. Chakraborty, “Deep learning based model building attacks on arbiter puf compositions,” Cryptology ePrint Archive, Report 2019/566. 2019. Available online: https . . . , Tech. Rep., 2019

  25. [25]

    Neural-network- based modeling attacks on xor arbiter pufs revisited

    N. Wisiol, K. T. Mursi, J.-P. Seifert, and Y . Zhuang, “Neural-network- based modeling attacks on xor arbiter pufs revisited.” IACR Cryptol. ePrint Arch., vol. 2021, p. 555, 2021

  26. [26]

    Machine learning-based vulnerability study of interpose pufs as security primitives for iot networks,

    B. Thapaliya, K. T. Mursi, and Y . Zhuang, “Machine learning-based vulnerability study of interpose pufs as security primitives for iot networks,” in 2021 IEEE International Conference on Networking, Architecture and Storage (NAS) . IEEE, 2021, pp. 1–7

  27. [27]

    Combining optimization objectives: New machine-learning attacks on strong pufs,

    J. Tobisch, A. Aghaie, and G. T. Becker, “Combining optimization objectives: New machine-learning attacks on strong pufs,” Cryptology ePrint Archive, 2020

  28. [28]

    Multiclass classification- based side-channel hybrid attacks on strong pufs,

    W. Liu, R. Wang, X. Qi, L. Jiang, and J. Jing, “Multiclass classification- based side-channel hybrid attacks on strong pufs,” IEEE Transactions on Information Forensics and Security , vol. 17, pp. 924–937, 2022

  29. [29]

    Mlmsa: Multi-label multi-side-channel-information enabled deep learning attacks on apuf variants,

    Y . Gao, J. Yao, L. Pang, W. Yang, A. Fu, S. F. Al-Sarawi, and D. Abbott, “Mlmsa: Multi-label multi-side-channel-information enabled deep learning attacks on apuf variants,”IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems , 2023

  30. [30]

    Alsca: A framework for using auxiliary learning side-channel attacks to model pufs,

    W. Liu, Y . Zhang, Y . Tang, H. Wang, and Q. Wei, “Alsca: A framework for using auxiliary learning side-channel attacks to model pufs,” IEEE Transactions on Information Forensics and Security , vol. 18, pp. 804– 817, 2023

  31. [31]

    A novel reliability attack of physical unclonable functions,

    G. Li and Y . Zhuang, “A novel reliability attack of physical unclonable functions,” 2024. [Online]. Available: https://arxiv.org/abs/2405.13147

  32. [32]

    Quantitative and sta- tistical performance evaluation of arbiter physical unclonable functions on fpgas,

    Y . Hori, T. Yoshida, T. Katashita, and A. Satoh, “Quantitative and sta- tistical performance evaluation of arbiter physical unclonable functions on fpgas,” in Reconfigurable Computing and FPGAs (ReConFig), 2010 International Conference on . IEEE, 2010, pp. 298–303

  33. [33]

    Extracting secret keys from integrated circuits,

    D. Lim, J. W. Lee, B. Gassend, G. E. Suh, M. Van Dijk, and S. Devadas, “Extracting secret keys from integrated circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 10, pp. 1200– 1205, 2005