Paper Citation Record · LEDGER

FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware

As of 8 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 6 inbound Pith citation observations for arXiv:2410.23299.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2410.23299 v1

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 6 of 6 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00

measured 6 of 6 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-07T04:18:23.084403Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-07-03T00:47:30.499918Z

Reference resolution

0 of 0 outbound references displayed

verified exact0
verified fuzzy0
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation 655f67c0-73d6-4a98-83ad-59c58bf4de37 · inbound

LASA: Enhancing SoC Security Verification with LLM-Aided Property Generation cites this paper.

LASA: Enhancing SoC Security Verification with LLM-Aided Property Generation FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware

Reference 23

Resolution: unresolved; no resolver link, observed 2026-08-06T23:29:21.675304Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 98ff1636-de98-4b97-ab8b-3b2b14d63cbc · inbound

SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models cites this paper.

SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware

Reference 78

Resolution: unresolved; no resolver link, observed 2026-08-06T22:55:09.379104Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 34a53360-9e81-4a07-888f-5cd4f8be435a · inbound

Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVA cites this paper.

Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVA FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-07T04:18:23.084403Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 32500853-a472-48d3-8eb4-c177ce6a5462 · inbound

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification cites this paper.

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware

Reference 31

Resolution: unresolved; no resolver link, observed 2026-08-06T19:58:08.613716Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 4b48f656-7762-483c-b8c6-ade08487bf95 · inbound

From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation cites this paper.

From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware

Reference 25

Resolution: verified exact; arxiv_id, observed 2026-05-11T20:41:11.807593Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 0ee511b1-cbfc-46d5-8f16-e56062feb309 · inbound

RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models cites this paper.

RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware

Reference 16

Resolution: verified exact; arxiv_id, observed 2026-07-03T00:47:30.501669Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.