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REVIEW 4 major objections 5 minor 1 cited by

Schemato -- An LLM for Netlist-to-Schematic Conversion

T0 review · 4 major / 5 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read A fine-tuned 8-billion-parameter LLM converts circuit netlists into compilable LTSpice schematics, beating GPT-4o.

desk verdict A plausible first LLM netlist-to-schematic converter, modestly new and honestly reported, but the headline numbers are weakened by test-set selection and the evaluation never touches ML-generated netlists. read the letter →

arxiv 2411.13899 v2 pith:KZASKYAW submitted 2024-11-21 cs.LG cs.AR

Ryoga Matsuo , Stefan Uhlich , Arun Venkitaraman , Andrea Bonetti , Chia-Yu Hsieh , Ali Momeni , Lukas Mauch , Augusto Capone
show 2 more authors
Eisaku Ohbuchi Lorenzo Servadei
This is my paper · ORCID
classification cs.LGcs.AR
keywords netlist-to-schematicconversionlargelanguagemodelsanalogcircuitdesignLTSpice.ascformatfine-tuninggrapheditdistancestructuralsimilarityelectronicautomation
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper aims to show that translating a circuit netlist -- a plain-text list of components and connections -- into a human-readable schematic can be automated by fine-tuning a large language model, rather than by writing heuristic placement rules or relying on a specific circuit topology. It introduces Schemato, an 8-billion-parameter LLM adapted on human-drawn LTSpice schematic pairs, and reports that on 117 test circuits it generates .asc files that compile 76.07% of the time, compared with 63.25% for the best pretrained LLM. When scores are adjusted for compilation success, its connectivity and visual-similarity scores are 1.8x and 4.3x the best pretrained values. The reason this matters is that ML-generated analog circuits are often returned as netlists that human designers cannot inspect directly, so fast schematic recovery would let designer knowledge feed back into ML design loops.

What carries the argument

The machinery is instruction fine-tuning of an 8-billion-parameter language model on paired netlist and .asc data, where the schematic file is treated as the model's target translation. Prompt design carries part of the load: one prompt variant tells the model to begin with 'Version 4' and a SHEET line carrying the reference schematic's sheet size, and that single addition has a large effect on visual similarity in the fine-tuned models. Data augmentation randomly shuffles the order of SYMBOL/SYMATTR lines so the model learns that line ordering is irrelevant to the circuit. The evaluation stack -- graph edit distance for connectivity, SSIM for visual similarity, compilation success rate for syntax, and BLEU for text fidelity -- determines which prompt and training epoch become Schemato.

What would settle it

Run Schemato on a batch of netlists produced by an ML-based circuit generator, not derived from human schematics, and measure its compilation success rate and CSR-scaled GED and MSSIM; if those numbers fall back to pretrained-LLM levels, the claim that Schemato is ready for ML-generated designs would be contradicted.

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Extended reading notes

Core claim

The central claim is that netlist-to-schematic conversion can be treated as a text-to-text translation task and solved by supervised fine-tuning of a general LLM, without heuristic layout rules, topology-specific templates, or an explicit aesthetic measure. Schemato starts from the Llama-3.1-8B instruct model and is trained on roughly 45,000 netlist-to-.asc pairs derived from human-drawn LTSpice schematics. On a held-out test set of 117 circuits, it reaches a 76.07% compilation success rate, compared with 63.25% for the best pretrained baseline, and its compilation-scaled average graph-edit-distance score and mean-structural-similarity score are 0.27 and 0.17, 1.8x and 4.3x the best pretrained values. The paper takes this as evidence that a fine-tuned LLM can output schematics that are syntactically valid, topologically faithful, and visually closer to the human reference than any pretrained model.

Load-bearing premise

The load-bearing premise is that netlists extracted from human-drawn LTSpice schematics are representative of the netlists that machine-learning circuit generators will hand to Schemato, because the training and test sets contain only human-drawn examples while the motivation is ML-generated designs.

Editorial extensions

If this is right

  • A designer working with an ML-generated netlist could receive a compilable LTSpice schematic instead of having to draw one by hand, making human review of ML-designed analog circuits practical.
  • Because the conversion is framed as translation and the model is fine-tuned on many topologies, the same trained model applies to diverse circuit types without per-topology templates.
  • The gap in compilation success between fine-tuned and pretrained models shows that most of the improvement comes from task-specific training, not from stronger base-model reasoning.
  • The approach extends to other text-based schematic formats, since the learning procedure does not depend on LTSpice-specific syntax beyond the training data.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The obvious untested scenario is a netlist produced by an ML circuit generator; the dataset contains only human-drawn schematics, so distribution shift in component naming, scale, or topology could lower the reported 76.07% CSR.
  • The paper's own analysis shows that more than half of the training samples contain components seen fewer than ten times, suggesting that rare component geometry is a hidden bottleneck and that a larger or more constrained component library would push reliable conversion beyond five-component circuits.
  • Since GED and MSSIM measure different things, a practical deployment could combine Schemato with a deterministic placement pass to fix geometric layout while keeping the model's topological correctness.
  • The same fine-tuning recipe could be used to learn a specific designer's layout style by training on that designer's own schematics, turning the model into a personalized drafting aid.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper introduces Schemato, a fine-tuned Llama-3.1-8B model that converts SPICE netlists into LTSpice .asc schematic files. The authors create a training set from publicly available LTSpice schematics, preprocess and augment it, and evaluate Schemato against pretrained Llama-3.1-8B and GPT-4o on 117 filtered circuits from the Circuits-LTSpice repository. Using four metrics (GED score, MSSIM, compilation success rate, and BLEU), the paper reports that Schemato achieves 76% CSR and higher GED/MSSIM scores scaled by CSR than the best pretrained models (1.8x and 4.3x, respectively). The paper concludes that Schemato can generate interpretable schematics from netlists and discusses limitations related to component familiarity and circuit size.

Significance. If the reported results hold, the paper presents a potentially useful application of LLMs to an underexplored EDA task: translating netlists into human-readable schematic files. The systematic comparison of prompting strategies, the construction of a curated training set, and the use of multiple evaluation metrics are strengths. However, the paper's central claim—that Schemato supports interpretation of ML-generated netlists—is not directly tested, and the evaluation methodology has load-bearing weaknesses (test-set-based model selection, no confidence intervals, metric computation on compilable outputs only) that affect the reliability of the quantitative claims. The contribution is timely given growing interest in LLMs for analog circuit design, but the evidence as presented is not yet conclusive.

major comments (4)
  1. [Sec. V, Figs. 4-5] The final model is selected using test-set metrics: the prompt variant is chosen based on Table I results, and the fine-tuning epoch (epoch 6) is chosen because it 'demonstrated the best combination of scores in Fig. 4 and Fig. 5,' where both figures are computed on the test set. This means the reported test performance is the result of selecting the best model on the same 117 circuits, which inflates the apparent advantage over baselines and makes the exact margins (1.8x, 4.3x, 76% vs 63%) unreliable. The authors should use the validation set for all model-selection decisions and report test performance only for the final selected model.
  2. [Sec. I, Sec. IV-A] The motivating use case is translating ML-generated netlists into schematics, yet the evaluation uses only netlists derived from human-drawn LTSpice schematics (Circuits-LTSpice). The preprocessing in Sec. IV-A removes .lib/.model lines, renames components, and normalizes coordinates, so the resulting netlists are in a simplified format that may not match the output of ML circuit generators, which often emit subcircuits, non-default symbols, or arbitrary naming. No experiment uses netlists from an ML-based generator, so distribution shift in naming, topology, and scale is unmeasured. The paper's own conclusion (Sec. VI) states that Schemato 'cannot generate schematics containing less familiar or unfamiliar components,' which further limits the generality of the practical-utility claim. The authors should either evaluate on ML-generated netlists or explicitly restrict their claims to the tested distribution.
  3. [Sec. IV-D, Table I] The GED and MSSIM scores are computed only for compilable outputs, and the headline numbers are 'scaled by CSR' (raw score multiplied by CSR). This composite is a nonstandard heuristic: multiplying a quality score by a compilation rate conflates syntactic correctness with structural/visual similarity, and the direction of the bias is unclear. For example, a model that compiles only easy circuits could obtain a high raw score, while a model that compiles many hard circuits could obtain a lower raw score despite better overall performance. The paper does not report confidence intervals for any metric, which is especially problematic given the small test set (117 circuits). The authors should report raw scores on compilable outputs, provide confidence intervals or error bars, and justify the use of CSR-scaled scores as a primary comparison.
  4. [Sec. VI] The limitations section explicitly acknowledges that over half of the training samples (5,227 of 9,907) contain components appearing fewer than 10 times, and that the model struggles with larger circuits and unfamiliar components. These limitations are central to the claimed generalization: the test set is small and composed of 'generic components,' so the favorable results do not establish that Schemato would succeed on the diverse, large, or ML-generated netlists that the introduction motivates. The paper should either provide evidence on such challenging inputs or temper the abstract's claim that Schemato demonstrates 'the potential of Schemato in reliably generating human-intuitive schematics from netlists' to the specific evaluated setting.
minor comments (5)
  1. [Abstract] The phrase 'average graph edit distance score and mean structural similarity index measure, scaled by the compilation success rate that are 1.8x and 4.3x higher' is grammatically awkward and could be misread as comparing raw scores; it should clearly state that the comparison is on CSR-scaled scores.
  2. [Fig. 3] The caption says 'Validations losses are computed after every training epoch,' but the figure shows training and validation loss curves; consider labeling the curves explicitly and correcting the typo 'Validations' to 'Validation'.
  3. [Sec. IV-C] The sentence 'The number of weight updates per epoch is: Ntrain/(Niter*N_GPU*N_batch) = 44,995/(8*8*1) ≈ 703' is missing a division sign in the text; the equation is clear but should be typeset correctly.
  4. [Sec. IV-A] The preprocessing description states 'Remove the lines starting with *, TEXT, RECTANGLE, WINDOW, LINE, and CIRCLE.' It would be helpful to clarify whether this includes lines starting with a semicolon or other comment markers used in SPICE netlists.
  5. [References] Reference [24] has a typo: 'https//github.com/pytorch/torchtune' is missing a colon after 'https'.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the core result is standard supervised fine-tuning with an independent held-out test set; test-set model selection is a leakage concern, not a definitional circularity.

full rationale

Schemato is a fine-tuned LLM trained on netlist-to-.asc pairs and evaluated on a separate held-out set (Circuits-LTSpice). The input-output mapping is not defined in terms of the reported metrics, and no fitted parameter is renamed as a prediction. The pre-processing, data augmentation, prompt variants, and fine-tuning procedure are transparent and externally grounded: the model is trained with cross-entropy on human-drawn schematic pairs, while CSR, GED, MSSIM, and BLEU are computed on test circuits not used for training. The paper's selection of the best prompt and epoch from test-set curves (Fig. 4 and Fig. 5) does create optimistic bias in the final test numbers because the test set is reused for model selection; however, this is a statistical leakage/overfitting concern rather than circularity, since the test metric is not equal by construction to the training objective and the final architecture is not derived from the evaluation result. Self-citations are incidental and not load-bearing, no uniqueness theorem from the authors is invoked to forbid alternatives, and no known result is renamed as a new derivation. The manuscript's own limitation statements about unfamiliar components and larger circuits further indicate that generalization is treated as an empirical question rather than assumed by construction. Accordingly, no circular step can be exhibited from the paper's equations or dependencies.

Assumptions & free parameters 5 free parameters · 4 assumptions · 0 invented entities

The central claim rests on three domain assumptions: compilation as correctness, the proxy metrics, and the match between test distribution and target use case. The free parameters are mostly evaluation and model-selection choices; the most concerning is the use of the test set to select prompt and epoch.

free parameters (5)
  • Prompt variant = Prompt 3
    Selected after comparing five prompt templates; chosen based on test-set GED/MSSIM (Sec. V).
  • Fine-tuning checkpoint epoch = Epoch 6
    Chosen as the best epoch using test-set metrics (Sec. V), despite validation loss rising after epoch 3.
  • LoRA rank = r=8
    Fixed LoRA rank for memory reasons (Sec. IV-C); not swept.
  • LoRA scaling factor = alpha=16
    Fixed scaling factor (Sec. IV-C).
  • GED timeout = 60 seconds
    NetworkX graph edit distance is aborted at 60s, returning the best distance found so far (Sec. IV-D1), which affects GED scores for larger graphs.
assumptions (4)
  • domain assumption LTSpice compilation is a valid and sufficient measure of schematic syntactic correctness
    CSR is defined as the fraction of generated .asc files that compile (Sec. IV-D3); this assumes compilation implies usable schematic.
  • domain assumption GED and MSSIM on compilable outputs are valid proxies for schematic quality and closeness to human design
    These metrics are used to support the claim of accurate connectivity and fidelity (Sec. IV-D1, IV-D2), but they only apply to the subset that compiles.
  • domain assumption Human-designed LTSpice circuits are an adequate training and test distribution for ML-generated netlists
    The task is motivated by ML-generated netlists (Sec. I), but all data originates from human-created schematics (Sec. IV).
  • domain assumption The GED normalization and timeout return a consistent comparison across models
    Normalization uses max node/edge counts and a 60s timeout; behavior on large graphs is approximate (Sec. IV-D1).

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Cite this review

Pith. "Pith review of Schemato -- An LLM for Netlist-to-Schematic Conversion." pith.science (2026). https://pith.science/paper/KZASKYAW

@misc{pith2026241113899,
  author       = {Pith},
  title        = {Pith review of: Schemato -- An LLM for Netlist-to-Schematic Conversion},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/KZASKYAW}},
  note         = {Machine review of arXiv:2411.13899}
}
read the original abstract

Machine learning models are advancing circuit design, particularly in analog circuits. They typically generate netlists that lack human interpretability. This is a problem as human designers heavily rely on the interpretability of circuit diagrams or schematics to intuitively understand, troubleshoot, and develop designs. Hence, to integrate domain knowledge effectively, it is crucial to translate ML-generated netlists into interpretable schematics quickly and accurately. We propose Schemato, a large language model (LLM) for netlist-to-schematic conversion. In particular, we consider our approach in converting netlists to .asc files, text-based schematic description used in LTSpice. Experiments on our circuit dataset show that Schemato achieves up to 76% compilation success rate, surpassing 63% scored by the state-of-the-art LLMs. Furthermore, our experiments show that Schemato generates schematics with an average graph edit distance score and mean structural similarity index measure, scaled by the compilation success rate that are 1.8x and 4.3x higher than the best performing LLMs respectively, demonstrating its ability to generate schematics that are more accurately connected and are closer to the reference human design.

Figures

Figures reproduced from arXiv: 2411.13899 by the authors.

Figure 1
Figure 1. Use case of Schemato: AI conversion of SPICE netlists into human-readable schematics. influence of LLMs, we believe our contribution is both timely and valuable for advancing ML-based approaches for analog design. II. PRELIMINARIES In this section, we present a short review of LLMs followed by a short review of the LTSpice .asc schematic format that builds the basis of our current work. A. Review of LLMs Large Langu… view at source ↗
Figure 2
Figure 2. Zero-shot Prompt 1-3 and one-shot Prompt 4-5 for netlist-to-schematic conversion. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Training and validation losses. Llama-3.1-8B is fine [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (2 more)
Figure 4
Figure 4. Figure 4: GED scores scaled by CSR evaluated with the test set. Llama￾3.1-8B is fine-tuned with (a) Prompt 2, (b) Prompt 3, (c) Prompt 4, and (d) Prompt 5. The missing data points indicate that no generated samples are compilable (i.e. CSR = 0). The number of components in the t…
Figure 5
Figure 5. Figure 5: MSSIM scaled by CSR evaluated with the test set. Llama￾3.1-8B is fine-tuned with (a) Prompt 2, (b) Prompt 3, (c) Prompt 4, and (d) Prompt 5. The missing data points indicate that no generated samples are compilable (i.e. CSR = 0). The number of components in the test c…

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Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. CircuitLM: A Multi-Agent LLM-Aided Design Framework for Generating Circuit Schematics from Natural Language Prompts

    cs.AI 2026-01 reject novelty 5.0 of 10

    A five-stage multi-agent pipeline with retrieval from a component database generates CircuitJSON schematics from natural-language prompts, achieving high ERC pass rates but much lower LLM-judge pass rates.

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    Available: https://www.analog.com/en/resources/ design-tools-and-calculators/ltspice-simulator.html

    [Online]. Available: https://www.analog.com/en/resources/ design-tools-and-calculators/ltspice-simulator.html

Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.