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GraCo -- A Graph Composer for Integrated Circuits

T0 review · 3 major / 5 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read The paper claims that a reinforcement-learning agent which assembles circuits graph by graph and receives SPICE simulation rewards can beat random search, finding a verified inverter in about five times fewer sampling steps and a…

desk verdict A working RL graph-composer for circuit synthesis with a useful consistency-check idea, but the 2.5x NAND2 speedup is a best-of-run artifact and the claims need more runs and stronger baselines. read the letter →

arxiv 2411.13890 v2 pith:2K7N3VV6 submitted 2024-11-21 cs.LG cs.AR

Stefan Uhlich , Andrea Bonetti , Arun Venkitaraman , Ali Momeni , Ryoga Matsuo , Chia-Yu Hsieh , Eisaku Ohbuchi , Lorenzo Servadei This is my paper · ORCID
classification cs.LGcs.AR
keywords circuitsynthesisreinforcementlearninggraphneuralnetworksSPICEsimulationstandardcellsconsistencychecksevolutionstrategiesautoregressivegeneration
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper introduces GraCo, a reinforcement-learning method that builds circuit schematics as graphs, one node and edge at a time, then converts the finished graph into a netlist and scores it with a SPICE simulation. The central claim is that learning to assemble the graph, guided by reward from simulation, is more sample-efficient than random search for small standard-cell design tasks. On an inverter, GraCo with evolution strategies finds a verified cell with roughly five times fewer sampling steps than the random baseline; on a two-input NAND gate, it finds a circuit that is on average 2.5 times faster than the random baseline's best. The paper also shows that graph consistency checks, applied during or after generation, improve the average best reward from 0.88 to 0.90 for the evolution-strategy variant. The framework is deliberately configurable, letting design knowledge enter through reward shaping, step limits, subcircuits, consistency checks, and explicit wiring rules.

What carries the argument

The load-bearing object is the graph itself, with nets and component terminals as nodes and with each component's terminals forming a complete subgraph, so terminal identity needs no edge features. GraCo assembles this graph with a DeeperGCN, a graph convolutional network with skip connections, that reads the partially built graph and outputs logits for the next action, logits for choosing a component, means and log-variances for sizing parameters, and logits connecting each new terminal to an existing net. Two learning algorithms drive the search: RLOO, a REINFORCE variant with a leave-one-out baseline, and evolution strategies with mirrored sampling. The second key mechanism is a set of four graph consistency checks: connected input/output nets, a path from every input to every output, no floating nets, and no isolated subgraphs. These checks can be used to block premature stopping, to resample invalid graphs, or to augment the GCN input features, and they reduce the number of SPICE simulations spent on circuits that would fail anyway.

What would settle it

Run the same GraCo ES configuration on a larger standard cell, such as a 3-input NAND or full adder, with identical wiring rules and step limits scaled to the task; if the sampling-step advantage over random search disappears or becomes negative as the space grows, then the 5x and 2.5x results are artifacts of the small constrained inverter and NAND2 spaces rather than of the learned composer.

Watch

Extended reading notes

Core claim

GraCo's central claim is that circuit synthesis reduces to an autoregressive graph-generation problem that a reinforcement-learning agent can solve with fewer SPICE simulations than a random sampler. At each step the agent chooses one of three actions: add an internal net, add a component with continuously sampled sizing parameters, or stop generation and send the graph to SPICE. The paper reports that training this policy with evolution strategies rather than with RLOO, a leave-one-out-baseline REINFORCE variant, is the key to reliable search: ES finds a verified inverter in about five times fewer steps than random, and for NAND2 it discovers a circuit whose best reward corresponds to a gate that is on average 2.5 times faster than the random baseline's best. Consistency checks that reject invalid graphs before or after simulation make the search more efficient; on the NAND2 task, using all checks together raises the average best reward for the ES variant from 0.88 to 0.90. These results are presented as evidence that topology search and sizing can be learned jointly rather than assumed from a fixed circuit library.

Load-bearing premise

The results assume that with the hand-set step limits (6 for inverter, 10 for NAND2) and mandatory wiring rules (bulk to supply/ground, no supply to gate), the remaining design space is large enough that the learned policy, and not the constraints, produces the reported gain over random search.

Editorial extensions

If this is right

  • If the results hold, topology search and transistor sizing can be optimized in one reinforcement-learning loop rather than in separate fixed-topology sizing steps.
  • The consistency-check mechanism is not tied to a particular component library, so the same four checks should transfer to other graph-based synthesis tasks.
  • Because ES outperformed RLOO on both tasks, exploration-oriented search is a better fit than exploitation-heavy policy gradients when the goal is a single best circuit rather than a reusable policy.
  • Adding subcircuits to the inventory lets designers inject existing IP blocks into the search without changing the underlying graph procedure.
  • Using all consistency checks during or after generation yielded the best average reward for the ES variant, while feeding the checks as extra GCN inputs did not help (0.86).

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A testable extension the paper leaves implicit: on larger design spaces where invalid graphs are more common, pruning with consistency checks should yield a larger speedup than the 5x observed on an inverter.
  • The comparison against random sampling leaves open how GraCo would fare against other learned topology or sizing tools on the same cells; a direct benchmark would clarify where the bounds lie.
  • The paper's single-best-instance goal suggests that an explicit replay buffer of successful circuits, which the authors list as future work, could turn GraCo into a reusable prior for new cells rather than a per-task search.
  • The consistency-check idea is purely graph-theoretic, so it might also apply to other autoregressive graph generators such as molecule synthesis or analog layout exploration.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper proposes GraCo, an autoregressive graph-generation framework for integrated-circuit synthesis in which a graph neural network (DeeperGCN) sequentially adds nets and components, converts the assembled graph to a SPICE netlist, and scores it with a reward derived from transient simulation. Two optimization strategies are considered, REINFORCE with a leave-one-out baseline (RLOO) and evolution strategies (ES), and the framework allows the injection of design knowledge through explicit wiring rules, reward shaping, component limits, and graph consistency checks. Experiments are reported for two standard-cell tasks: an inverter and a two-input NAND gate. The headline claims are that ES finds the inverter with approximately 5× fewer sampling steps than a random baseline and that ES synthesizes a NAND2 gate that is 2.5× faster than the random baseline's best result, with consistency checks improving sampling efficiency. The manuscript describes the task setup, the graph representation, the consistency-check taxonomy, and an ablation table over consistency-check variants.

Significance. If the empirical claims were supported, GraCo would be a genuinely useful contribution to ML-based circuit synthesis: it jointly searches topology and sizing, is not tied to a fixed cell library, and formalizes several ways to inject expert knowledge (wiring rules, consistency checks, subcircuits). The paper is also honest about negative results, such as RLOO's premature convergence, and it reports multi-run data (30 runs for the inverter, 3 runs per NAND2 configuration). The stress-test worry that the design space is too constrained to make learning matter is not supported by the paper's own Table I: even after the mandatory wiring rules, the NAND2 topology space is on the order of 1e8–1e10 configurations. The weakness lies not in the task difficulty but in the reported comparisons: the NAND2 speedup claim is obtained by selecting the best run from different consistency-check settings, which is not a controlled comparison. The framework itself is plausible and the consistency-check ablation is informative, but the headline quantitative claims need to be re-established with paired, statistically grounded comparisons.

major comments (3)
  1. [Sec. V-B, Table II, Eq. (4)] The headline '2.5× faster NAND2' is not supported by the table as reported. The value 2.48 arises from sqrt(4.08e-4 / 6.66e-5), which compares the single best random run under 'Connected in/out nets (during generation)' with the single best ES run under 'No floating nets (GraCo input)'. These are different consistency-check configurations, and the ES run uses a GraCo-input mechanism that the random baseline cannot use. Under the pure 'None' row, the ratio is only sqrt(1.33e-1 / 8.13e-2) ≈ 1.28. Moreover, for the 'All (during generation)' configuration highlighted in the consistency-check discussion, the best random gap (6.77e-2) and best ES gap (6.79e-2) imply essentially no speedup. A fair comparison must be made per configuration, with paired runs and with explicitly reported delay values or confidence intervals, not by post-hoc selection of the best run from 15 different settings.
  2. [Sec. V-B, Table II] The companion claim that ES is 'on average 30% faster than RLOO' is also a best-of-runs comparison, not an average: sqrt(1.34e-4 / 6.66e-5) ≈ 1.42 gives the 30% figure by comparing the single best RLOO gap (Paths after generation, Run 1) with the single best ES gap (No floating nets GraCo input, Run 1). With only three runs per configuration and no per-run delay values, no error bars, and no paired comparison under a fixed configuration, the word 'on average' is misleading. The authors should either report mean/median delays with variability across a fixed setting or soften the claim accordingly.
  3. [Sec. V-A, Fig. 5] The inverter claim of '5× fewer sampling steps' is reported as a median ratio over 30 runs, but the figure does not show confidence intervals, and the text does not state whether the median is computed over successful runs only or over all runs (with failures counted at the 1024-step limit). Because the ratio of medians is a nonlinear statistic, a bootstrap confidence interval or at least explicit median and interquartile ranges should be reported. The current presentation leaves the magnitude of the improvement and its uncertainty unclear, which matters because the 5× figure is one of the two headline contributions.
minor comments (5)
  1. [Abstract and Sec. V-B] The phrase 'random baseline' is used inconsistently: the 2.5× claim compares ES with a random run that uses a consistency check, whereas the pure random baseline without any consistency check is much slower. Please specify which configuration of the random baseline is being compared in each claim.
  2. [Table II] The table reports only 'Optimality gap = 1 − Best reward' without giving the normalization factor m_norm from Eq. (4). Since delay is proportional to sqrt(gap) under the squared error reward, the reader should be told the m_norm used and, ideally, the absolute delay values for the best circuits, to make the speedup interpretation transparent.
  3. [Sec. III-A] The description of the 'No floating nets' check says 'all internal or output nodes are either unconnected or connected to at least two terminal nodes'; the phrase 'unconnected or' appears contradictory to the intent of preventing floating nodes and should be clarified.
  4. [Sec. II-C, Eq. (2)] The entropy regularization term is written as λH(πθ(·|st)) inside the sum over t; it should be made explicit whether H is a per-step entropy and whether the sum runs over all time steps, to avoid ambiguity in the loss definition.
  5. [Fig. 3 and Table I] The label 'until standard gate' in Table I is not defined in the text; please clarify whether it means the number of topologies that produce the standard-cell topology at exactly the minimal number of steps.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity found: GraCo's reward is an explicit objective, consistency checks are structural filters, and benchmarks are external random and SPICE baselines.

full rationale

GraCo's derivation chain is self-contained. The reward function (Eq. 4) is an explicitly specified objective that converts user-set targets for voltages and timings into a scalar reward; it does not secretly encode the discovered circuit or the claimed speedup. The learned policy and its ES perturbations are evaluated against SPICE simulations and compared with a random uniform sampler, which is an external benchmark rather than a fitted input. The consistency checks presented in Sec. III-A are structural validity filters (connected input/output nets, paths between inputs and outputs, no floating nets, no isolated subgraphs) and do not assume the target circuit topology, its timing, or its reward value. No load-bearing step relies on a self-citation: the cited references for DeeperGCN, RLOO, and evolution strategies are standard external sources, and no uniqueness theorem or prior result by the authors is invoked to force the chosen approach. The paper itself states that only the single best instance matters rather than the final policy, and the reported 2.5x NAND2 speedup is computed from the optimality gaps in Table II via Eq. 4; this is a post-hoc best-of-runs evaluation choice that raises a statistical-reporting concern, but it is not a circular derivation. The inverter 5x sampling-step reduction is measured against the random baseline in Fig. 5 using sampling-step and wall-clock distributions. No prediction in the paper reduces, by construction, to its own inputs.

Assumptions & free parameters 6 free parameters · 5 assumptions · 0 invented entities

The central claims rest on the SPICE reward being a faithful proxy, on the graph representation and consistency checks preserving good designs, and on random sampling being a meaningful baseline. These are domain assumptions rather than proven theorems; the paper provides no analysis of the reward landscape, no sensitivity study for hyperparameters, and no comparison to previously published synthesis methods.

free parameters (6)
  • Reward targets, normalization, and saturation thresholds for inverter/NAND2 = Not fully reported (e.g., mtar = 0 delay, rmin from cell specs)
    The reward is the sole learning signal; hand-set values define 'success' and strongly influence which circuits are found. Exact per-task values are not given.
  • Maximum sampling steps = 6 (inverter), 10 (NAND2)
    Caps topology size and difficulty; the design-space bounds in Table I depend on these limits.
  • ES perturbation scale sigma_ES = 0.05
    Exploration noise for evolution strategies; no sensitivity analysis reported.
  • Entropy weight lambda (RLOO) = 0.01
    Chosen to promote exploration in REINFORCE; tuned by hand.
  • Minibatch size and training steps = 256, 1024
    Batch size chosen for leave-one-out baseline stability; training length fixed without convergence analysis.
  • Consistency-check configuration = Best results reported for 'All (during generation)' in ES; 'No floating nets (after generation)' helps random baseline
    The choice of which consistency checks to enable is a modeling decision; the paper selects the configuration after observing results, which introduces selection over configurations.
assumptions (5)
  • domain assumption SPICE simulation of the SkyWater SKY130 PDK accurately captures functional and timing behavior of synthesized circuits.
    All rewards and 'verified circuit' claims come from ngspice transient analysis; no silicon validation or cross-simulator check is provided.
  • domain assumption The nets-and-terminals graph representation is sufficient for the GNN to learn circuit semantics.
    GraCo's actions are based solely on this representation; the paper does not validate that terminal roles (source/drain asymmetry, bulk) are fully captured beyond explicit wiring rules.
  • ad hoc to paper The four consistency checks are sufficient to avoid SPICE-invalid circuits without excluding valuable designs.
    Introduced specifically for GraCo; completeness is asserted, and the paper acknowledges checks can be combined and customized (Sec. III-A).
  • domain assumption Random sampling is a competitive baseline for small design spaces.
    Stated in the abstract and Sec. V with no citation; the design-space size estimates range from 1e3 to 4e19, so this assumption is not uniformly justified.
  • standard math The Bell-number and topology design-space bounds correctly characterize the search space.
    Used to motivate consistency checks; the bounds are presented in Fig. 3 without derivation of the enumeration formula.

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Cite this review

Pith. "Pith review of GraCo -- A Graph Composer for Integrated Circuits." pith.science (2026). https://pith.science/paper/2K7N3VV6

@misc{pith2026241113890,
  author       = {Pith},
  title        = {Pith review of: GraCo -- A Graph Composer for Integrated Circuits},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/2K7N3VV6}},
  note         = {Machine review of arXiv:2411.13890}
}
read the original abstract

Designing integrated circuits involves substantial complexity, posing challenges in revealing its potential applications - from custom digital cells to analog circuits. Despite extensive research over the past decades in building versatile and automated frameworks, there remains open room to explore more computationally efficient AI-based solutions. This paper introduces the graph composer GraCo, a novel method for synthesizing integrated circuits using reinforcement learning (RL). GraCo learns to construct a graph step-by-step, which is then converted into a netlist and simulated with SPICE. We demonstrate that GraCo is highly configurable, enabling the incorporation of prior design knowledge into the framework. We formalize how this prior knowledge can be utilized and, in particular, show that applying consistency checks enhances the efficiency of the sampling process. To evaluate its performance, we compare GraCo to a random baseline, which is known to perform well for smaller design space problems. We demonstrate that GraCo can discover circuits for tasks such as generating standard cells, including the inverter and the two-input NAND (NAND2) gate. Compared to a random baseline, GraCo requires 5x fewer sampling steps to design an inverter and successfully synthesizes a NAND2 gate that is 2.5x faster.

Figures

Figures reproduced from arXiv: 2411.13890 by the authors.

Figure 1
Figure 1. Auto-regressive graph generation in GraCo. At each step, it decides whether to add an internal net, insert a component, or stop the generation process. As an example, we illustrate the design of an inverter consisting of an NMOS and a PMOS transistor. arXiv:2411.13890v2 [cs.LG] 13 Mar 2025 [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Overall framework of GraCo. As an example, we show the design of an inverter with a NMOS and PMOS transistor. II. CIRCUIT DESIGN WITH GraCo In this section, we will explain GraCo, our proposed graph com￾posing approach for the design of integrated circuits. A. Graph Representation of Circuits It is well-established that circuits can be represented as graphs, as shown in studies such as [20]–[23]. In this paper, we u… view at source ↗
Figure 3
Figure 3. Bounds on NAND2 topology design space size (solid: upper [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (3 more)
Figure 4
Figure 4. Figure 4: Two examples of consistency checks. These checks are used [PITH_FULL_IMAGE:figures/full_fig_p003_4.png]
Figure 5
Figure 5. Figure 5: Distribution of sampling steps and wall clock time to find the [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 6
Figure 6. Figure 6: Evolution of generated NAND2 circuits for [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]

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Forward citations

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    Available: https://github.com/google/skywater-pdk

    [Online]. Available: https://github.com/google/skywater-pdk

Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.