Pith. sign in

REVIEW 3 major objections 6 minor 49 references

Reinforcement Learning Policy as Macro Regulator Rather than Macro Placer

T0 review · 3 major / 6 minor · reviewed 2026-08-11 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗ Review JSON

Pith's one-line read This paper claims that recasting RL for macro placement as a refinement regulator—adjusting an existing layout instead of placing from scratch—improves placement quality, PPA metrics, and generalization, and that adding a regularity…

desk verdict The regulator MDP is a genuinely new idea and the system appears to work, but the headline claim that the formulation itself (rather than the DREAMPlace warm start) drives the gains is not yet isolated. read the letter →

arxiv 2412.07167 v1 pith:5PYCNDQM submitted 2024-12-10 cs.LG cs.AI

Ke Xue , Ruo-Tong Chen , Xi Lin , Yunqi Shi , Shixiong Kai , Siyuan Xu , Chao Qian This is my paper · ORCID
classification cs.LGcs.AI
keywords reinforcementlearningmacroplacementrefinementregularitychipdesignhalf-perimeterwirelengthPPAMaskRegulate
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper tries to establish that reinforcement learning for macro placement works better when the policy acts as a regulator that refines an existing placement than as a placer that builds one from scratch. The reason offered is that a regulator sees a complete layout at every step, giving it rich state information and dense, accurate rewards, which from-scratch placers lack. The paper shows that its method, MaskRegulate, improves global half-perimeter wirelength on every tested ICCAD 2015 circuit and reports large PPA gains over the from-scratch RL placer MaskPlace, including 17.08% lower routed wirelength and 37.89% better total negative slack. It also reports better generalization to unseen chips and to the ISPD 2005 benchmark, and it shows that adding a regularity objective—encouraging macros near the chip edge—further improves results. If true, this reframes the role of RL in chip design from generating placements to improving any placement produced by another method.

What carries the argument

The load-bearing mechanism is a reformulated Markov decision process: instead of placing macros one by one onto an empty canvas, the policy modifies one macro at a time on a complete existing layout, with all other macro positions visible in the state. The state is encoded as pixel-level masks—a PositionMask of feasible cells (including cells occupied by not-yet-adjusted macros), a WireMask of HPWL change normalized to $[-1,1]$, and a new RegularMask measuring change in edge proximity—fused by a convolutional encoder-decoder that outputs an action-probability matrix. The reward is a normalized blend $r = \alpha r_{\text{wire}} + (1-\alpha) r_{\text{reg}}$ with $\alpha = 0.7$, trained with proximal policy optimization. This formulation gives the policy dense, accurate reward signals and lets it operate as a regulator that can be applied to any initial placement.

What would settle it

Run the regulator, including the vanilla variant, from a random or empty initial layout while keeping all other training details fixed, or let the from-scratch MaskPlace baseline start from the same DREAMPlace-initialized canvas; if the advantage largely disappears, the regulator formulation itself is not what drives the reported gains.

Watch

Extended reading notes

Core claim

MaskRegulate, an RL policy trained as a macro regulator, consistently outperforms the from-scratch RL placer MaskPlace with which it shares most of its architecture and training settings: on the eight ICCAD 2015 circuits, global HPWL improves on every chip, the average rank across proxy and PPA metrics is best, routed wirelength drops 17.08%, horizontal and vertical congestion overflow drop 73.08% and 38.81%, worst negative slack improves 18.35%, total negative slack improves 37.89%, and the number of violation points drops 46.17%. The same policy generalizes better to unseen chips than a from-scratch placer and can fine-tune placements produced by MaskPlace, AutoDMP, and WireMask-EA. Adding the regularity signal to the state and reward yields higher regularity than all baselines on all eight chips.

Load-bearing premise

The comparison assumes the gains come from the regulator's MDP formulation and not simply from starting with a good DREAMPlace placement, because the vanilla-regulator ablation still uses DREAMPlace initialization and the from-scratch baselines start from an empty canvas, so the effect of initialization alone is never isolated.

Editorial extensions

If this is right

  • RL policies for macro placement can be trained as generic improvement operators that post-process any existing placement, not just as one-shot placers.
  • Because the regulator sees a complete layout at each step, it receives denser and more accurate reward signals, which should shorten training relative to from-scratch placement.
  • Adding a regularity reward pushes macros toward the chip periphery, reducing macro blockage and the congestion and timing problems that blockage causes.
  • A policy trained on a few chips transfers to unseen chips and to other benchmarks, suggesting regulator-style training is a path toward reusable chip-placement policies.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the regulator formulation is genuinely the source of the gains, the same refinement framing could be applied after other weak initial placements, converting any analytical, black-box, or learning-based placer into a hybrid search-plus-RL pipeline.
  • The regularity measure used here, edge proximity $\min\{x, X_{\max}-x\} + \min\{y, Y_{\max}-y\}$, is only one possible operationalization; a testable extension is whether more structured regularity terms, such as alignment or symmetric placement constraints, yield further PPA gains without hurting wirelength.
  • The demonstrated ability to fine-tune placements from several distinct methods hints that a trained regulator could serve as a general placement-polisher in industry flows, but the paper does not yet test the policy on truly out-of-distribution netlist sizes or aspect ratios, so that claim remains open.
Share X Bluesky LinkedIn Reddit HN

Signed reviews

No signed human review yet.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. The paper proposes MaskRegulate, an RL-based macro placement method that acts as a "regulator" by refining an existing placement (obtained from DREAMPlace) rather than placing macros from scratch, and integrates a regularity metric into the state and reward. Experiments on ICCAD 2015 and ISPD 2005 compare against DREAMPlace, AutoDMP, WireMask-EA, and MaskPlace, reporting global HPWL, regularity, and PPA metrics from Cadence Innovus. The central claims are that the regulator formulation improves placement quality and PPA over from-scratch RL placers, that adding regularity further helps, and that the method generalizes better to unseen chips.

Significance. If the regulator formulation is validated, this is a worthwhile contribution: it reframes RL macro placement as a refinement step, which naturally provides denser rewards and allows RL to exploit the output of analytical placers. The paper provides code, reports 5-run means for proxy metrics, compares with several strong baselines, and evaluates PPA with a commercial tool. However, the key causal claim that the MDP reformulation (rather than the DREAMPlace initialization) drives the improvements is not yet established by the reported ablations, and the PPA results rest on single selected runs. These issues are load-bearing for the paper's central narrative.

major comments (3)
  1. [Section 4.2 / Appendix B.1 (Table 6)] The ablation 'Vanilla-MaskRegulate' is described as differing from MaskPlace 'only in the problem formulation,' but the manuscript itself indicates two additional differences. First, Section 4.2 states that MaskRegulate uses DREAMPlace to obtain an initial macro placement, while MaskPlace starts from an empty canvas; the Vanilla-MaskRegulate ablation also starts from that DREAMPlace placement. Second, Section 3.1 modifies the PositionMask so that grids occupied by unadjusted macros become available for placement, which is a different action space from MaskPlace's sequential placement. The training budget also differs (1000 vs 2000 episodes). Consequently, Table 6 cannot isolate the effect of the regulator MDP; the improvement could be largely due to the warm start. I request a controlled experiment that varies initialization independently of the MDP formulation (e.g., allowing MaskPlace to start from a DREAMPlace placement, or training the regulator from an empty canvas), or an equivalent analysis that separates these factors.
  2. [Section 4.3 (Table 2)] The generalization comparison between MaskRegulate and MaskPlace has the same confound as the main ablation: MaskRegulate is initialized with DREAMPlace on the test chips, whereas MaskPlace begins from an empty canvas. The claim of superior generalization (Section 4.3) therefore conflates initialization with the regulator formulation. The controlled experiment suggested above is also needed here to support the generalization claim.
  3. [Section 4.1 (Table 1)] PPA metrics are measured on a single selected run per method (the run with the best global HPWL), with no variance or multiple independent runs reported. Since the headline PPA improvements (e.g., 17.08% routing wirelength and 37.89% TNS over MaskPlace) are central to the paper's impact, this selection makes the quantitative claims fragile, particularly given that proxy-metric variances in Table 1 are sometimes substantial. Please report PPA for multiple runs or otherwise demonstrate that the reported improvements are robust to run-to-run variability.
minor comments (6)
  1. [Abstract] The phrase 'which results in limits useful information' is ungrammatical; it should be 'limits useful information' or 'limited useful information.'
  2. [Section 1] In the sentence 'which is is currently one of the largest open-source benchmarks,' the word 'is' is duplicated.
  3. [Table 1 caption] 'evaluated byCadence Innovus' is missing a space; it should be 'evaluated by Cadence Innovus.'
  4. [Section 3.1 / Figure 2 / Figure 3] The terms 'Regularity Mask' and 'RegularMask' are used interchangeably; standardize the terminology throughout.
  5. [Appendix A.3 (Table 4)] The hyperparameters 'Mask soft coefficient' and 'Grid soft coefficient' are not defined or explained; please clarify their roles.
  6. [Appendix B.4] The sentence 'MaskRegulate consistently improves regularity on all four unseen chips and enhances global HPWL on three chips' is ambiguous because Table 11 shows different improvement patterns across the three source methods; specify exactly which comparison is being summarized.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: MaskRegulate is an empirical refinement method whose PPA claims are judged by an external commercial tool, and no prediction reduces to a fitted parameter or a self-citation chain.

full rationale

The paper's central claim is empirical: an RL policy that refines an existing placement outperforms from-scratch RL placers on proxy and PPA metrics. No theoretical derivation is claimed, and no fitted parameter is relabeled as a prediction. The use of DREAMPlace to obtain the initial macro placement is openly disclosed in Section 4.2 ('For each chip, MaskRegulate uses DREAMPlace to obtain an initial macro placement result to be adjusted'), and the warm-start difference between Vanilla-MaskRegulate and MaskPlace is an experimental design concern rather than a circularity, because the regulator's output is not defined to equal its input and its quality is measured externally by Cadence Innovus. The regularity reward is optimized and then reported as a proxy metric, but this is a standard objective-vs-metric relationship; the paper independently evaluates PPA with a commercial tool, providing an external benchmark, and the trade-off coefficient alpha=0.7 is a fixed hyperparameter, not fitted per chip. Self-citations (e.g., WireMask-BBO [29] and the authors' global-placement paper [34]) are background references used for motivation and comparison, not load-bearing support for the central claim, and no uniqueness theorem or ansatz is imported from the authors' prior work. Consequently, no circular step can be exhibited by quoting an equation or reduction, and the honest finding is no significant circularity.

Assumptions & free parameters 1 free parameters · 3 assumptions · 1 invented entities

The paper introduces one free hyperparameter (alpha), relies on domain assumptions about the regularity metric, the quality of DREAMPlace initializations, and HPWL as a proxy, and introduces a new reward component (Regularity) that lacks independent external validation.

free parameters (1)
  • trade-off coefficient alpha = 0.7
    Chosen after sensitivity analysis (Figure 4) to balance HPWL and regularity rewards; fixed across all chips, not fitted per benchmark.
assumptions (3)
  • domain assumption Regularity, defined as sum of Manhattan distances to nearest chip edges, is a valid proxy for manufacturability and performance
    Invoked in Section 3.2; the paper argues edge placement prevents macro blockage, but the exact metric form is hand-designed and not externally validated.
  • domain assumption DREAMPlace provides a sufficiently good initial macro placement that refinement can improve
    MaskRegulate is initialized with DREAMPlace placements in all experiments; if the initial placement were poor or adversarial, the regulator's advantage may vanish.
  • domain assumption HPWL (macro-level and global) is a reliable proxy for PPA outcomes
    Used as the wirelength reward and as the selection criterion for PPA evaluation; standard in the field but an approximation.
invented entities (1)
  • Regularity reward and RegularMask
    purpose: Reward shaping to push macros toward chip edges
    A new training signal and input mask introduced by the paper; its external validity is only tested through downstream PPA in the same paper, not against external benchmarks or predictions.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Reinforcement Learning Policy as Macro Regulator Rather than Macro Placer." pith.science (2026). https://pith.science/paper/5PYCNDQM

@misc{pith2026241207167,
  author       = {Pith},
  title        = {Pith review of: Reinforcement Learning Policy as Macro Regulator Rather than Macro Placer},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/5PYCNDQM}},
  note         = {Machine review of arXiv:2412.07167}
}
read the original abstract

In modern chip design, placement aims at placing millions of circuit modules, which is an essential step that significantly influences power, performance, and area (PPA) metrics. Recently, reinforcement learning (RL) has emerged as a promising technique for improving placement quality, especially macro placement. However, current RL-based placement methods suffer from long training times, low generalization ability, and inability to guarantee PPA results. A key issue lies in the problem formulation, i.e., using RL to place from scratch, which results in limits useful information and inaccurate rewards during the training process. In this work, we propose an approach that utilizes RL for the refinement stage, which allows the RL policy to learn how to adjust existing placement layouts, thereby receiving sufficient information for the policy to act and obtain relatively dense and precise rewards. Additionally, we introduce the concept of regularity during training, which is considered an important metric in the chip design industry but is often overlooked in current RL placement methods. We evaluate our approach on the ISPD 2005 and ICCAD 2015 benchmark, comparing the global half-perimeter wirelength and regularity of our proposed method against several competitive approaches. Besides, we test the PPA performance using commercial software, showing that RL as a regulator can achieve significant PPA improvements. Our RL regulator can fine-tune placements from any method and enhance their quality. Our work opens up new possibilities for the application of RL in placement, providing a more effective and efficient approach to optimizing chip design. Our code is available at \url{https://github.com/lamda-bbo/macro-regulator}.

Figures

Figures reproduced from arXiv: 2412.07167 by the authors.

Figure 1
Figure 1. Placement layouts and congestions of (a) MaskPlace and (b) MaskRegulate on the su [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Overview of MaskRegulate. MaskRegulate shares a similar architecture to MaskPlace [ [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Illustration of chip canvas, PositionMask, WireMask and RegularMask. We use the left [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (2 more)
Figure 4
Figure 4. Figure 4: Illustration of MaskRegulate regulators with varying [PITH_FULL_IMAGE:figures/full_fig_p009_4.png]
Figure 5
Figure 5. Figure 5: Placement layouts and congestions of different methods on the eight ICCAD 2015 bench [PITH_FULL_IMAGE:figures/full_fig_p010_5.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

49 extracted references · 46 canonical work pages

  1. [26]

    Y . Pu, T. Chen, Z. He, C. Bai, H. Zheng, Y . Lin, and B. Yu. Incremacro: Incremental macro placement refinement. In Proceedings of the 2024 International Symposium on Physical Design , pages 169–176, 2024

    work page 2024

  2. [1]

    Agnesina, P

    A. Agnesina, P. Rajvanshi, T. Yang, G. Pradipta, A. Jiao, B. Keller, B. Khailany, and H. Ren. AutoDMP: Automated DREAMPlace-based macro placement. In Proceedings of the 27th International Symposium on Physical Design , pages 149–157, Virtual, 2023

    work page 2023

  3. [2]

    A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov, and A. Zelikovsky. On wirelength esti- mations for row-based placement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 18(9):1265–1278, 1999

    work page 1999

  4. [3]

    H. Chan, P. Mazumder, and K. Shahookar. Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome. Integration, 12(1):49–77, 1991

    work page 1991

  5. [4]

    Chang, Z

    Y . Chang, Z. Jiang, and T. Chen. Essential issues in analytical placement algorithms. IPSJ Transactions on System LSI Design Methodology , 2:145–166, 2009

    work page 2009

  6. [5]

    Chang, Y .-W

    Y .-C. Chang, Y .-W. Chang, G.-M. Wu, and S.-W. Wu. B*-trees: A new representation for non-slicing floorplans. In Proceedings of the 37th Annual Design Automation Conference, pages 458–463, Los Angeles, CA, 2000

    work page 2000

  7. [6]

    Chen, Z.-W

    T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y .-W. Chang. Ntuplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 27(7):1228–1240, 2008

    work page 2008

  8. [7]

    Cheng, A

    C.-K. Cheng, A. B. Kahng, I. Kang, and L. Wang. Replace: Advancing solution quality and routability validation in global placement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 38(9):1717–1730, 2018

    work page 2018

Show all 49 references
  1. [8]

    Cheng, X

    R. Cheng, X. Lyu, Y . Li, J. Ye, J. Hao, and J. Yan. The policy-gradient placement and generative routing neural networks for chip design. In Advances in Neural Information Processing Systems 35, New Orleans, LA, 2022

    2022

  2. [9]

    Cheng and J

    R. Cheng and J. Yan. On joint learning for solving placement and routing in chip design. In Advances in Neural Information Processing Systems 34 , pages 16508–16519, Virtual, 2021

    2021

  3. [10]

    Z. Geng, J. Wang, Z. Liu, S. Xu, Z. Tang, M. Yuan, H. Jianye, Y . Zhang, and F. Wu. Rein- forcement learning within tree search for fast macro placement. In Proceedings of the 41st International Conference on Machine Learning , 2024

    2024

  4. [11]

    X. He, T. Huang, L. Xiao, H. Tian, and E. F. Y . Young. Ripple: A robust and effective routability- driven placer. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(10):1546–1556, 2013

    2013

  5. [12]

    X. Hong, G. Huang, Y . Cai, J. Gu, S. Dong, C.-K. Cheng, and J. Gu. Corner block list: An effective and efficient topological representation of non-slicing floorplan. In Proceedings of the 13th IEEE/ACM International Conference on Computer Aided Design , pages 8–12, San Jose, CA, 2000

    2000

  6. [13]

    A. B. Kahng and S. Reda. A tale of two nets: Studies of wirelength progression in physical de- sign. In Proceedings of the 7th International Workshop on System-level Interconnect Prediction , pages 17–24, Munich, Germany, 2006

    2006

  7. [14]

    M. Kim, J. Hu, J. Li, and N. Viswanathan. ICCAD-2015 CAD contest in incremental timing- driven placement and benchmark suite. In Proceedings of the IEEE/ACM International Confer- ence on Computer-Aided Design , pages 921–926, Austin, TX, 2015

    2015

  8. [15]

    Y . Lai, J. Liu, Z. Tang, B. Wang, J. Hao, and P. Luo. Chipformer: Transferable chip placement via offline decision transformer. In Proceedings of the 40th International Conference on Machine Learning, pages 18346–18364, Honolulu, HA, 2023

    2023

  9. [16]

    Y . Lai, Y . Mu, and P. Luo. Maskplace: Fast chip placement via reinforced visual representation learning. In Advances in Neural Information Processing Systems 35 , New Orleans, LA, 2022. 11

    2022

  10. [17]

    P. Liao, D. Guo, Z. Guo, S. Liu, Y . Lin, and B. Yu. Dreamplace 4.0: Timing-driven placement with momentum-based net weighting and lagrangian-based refinement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 42(10):3374–3387, 2023

    2023

  11. [18]

    T. Lin, C. C. N. Chu, and G. Wu. POLAR 3.0: An ultrafast global placement engine. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design , pages 520–527, Austin, TX, 2015

    2015

  12. [19]

    Y . Lin, Z. Jiang, J. Gu, W. Li, S. Dhar, H. Ren, B. Khailany, and D. Z. Pan. DREAMPlace: Deep learning toolkit-enabled gpu acceleration for modern VLSI placement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 40(4):748–761, 2020

    2020

  13. [20]

    J. Lu, P. Chen, C.-C. Chang, L. Sha, D. J.-H. Huang, C.-C. Teng, and C.-K. Cheng. ePlace: Electrostatics-based placement using fast Fourier transform and Nesterov’s method. ACM Transactions on Design Automation of Electronic Systems , 20(2):1–34, 2015

    2015

  14. [21]

    MacMillen, R

    D. MacMillen, R. Camposano, D. Hill, and T. W. Williams. An industrial view of electronic design automation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(12):1428–1448, 2000

    2000

  15. [22]

    I. L. Markov, J. Hu, and M.-C. Kim. Progress and challenges in VLSI placement research. In Proceedings of the 25th International Conference on Computer-Aided Design , pages 275–282, San Jose, CA, 2012

    2012

  16. [23]

    Mirhoseini, A

    A. Mirhoseini, A. Goldie, M. Yazgan, J. W. Jiang, E. Songhori, S. Wang, Y .-J. Lee, E. Johnson, O. Pathak, A. Nazi, et al. A graph placement methodology for fast chip design. Nature, 594(7862):207–212, 2021

    2021

  17. [24]

    Murata, K

    H. Murata, K. Fujiyoshi, S. Nakatake, and Y . Kajitani. VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(12):1518–1524, 1996

    1996

  18. [25]

    G.-J. Nam, C. J. Alpert, P. Villarrubia, B. Winter, and M. Yildiz. The ISPD2005 placement contest and benchmark suite. In Proceedings of the 9th International Symposium on Physical Design, pages 216–220, San Francisco, CA, 2005

    2005

  19. [27]

    Schulman, F

    J. Schulman, F. Wolski, P. Dhariwal, A. Radford, and O. Klimov. Proximal policy optimization algorithms. arXiv preprint arXiv:1707.06347, 2017

    2017 arXiv

  20. [28]

    Shahookar and P

    K. Shahookar and P. Mazumder. VLSI cell placement techniques. ACM Computing Surveys, 23(2):143–220, 1991

    1991

  21. [29]

    Y . Shi, K. Xue, L. Song, and C. Qian. Macro placement by wire-mask-guided black-box optimization. In Advances in Neural Information Processing Systems 36 , New Orleans, LA, 2023

    2023

  22. [30]

    Spindler and F

    P. Spindler and F. M. Johannes. Fast and accurate routing demand estimation for efficient routability-driven placement. In Proceedings of the 14th Conference on Design, Automation & Test in Europe, pages 1–6, Nice, France, 2007

    2007

  23. [31]

    R. S. Sutton and A. G. Barto. Reinforcement Learning: An Introduction . MIT Press, 2018

    2018

  24. [32]

    Tang and X

    M. Tang and X. Yao. A memetic algorithm for VLSI floorplanning. IEEE Transactions on Systems, Man, and Cybernetics , 37(1):62–69, 2007

    2007

  25. [33]

    Vashisht, H

    D. Vashisht, H. Rampal, H. Liao, Y . Lu, D. Shanbhag, E. Fallon, and L. B. Kara. Placement in integrated circuits using cyclic reinforcement learning and simulated annealing. arXiv preprint arXiv:2011.07577, 2020

    2011 arXiv

  26. [34]

    Net 1"(in green) connects modules M 1, M 2 and M 3 using wires through pins P (1,1), P (2,1) and P (3,1), while

    K. Xue, X. Lin, Y . Shi, S. Kai, S. Xu, and C. Qian. Escaping local optima in global placement. arXiv preprint arXiv:2402.18311, 2024. 12 A Implementation Details A.1 Benchmarks The detailed statistics of our benchmarks are listed in Table 3. Table 3: Detailed statistics of th...

    2024 arXiv

  27. [35]

    Guidelines: • The answer NA means that the abstract and introduction do not include the claims made in the paper

    Claims Question: Do the main claims made in the abstract and introduction accurately reflect the paper’s contributions and scope? Answer: [Yes] Justification: See the last sentence of abstract and last paragraph of introduction. Guidelines: • The answer NA means that the abstr...

  28. [36]

    Limitations

    Limitations Question: Does the paper discuss the limitations of the work performed by the authors? Answer: [Yes] Justification: See the last paragraph of the paper. Guidelines: • The answer NA means that the paper has no limitation while the answer No means that the paper has ...

  29. [37]

    Guidelines: • The answer NA means that the paper does not include theoretical results

    Theory Assumptions and Proofs Question: For each theoretical result, does the paper provide the full set of assumptions and a complete (and correct) proof? Answer: [NA] 18 Justification: There is no theoretical results in this paper. Guidelines: • The answer NA means that the ...

  30. [38]

    Guidelines: • The answer NA means that the paper does not include experiments

    Experimental Result Reproducibility Question: Does the paper fully disclose all the information needed to reproduce the main ex- perimental results of the paper to the extent that it affects the main claims and/or conclusions of the paper (regardless of whether the code and da...

  31. [39]

    Guidelines: • The answer NA means that paper does not include experiments requiring code

    Open access to data and code Question: Does the paper provide open access to the data and code, with sufficient instruc- tions to faithfully reproduce the main experimental results, as described in supplemental material? 19 Answer: [Yes] Justification: We have provided our cod...

  32. [40]

    Guidelines: • The answer NA means that the paper does not include experiments

    Experimental Setting/Details Question: Does the paper specify all the training and test details (e.g., data splits, hyper- parameters, how they were chosen, type of optimizer, etc.) necessary to understand the results? Answer: [Yes] Justification: We have provided experimental...

  33. [41]

    Please see Table 1

    Experiment Statistical Significance Question: Does the paper report error bars suitably and correctly defined or other appropriate information about the statistical significance of the experiments? Answer: [Yes] Justification: We have reported the error bars in our experiments...

  34. [42]

    Guidelines: • The answer NA means that the paper does not include experiments

    Experiments Compute Resources Question: For each experiment, does the paper provide sufficient information on the com- puter resources (type of compute workers, memory, time of execution) needed to reproduce the experiments? Answer: [Yes] Justification: This information is pro...

  35. [43]

    Guidelines: • The answer NA means that the authors have not reviewed the NeurIPS Code of Ethics

    Code Of Ethics Question: Does the research conducted in the paper conform, in every respect, with the NeurIPS Code of Ethics https://neurips.cc/public/EthicsGuidelines? Answer: [Yes] Justification: We have read the NeurIPS Code of Ethics and follow it. Guidelines: • The answer...

  36. [44]

    Our method proposes a more efficient way of using reinforcement learning for macro placement of chips, which has the potential to enhance the quality of chip design

    Broader Impacts Question: Does the paper discuss both potential positive societal impacts and negative societal impacts of the work performed? Answer: [Yes] Justification: The chip is the core productivity of modern society. Our method proposes a more efficient way of using re...

  37. [45]

    Guidelines: • The answer NA means that the paper poses no such risks

    Safeguards Question: Does the paper describe safeguards that have been put in place for responsible release of data or models that have a high risk for misuse (e.g., pretrained language models, image generators, or scraped datasets)? Answer: [NA] Justification: Our paper has n...

  38. [46]

    Guidelines: • The answer NA means that the paper does not use existing assets

    Licenses for existing assets Question: Are the creators or original owners of assets (e.g., code, data, models), used in the paper, properly credited and are the license and terms of use explicitly mentioned and properly respected? Answer: [Yes] Justification: We cite the orig...

  39. [47]

    Guidelines: • The answer NA means that the paper does not release new assets

    New Assets Question: Are new assets introduced in the paper well documented and is the documentation provided alongside the assets? Answer: [Yes] Justification: We have provided our code and models in our supplymental file. Guidelines: • The answer NA means that the paper does...

  40. [48]

    Guidelines: • The answer NA means that the paper does not involve crowdsourcing nor research with human subjects

    Crowdsourcing and Research with Human Subjects Question: For crowdsourcing experiments and research with human subjects, does the paper include the full text of instructions given to participants and screenshots, if applicable, as well as details about compensation (if any)? A...

  41. [49]

    Guidelines: • The answer NA means that the paper does not involve crowdsourcing nor research with human subjects

    Institutional Review Board (IRB) Approvals or Equivalent for Research with Human Subjects Question: Does the paper describe potential risks incurred by study participants, whether such risks were disclosed to the subjects, and whether Institutional Review Board (IRB) approvals...

Pith tools

Reviewed August 11, 2026 · model on record in the stance chip above.