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REVIEW 3 major objections 4 minor 92 references

Harnessing Nonidealities in Analog In-Memory Computing Circuits: A Physical Modeling Approach for Neuromorphic Systems

T0 review · 3 major / 4 minor · reviewed 2026-08-11 · deepseek-v4-flash

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Pith's one-line read Training physical ODE models of analog in-memory circuits cuts model-to-hardware spike-timing error by an order of magnitude and turns a circuit nonideality into a learnable feature.

desk verdict DSTD is a real, useful training trick with a proof, and the post-layout IMC validation is honest hardware work; just don't take the 20x discrepancy reduction as a general law until the per-synapse nonideality spread is quantified. read the letter →

arxiv 2412.09010 v2 pith:HRYUHAAX submitted 2024-12-12 cs.LG

Yusuke Sakemi , Yuji Okamoto , Takashi Morie , Sou Nobukawa , Takeo Hosomi , Kazuyuki Aihara This is my paper · ORCID
classification cs.LG
keywords analogin-memorycomputingphysicalneuralnetworksreversalpotentialspikingdifferentiablespike-timediscretizationRC-SpikemodelhardwarenonidealitiesODE-basedtraining
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that the nonideal voltage dependence of synaptic currents in charge-domain in-memory computing circuits can be modeled exactly as reversal potentials in an ODE-based spiking neuron model, and that training the resulting physical neural network eliminates most of the model-to-hardware gap. On a post-layout sky130 circuit, the output-layer spike-timing error drops from 39.04 ns for conventional ANN mapping to 1.97 ns for the physics-based mapping. To make such training tractable at scale, the paper introduces differentiable spike-time discretization (DSTD), which reduces computational cost from quadratic to linear in spike count and enables convolutional networks on CIFAR-10. The authors further show that reversal potentials, usually considered a defect, can improve learning performance when the model accounts for them.

What carries the argument

The central object is the RC-Spike model, a spiking neuron whose membrane potential evolves as $dv/dt = -f(t) v + g(t)$ with reversal potentials $E^\pm_{\mathrm{rev}}$ bounding the membrane potential; it reduces to ideal charge-domain computing as $|E^\pm_{\mathrm{rev}}|\to\infty$. The load-bearing identity is the linearized MOSFET current model $I_D \approx I(1+\lambda V_{DS})$ (channel-length modulation), which converts the circuit equations into the same ODE form as the neuron model. DSTD then discretizes spike arrival times onto a regular grid with triangular real-valued spike variables, making the whole computation differentiable and cheap while retaining an $O(\Delta\tau^2)$ error bound.

What would settle it

Measure the drain current of the memory MOSFETs over a wider membrane-potential range (e.g., 0.1 V to 1.7 V) and fit the residual against the linear model; if the second derivative of $I_D$ versus $V_{DS}$ exceeds the reported roughly 5% channel-length-modulation variation, retrain the PNN and check whether the 1.97 ns RMSE degrades toward the ANN baseline.

Watch

Extended reading notes

Core claim

On the paper's own terms, the central discovery is that the RC-Spike neuron model, which adds reversal potentials $E^\pm_{\mathrm{rev}}$ to a non-leaky integrate-and-fire dynamics, is mathematically equivalent to a charge-domain IMC circuit whose synaptic currents depend linearly on membrane potential. Because of that equivalence, training the PNN with the measured reversal potentials yields spike timing predictions that match post-layout SPICE simulations with an order-of-magnitude smaller error than mapping a trained ANN. The paper also proves that DSTD approximates the exact ODE solution with error $O(\Delta\tau^2 |E^\pm_{\mathrm{rev}}|^{-1})$, and demonstrates that convolutional networks trained this way reach peak accuracy at finite, non-ideal reversal potentials rather than in the ideal limit.

Load-bearing premise

Everything rests on the claim that the synaptic current depends linearly on membrane potential with constant coefficients $\lambda_N$, $\lambda_P$, and $\lambda_{\mathrm{dis}}$; if that linear fit breaks outside the tested voltage range or under device variation, the circuit-to-model equivalence and the order-of-magnitude error reduction no longer follow.

Editorial extensions

If this is right

  • The PNN-to-IMC mapping reduces output-layer spike-timing RMSE from 39.04 ns to 1.97 ns on the post-layout sky130 circuit.
  • DSTD gives up to 20x speedup and 100x memory reduction for RC-Spike models, and larger gains for TTFS-SNN models.
  • Convolutional RC-Spike networks can be trained on CIFAR-10 with DSTD, with accuracy peaking at finite reversal potentials around $|E^\pm_{\mathrm{rev}}|\approx 3$.
  • ANN-to-IMC mapping with optimal positive/negative weight scaling still degrades markedly when $|E^\pm_{\mathrm{rev}}|<4$, while the physics-trained model does not.
  • The circuit-model equivalence extends to both resistor-based 1T1R synapses and MOSFET current sources with measured $\lambda$ coefficients.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the linear $\lambda$ model holds beyond the fitted 0.46-1.36 V range, the same bottom-up strategy could be applied to other nonidealities such as IR drop or sneak currents by adding them as state-dependent terms.
  • The DSTD error bound suggests that random offset acts as a gradient denoiser, so one could test whether fewer steps suffice for other ODE-based physical neural networks.
  • The claim that nonidealities can be 'harnessed' implies hardware designers might deliberately bias circuits toward regimes with strong, predictable nonlinearity instead of linearizing them.
  • A testable extension is to train the RC-Spike PNN on measured $\lambda_N$, $\lambda_P$, and $\lambda_{\mathrm{dis}}$ from a fabricated chip and compare closed-loop accuracy against post-layout simulation.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The paper proposes a bottom-up, physics-aware training framework for charge-domain analog in-memory computing (IMC). It models IMC circuit nonidealities, specifically the membrane-potential dependence of synaptic currents, as reversal potentials in an ODE-based physical neural network (PNN) called RC-Spike. To make training tractable at scale, the paper introduces differentiable spike-time discretization (DSTD), which approximates continuous spike times by differentiable discrete-time spike variables and is claimed to reduce computational cost from quadratic to linear in the number of input spikes. The authors prove approximation-error bounds for DSTD, demonstrate its use on Fashion-MNIST and CIFAR-10 with both RC-Spike and time-to-first-spike (TTFS) networks, and design a sky130 post-layout IMC circuit. They report that mapping a trained PNN to the circuit reduces output-layer spike-timing RMSE from 39.04 ns (ANN-to-IMC mapping) to 1.97 ns (PNN-to-IMC mapping), an order-of-magnitude improvement, and that finite reversal potentials can improve rather than degrade learning performance.

Significance. If the claims are fully supported, the paper makes a significant contribution. It provides an explicit circuit-to-ODE equivalence for charge-domain IMC with nonideal current sources, an analytical solution for the resulting neuron model, and a scalable training method (DSTD) with convergence guarantees. The CIFAR-10 results show that reversal-potential nonidealities can be harnessed rather than merely compensated, which is a non-obvious and potentially useful finding. The use of a post-layout SPICE simulation in an open-source sky130 process is a concrete and reproducible form of hardware validation, and the paper is careful to state the assumptions of the linearized MOSFET model. However, the central order-of-magnitude hardware claim is currently supported only by a within-sample fit: the nonideality parameters are extracted from the same circuit simulation used for evaluation, and the measured per-synapse spread in channel-length modulation is not propagated to the reported timing error. These issues do not invalidate the approach but they do require additional analysis before the headline claim is fully established.

major comments (3)
  1. [Section 2.3 and SI G.1, Eqs. (70)-(71), Table 2] The order-of-magnitude discrepancy claim rests on representing each MOSFET polarity by a single constant channel-length-modulation coefficient (lambda_N=0.41, lambda_P=0.75), but Figs. 15c-d show that the CLM coefficient varies by roughly 5% with the programmed synaptic current, and the text acknowledges that a current-dependent reversal potential E_rev(.) would be more accurate. No sensitivity analysis bounds how this measured per-synapse spread propagates to the output-layer firing-time RMSE. Because the reported PNN-to-IMC RMSE of 1.97 ns is much smaller than the ANN-to-IMC value of 39.04 ns, the claim may survive a 5% variation, but the paper must quantify this, for example by drawing per-synapse lambda values from the measured spread and re-running the model-to-SPICE comparison, or by deriving an analytic bound. Without this, the central 'at least an order of magnitude' conclusion is not established for the actual circuit with nonuniform devices.
  2. [Section 2.3, Algorithms 5-6, SI F] The PNN-to-IMC validation is a within-sample fit: lambda_N, lambda_P, lambda_dis, the resulting E_rev values, and the current scaling are all extracted from post-layout SPICE simulations of the exact same circuit instance used for the discrepancy evaluation. The 1-dimensional scaling for PNN-to-IMC mapping and the 2-dimensional scaling for ANN-to-IMC mapping are also tuned on the same SPICE results. The manuscript should either present an out-of-sample test (e.g., a different process corner, a Monte Carlo process-variation run, or a hold-out circuit instance) or explicitly qualify the claim as reproduction of the fitted circuit rather than prediction for a new circuit. As written, the 'reduces discrepancy' wording overstates what is demonstrated.
  3. [Section 4.4, Eq. (49), and SI B.2] The main text states the DSTD error as O(Delta_tau^2 |E_rev|^{-1}), but the proof in SI B.1 establishes O(Delta_tau^2) for fixed reversal potential and SI B.2 establishes O(|E_rev|^{-1}) for fixed step size. The combined dependence is not proven; the error expression in B.2 contains terms that depend on both Delta_tau and beta, and the proof does not show a uniform bound of the form C * Delta_tau^2 * beta. Please either supply the combined bound or restate Theorem 1 as two separate convergence statements. This matters because the main text uses the combined order to motivate the efficiency-accuracy trade-off of DSTD.
minor comments (4)
  1. [Section 4.4, Eq. (48)] In Eq. (48), the conditions for the spike variable s^{(l-1)}_{jm} reference t^{(l)}_i, but the variable being defined is the discretized input spike from neuron j, so the condition should refer to t^{(l-1)}_j throughout.
  2. [Section 2.3 and Fig. 5h] The text and figure caption use 'SNN-to-IMC mapping' where the intended term is 'PNN-to-IMC mapping'; this is inconsistent with the rest of the paper and should be corrected.
  3. [Throughout] There are numerous typos and formatting inconsistencies, including 'CIF AR-10' instead of 'CIFAR-10', 'refered' instead of 'referred', 'recieved' instead of 'received', 'membrene' instead of 'membrane', and 'Oder' instead of 'Order'. A careful proofread is needed.
  4. [Table 2 and SI G.2] Table 2 lists the membrane capacitance Cm as 140 fF, while SI G.2 states that the MIMCAP in the layout has a capacitance of 103.3 fF. Please clarify whether the model uses the MIMCAP value plus parasitic capacitance or some other convention.

Circularity Check

1 steps flagged · score 4.0 of 10

Hardware-validated discrepancy reduction is partly in-sample: E_rev is fit from the same SPICE circuit used for evaluation, so the order-of-magnitude model-circuit match is a calibration demonstration, not a fully external prediction.

  1. fitted input called prediction [Methods 4.7 (Algorithm 6) and Results 2.3, Fig. 5h]
    "When computing the RC-Spike model with the IMC circuit, the reversal potentials E±rev was first calculated through circuit simulation, and based on that, the RC-Spike model was trained. Then, the trained weights were mapped onto the IMC circuit (the PNN-to-IMC mapping). ... The RMSE of the firing time differences was 39.04 ns for the ANN-to-IMC mapping and 1.97 ns for the SNN-to-IMC mapping, demonstrating a reduction in error by more than an order of magnitude."

    The headline hardware-validation claim reduces by construction: E±rev (and λN, λP, λdis, the current-scaling parameters in Table 2) are extracted from post-layout SPICE simulations of the very same circuit whose behavior is then compared with the PNN model. With Algorithm 6, the PNN is explicitly built from those fitted nonidealities before the model-to-hardware discrepancy is measured. The 1.97 ns RMSE therefore measures in-sample fit quality of an E_rev-parameterized model to the data from which E_rev was obtained, rather than an external prediction of circuit dynamics.

full rationale

The central methodological contributions—DSTD, its O(M^-2 |E_rev|^-1) convergence proof, and the CIFAR-10/Fashion-MNIST training results—are self-contained and do not depend on a circular chain. The hardware-matching claim is different: the PNN-to-IMC discrepancy reduction is obtained after fitting E_rev and the global λ coefficients to the same post-layout SPICE circuit that is used for the final RMSE comparison. This is a legitimate model-calibration demonstration, but it should not be read as an external prediction of unmeasured hardware behavior. The paper itself acknowledges in SI G.1 that the CLM coefficient varies by about 5% with programmed current and that a membrane-potential-dependent E_rev would be more accurate, further showing that the fitted global-lambda model is an approximation whose residual is not separately validated. There is no evidence that a self-citation chain is load-bearing: the RC-Spike model is re-derived from circuit equations in SI A, not imported solely by citation; DSTD is proven in SI B; and the benchmark comparisons are internal to this paper. Overall, the only material circularity is the in-sample extraction and evaluation of E_rev, which makes the headline 'order of magnitude' hardware reduction partially forced by construction. Weighting that against the independent DSTD and learning results, a score of 4 is appropriate.

Assumptions & free parameters 4 free parameters · 7 assumptions · 0 invented entities

The central claims rest on standard ODE solution techniques, the linear constant-lambda MOSFET approximation, the at-most-one-spike-per-step assumption in the DSTD proof, and fitted nonideality parameters taken from the same circuit used for validation. No new physical entities are introduced.

free parameters (4)
  • lambda_N = 0.41
    CLM coefficient for NMOS synaptic current sources; fitted to post-layout SPICE I-V curves over roughly 0.46-1.36 V (SI G.1, Fig. 15), used to set E+_rev = 2.80 V.
  • lambda_P = 0.75
    CLM coefficient for PMOS synaptic current sources; fitted to post-layout SPICE I-V curves (SI G.1, Fig. 15), used to set E-_rev = -1.53 V.
  • lambda_dis = 0.177
    CLM coefficient for the firing-phase discharger current; fitted from SPICE (SI G.2, Fig. 18), used to set E^dis_rev = 6.44 V and to model the firing phase in the PNN-to-IMC mapping.
  • Current scaling for hardware mapping = Alpha or (Alpha+, Alpha-) optimized per mapping
    For ANN-to-IMC, positive and negative currents are separately scaled and optimized against the same SPICE circuit to compensate nonidealities; for PNN-to-IMC, a global one-dimensional scale is optimized. These fitted scales participate in the reported discrepancy result.
assumptions (7)
  • standard math First-order linear ODEs are solved by variation of parameters.
    Used in Methods 4.1 to derive the analytic membrane-potential solution in Eq. (13).
  • standard math In the DSTD proof, at most one random spike falls in each regular time interval, and f_i and g_i are bounded.
    SI B Remark 2 states this assumption is needed for the O(Delta^2) error bound and is satisfied as the grid becomes fine.
  • domain assumption MOSFET current sources obey the linear approximation I_D approximately I(1 + lambda V_DS) with constant lambda over the operating range.
    SI A.2, Eqs. (70)-(71), is the core physical approximation connecting the circuit ODE to the RC-Spike model.
  • domain assumption Synaptic currents are stepwise and nonleaky, with no decay after spike arrival, and the neuron leak alpha is set to zero.
    Methods 4.1 establishes the input drive as Heaviside-step currents and adopts alpha = 0 for simplicity.
  • domain assumption Each neuron fires at most once per input sample.
    RC-Spike uses separate accumulation and firing phases with a single spike; TTFS-SNN enforces at-most-one firing in Methods 4.2-4.3.
  • domain assumption Charge-domain IMC output can be represented as a capacitor voltage driven by conductance- or current-source-based synaptic currents.
    SI A.1 and A.2 derive the equivalence between the crossbar circuit and the RC-Spike ODE under this representation.
  • ad hoc to paper Numerical experiments mostly use symmetric reversal potentials E+_rev = -E-_rev.
    Unless otherwise stated, experiments set E+_rev = -E-_rev (Methods 4.5 and SI C), while the measured circuit has E+_rev = 2.80 and E-_rev = -1.53, so the symmetric setting is a simplification.

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Cite this review

Pith. "Pith review of Harnessing Nonidealities in Analog In-Memory Computing Circuits: A Physical Modeling Approach for Neuromorphic Systems." pith.science (2026). https://pith.science/paper/HRYUHAAX

@misc{pith2026241209010,
  author       = {Pith},
  title        = {Pith review of: Harnessing Nonidealities in Analog In-Memory Computing Circuits: A Physical Modeling Approach for Neuromorphic Systems},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/HRYUHAAX}},
  note         = {Machine review of arXiv:2412.09010}
}
read the original abstract

Large-scale deep learning models are increasingly constrained by their immense energy consumption, limiting their scalability and applicability for edge intelligence. In-memory computing (IMC) offers a promising solution by addressing the von Neumann bottleneck inherent in traditional deep learning accelerators, significantly reducing energy consumption. However, the analog nature of IMC introduces hardware nonidealities that degrade model performance and reliability. This paper presents a novel approach to directly train physical models of IMC, formulated as ordinary-differential-equation (ODE)-based physical neural networks (PNNs). To enable the training of large-scale networks, we propose a technique called differentiable spike-time discretization (DSTD), which reduces the computational cost of ODE-based PNNs by up to 20 times in speed and 100 times in memory. We demonstrate that such large-scale networks enhance the learning performance by exploiting hardware nonidealities on the CIFAR-10 dataset. The proposed bottom-up methodology is validated through the post-layout SPICE simulations on the IMC circuit with nonideal characteristics using the sky130 process. The proposed PNN approach reduces the discrepancy between the model behavior and circuit dynamics by at least an order of magnitude. This work paves the way for leveraging nonideal physical devices, such as non-volatile resistive memories, for energy-efficient deep learning applications.

Figures

Figures reproduced from arXiv: 2412.09010 by the authors.

Figure 1
Figure 1. Comparison of the dynamics between IMC circuits and biological neurons a. Schematic of charge-domain IMC Circuits. Input signals are delivered through horizontal lines in the form of spikes. Upon receiving these spikes, synaptic currents are induced along the vertical lines due to interactions between the spike signals and the memory elements, denoted as ‘W’ in the figure. The currents are integrated and converted i… view at source ↗
Figure 2
Figure 2. Computation with differentiable spike-time discretization (DSTD). a. Illustration of calculating the firing time of a neuron in the lth layer when spikes are input from the jth and kth neurons in the preceding l−1th layer at times t (l−1) j and t (l−1) k , respectively, using DSTD. First, the discrete time points T (l) m are determined based on an offset time t (l) offset and a time interval ∆τ . The discrete spike … view at source ↗
Figure 3
Figure 3. Basic properties of DSTD. a, b. Errors between the membrane potential values at time 1 when using the exact solution and the approximated solution with DSTD. The membrane potential is obtained from a single-layer, untrained network consisting of 10 neurons, with spike inputs. The data consist of 1000 samples, with each sample containing 1000 input spikes. The input spike times are uniformly distributed over the inte… view at source ↗
Figures from the paper (16 more)
Figure 4
Figure 4. Figure 4: Learning results for RC-Spike models using DSTD. a. The experimental setup. Each data point of a dataset is represented as a three-dimensional tensor xijk. These features are converted into single input spikes, t (0) ijk = 1 − xijk, which are processed by a PNN, which …
Figure 5
Figure 5. Figure 5: Circuit overview. a. Circuit layout of the RC-Spike circuit designed using the sky130 PDK. This circuit forms a two-layer network, with each layer composed of five neurons. The inset shows a schematic overview of the layout. One synapse circuit in the second layer and …
Figure 5
Figure 5. Figure 5: (continued) e. Outline of methods for reproducing the behavior of ANNs and PNNs, the RC￾Spike model in this case, on IMC hardware, termed ANN-to-IMC and PNN-to-IMC mapping, respectively. In the ANN-to-IMC mapping, we first train an ANN model (approximated here using |E…
Figure 6
Figure 6. Figure 6: a. Charge-domain IMC circuits with resistors and transistor switches. The network weights are represented by the conductance values of resistors, denoted as σ (l)± ij . Vdd is the supply voltage and Vgnd is the ground voltage. b. Charge-domain IMC circuits with current…
Figure 7
Figure 7. Figure 7: Schematic of random time points ti and regular time points τi . The time interval between two regular time points is constant and is denoted as ∆τ . The black solid line represents the values of fi or bi , whereas the red solid line represents the approximate values of…
Figure 8
Figure 8. Figure 8: Learning results for convolutional TTFS-SNN models with reversal potentials on Fashion-MNIST dataset. a-c. The time evolution of membrane potentials in the trained network. The top panels show results from the final hidden layer, while the bottom panels display the out…
Figure 9
Figure 9. Figure 9: Dependence of the recognition performance of the RC-Spike model on [PITH_FULL_IMAGE:figures/full_fig_p037_9.png]
Figure 10
Figure 10. Figure 10: Dependence of the recognition performance of the RC-Spike model on [PITH_FULL_IMAGE:figures/full_fig_p038_10.png]
Figure 11
Figure 11. Figure 11: Effect of DSTD steps M during the test phase. Each figure presents the variation in recognition accuracy as a function of the number of DSTD steps M during the test phase using trained models. Specifically, a fully connected RC-Spike model (784-400-400-10) trained on …
Figure 12
Figure 12. Figure 12: We present the results of optimizing the scaling of both positive and negative weights during the [PITH_FULL_IMAGE:figures/full_fig_p041_12.png]
Figure 13
Figure 13. Figure 13: a. Optimization of current values during ANN-to-IMC mapping. A grid search was conducted on positive and negative currents with a step size of 1%. The evaluation metric is the root mean square error (RMSE) between the spike timing of the output layer from the RC-Spike…
Figure 14
Figure 14. Figure 14: a. Layout of the array of synapse circuit blocks. In this schematic, five spike signals from the preceding layer are transferred from the left side. These input spike signals trigger the generation of synaptic currents, which are subsequently summed and directed towar…
Figure 15
Figure 15. Figure 15: Current characteristics of synapse circuits. a. Dependence of drain current on drain voltage for an N-type MOSFET (NMOS) for gate voltages varying in 0.2 V increments from 0.4 V to 0.65 V. b. Dependence of drain current on drain voltage for a P-type MOSFET (PMOS) for …
Figure 16
Figure 16. Figure 16: a. Neuron circuit layout. Synaptic currents are introduced from the top via the synapse circuit. The membrane capacitance is implemented using a metal-insulator-metal capacitor (MIMCAP) between the fourth and fifth metal layers, with dimensions of 7 µm × 7 µm and a ca…
Figure 17
Figure 17. Figure 17: a. Input-output voltage characteristics of the sensing inverter circuit under various bias voltages V sense b . b. Power dissipation characteristics of the sensing inverter circuit under various bias voltages V sense b . 45 [PITH_FULL_IMAGE:figures/full_fig_p045_17.png]
Figure 18
Figure 18. Figure 18: a. Dependence of the discharger circuit current on membrane potential under various bias voltages of V dis b . The vertical black dashed lines in the figures indicate the fitting range of [0.43 V, 1.36 V], where a linear fit is applied to determine the non-ideal chara…

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Pith tools

Reviewed August 11, 2026 · model on record in the stance chip above.