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REVIEW 3 major objections 5 minor 34 references

Design-Agnostic Distributed Timing Fault Injection Monitor With End-to-End Design Automation

T0 review · 3 major / 5 minor · reviewed 2026-08-10 · deepseek-v4-flash

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Pith's one-line read The paper claims that a standard-cell-only clock-pulse-width monitor, generated automatically and distributable across a chip, can detect all twelve clock glitch types and timing fault injections via voltage, electromagnetic interference…

desk verdict Strong silicon validation and a real automation contribution, but the security coverage claim overreaches relative to the attack model. read the letter →

arxiv 2501.09665 v1 pith:LS47SB4D submitted 2025-01-16 eess.SY cs.SY

Yan He , Yumin Su , Kaiyuan Yang This is my paper · ORCID
classification eess.SYcs.SY
keywords timingfaultinjectionattackclockglitchingdelay-lockedloopmonitorhardwaresecuritystandard-celldesignautomationsupplyvoltageglitch
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper tries to establish that a single design-agnostic, fully synthesizable monitor can defend arbitrary digital chips against timing fault injection attacks (FIAs), the low-cost attack class that glitches the clock or disturbs voltage, electromagnetic, or temperature conditions to make registers sample wrong values. The monitor builds a digital replica of the clock's pulse width, locks to the legitimate clock automatically after power-up, and compares every later clock edge against a programmable acceptance window. Any pulse width that falls outside that window raises an alert in the same cycle. A 65 nm prototype occupies 1500 µm², locks from 2 MHz to 1.26 GHz, detects all twelve enumerated clock glitches when two monitors are used, and detects voltage, EMI, and temperature injections. An accompanying automation flow turns a standard-cell library plus frequency and resolution requirements into place-and-route-ready monitor netlists, with 28 nm demonstrations, so timing-FIA protection becomes a drop-in digital IP rather than a custom design effort.

What carries the argument

The load-bearing object is the configurable delay line together with the locking FSM and the acceptance window. The delay line produces three pulses—PMin, PL, and PMax—that set the minimum acceptable delay, the locked replica of the clock's pulse width, and the maximum acceptable delay. At the falling clock edge, the monitor samples whether the replica has already fired and whether it has not yet exceeded the window; any sample pattern other than RMin = 0 and RMax = 1 raises a glitch alert in the same cycle. The automation framework's core mechanism is the delay-line compiler, which simulates candidate standard-cell delay cells, optimizes the coarse, medium, and fine stage sizes against an area model that balances counter area against medium-stage area, runs automatic place and route, verifies post-layout tuning range and resolution, and returns the smallest monitor that satisfies the requested frequency range and resolution.

What would settle it

Inject a fast, localized disturbance, for example a roughly 1 ns supply droop covering only a register's data path while leaving the monitor's replica delay line unaffected, with a clean clock, and observe whether a register samples a wrong value while no alert is raised. If such an experiment produces an undetected timing fault, the claim that the monitor detects timing FIAs via voltage, EM, and temperature as stated is falsified.

Watch

Extended reading notes

Core claim

The central claim is that tracking the clock's positive pulse width with a delay-locked replica catches both entry points of a timing FIA: hijacking the clock changes the pulse width directly, and delay-manipulation attacks change the replica delay relative to the clock, causing the sampled window bits to deviate from the expected pattern. The paper enumerates twelve clock glitch types, shows that one monitor catches nine and a second monitor tracking the negative phase catches the rest, and reports that with an acceptance window of 400 ps or less all twelve are detected at a 250 MHz clock. Voltage glitches down to 120 mV, a 60 mV EMI disturbance, and fast heating or freezing attacks are all detected, while slow temperature drift over the automotive range does not trigger false alerts. The monitor is built entirely from standard cells using a coarse ring-oscillator-counting stage, a thermometer-coded medium stage, and a fine varactor-like stage, with an on-chip finite-state machine that locks in 7 to 26 clock cycles. The only bypass the paper acknowledges is an attack that changes gate delay and then matches the clock pulse width to the new delay, in which case no timing violation exists at the register.

Load-bearing premise

The security claim rests on the assumption that any timing fault injection that actually corrupts a register will change either the clock pulse width or the replica delay enough to fall outside the monitor's acceptance window, and that the monitor's slow-drift tracking will not follow an attack-induced change.

Editorial extensions

If this is right

  • A digital design team can insert timing-FIA protection by running the compiler and instantiating the generated monitor as standard-cell IP, with no analog design, manual layout, or post-silicon calibration.
  • Distributing monitors across the chip in a checkerboard of positive-phase and negative-phase units covers all twelve clock-glitch types and localized voltage, EM, and temperature attacks.
  • Because the monitor slow-tracks clock drift, normal environmental changes such as a -40 to 125 °C temperature ramp do not raise false alerts, while fast heating or freezing attacks do.
  • The same monitor IP scales to other process nodes: the 28 nm runs produce smaller footprints and higher locking frequencies than the measured 65 nm results.
  • The measured power and area overheads, 0.2 to 1.12 mW and 1500 µm² in 65 nm, are small enough that the monitor can be distributed densely rather than placed once per chip.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A residual gap not quantified in the paper is a spatially mismatched attack: if a voltage, EM, or temperature disturbance changes the guarded data path's delay more than it changes the replica delay, the monitor could in principle miss a timing fault that actually corrupts a register; mapping that spatial sensitivity would sharpen the coverage claim.
  • The detection guarantee is conditional on acceptance-window sizing, since the paper shows 400 ps catches all twelve glitch types at 250 MHz while wider windows sacrifice detection of short T5-T12-type events; a designer trading yield against security needs a quantitative window-selection rule.
  • The same architecture could serve as an on-chip clock-integrity sensor for safety-critical control logic, flagging excessive jitter, supply droop, or aging-induced delay drift even when no adversary is present.
  • A testable extension is to place the monitor at increasing distances from the protected logic and repeat the voltage and EM experiments, producing a coverage map that tells designers how densely the monitors must be distributed for a given attack localization.
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Signed reviews

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. This manuscript proposes a fully synthesizable, standard-cell-only timing fault-injection monitor based on a delayed-lock loop that locks to the clock pulse width and raises an alert when the delayed replica falls outside a programmable acceptance window. It also presents an automated design framework that generates and optimizes the monitor from PDK/library inputs, and reports silicon results from a 65 nm test chip (50 DUTs; 2 MHz to 1.26 GHz locking range; 12 on-chip-injected glitch types; voltage, EMI, and temperature injection experiments) as well as two generated 28 nm designs. The central security claim is that the monitor detects all possible clock glitches and all timing FIAs launched through supply voltage, EM, and temperature, provided the acceptance window is set appropriately; the authors acknowledge that the window must be 'reasonable' but do not provide a quantitative method for choosing it in a real deployment.

Significance. If the detection guarantees hold, the work is significant: it offers a small (1500 um2, 0.355 MF2 in 65 nm), low-power (0.487 mW at 250 MHz) standard-cell monitor that is design-agnostic, synthesizable, and automatically instantiated by a toolchain. The silicon validation is unusually extensive for this class of work, including 50 DUTs, the automotive temperature range, 0.5 to 1.4 V supply sweeps, on-chip arbitrary glitch injection at 100 to 500 ps widths, and voltage, EMI, and temperature attack experiments. The end-to-end automation framework, with its delay-line optimization and post-layout verification loop, is a practical contribution. Notably, detection performance is measured against physically injected glitches and attacks rather than derived from the calibration itself, so the central empirical claim is not circular; however, the coverage arguments are incomplete in the ways detailed below. The significance is conditional on clarifying what the monitor actually observes (clock and replica-delay timing, not DUT data-path margins) and on bounding the attack rates and spatial scales to which the alarm is guaranteed.

major comments (3)
  1. [Section III.A and III.B] Section III.A states that 'the only possible way to bypass the monitor is to change the delay of the gates and then match that delay with the pulse width of the clock accordingly,' and concludes that no timing violation exists in that case. This is not implied by the monitor's alert condition. The alert condition in Section III.B samples RMin and RMax from the replica delay line at the falling clock edge; it compares the replica delay with the clock pulse width, not with the actual setup/hold margins of the protected data paths. A localized EM or temperature event can slow a critical data path without changing the delay of a non-co-located replica, producing a setup violation while RMin and RMax remain normal. The paper offers only a qualitative 'checkerboard' placement suggestion in Section III.B and no spatial sensitivity bound. Please provide a quantitative coverage model (for example, the maximum allowed distance between a monitor and the paths it protects, or a bound on how much faster a local attack can move a data path than the replica), or restrict the security claim to attacks that uniformly affect the replica and the clock.
  2. [Section III.E and Table II] Section III.E implements a Full Range Linear Tracking mode with temporal majority voting whose purpose is to follow slow clock drift, and Table II reports that a 2 degC/min temperature drift is treated as 'no glitch.' The same mechanism gives an attacker a slow-ramp bypass: by changing supply voltage or temperature at a rate below the FSM's tracking threshold, the attacker can gradually push the DUT into a timing violation while RL remains locked and no alert is raised. The manuscript does not report the maximum slew rate the tracking loop can follow, nor does it argue that all realistic attack ramps exceed that rate. Please bound this rate (for example, in ppm/s of clock period or in V/s of supply voltage) and demonstrate that the measured voltage, EM, and temperature attacks, or any adversary within the stated threat model, are outside the tracked envelope.
  3. [Section V.C, Fig. 19b, and Section II.A] Fig. 19b shows that the 'all 12 types' detection is achieved only for acceptance windows of 400 ps or smaller at the tested 250 MHz clock; at 500 ps, types T5 through T12 are missed. The acceptance window width is a free design parameter (Section III.A), and no method is given for choosing it from the known clock jitter, the required false-alert rate, and the attack profile. The abstract and conclusion state unqualified detection of 'all twelve types of possible clock glitches,' so the claim should either be qualified by the window setting or accompanied by a design-time procedure that selects the window and proves the selected value covers the intended threat model. In addition, the completeness of the T1-T12 taxonomy is asserted in Section II.A and Fig. 2 rather than demonstrated; the paper should define the class of waveforms it claims to cover or prove that arbitrary glitch waveforms reduce to detectable combinations of the listed types.
minor comments (5)
  1. [Fig. 19b and Section V.C] Please clarify how the 100 trials were distributed across glitch types and acceptance-window settings, and report the false-alert rate at each setting in addition to the miss rate, since the distinction between detection and false positive is central to the 'reasonable acceptance window' discussion.
  2. [Section V.D and Fig. 21] The voltage-glitch experiment injects a supply disturbance but does not state whether the DUT actually produced a faulty output; please state explicitly whether the monitored metric is attack detection or fault detection, and whether the two are distinguished in the measurements.
  3. [Table II] The 'Temperature Drift' row says 'No glitch'; please clarify that this means no false alert was raised during a non-attack drift, rather than that a glitch went undetected.
  4. [Section VI and Table I] The 28 nm rows in Table I are described as post-layout evaluation, but the text should state explicitly near the table that no 28 nm silicon was measured, to avoid the impression that the 28 nm results are as experimentally validated as the 65 nm results.
  5. [Section V.E] The phrase 'validated under a versatile of voltages' should read 'validated under a variety of voltages.'

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: detection claims are backed by direct silicon measurements and physical fault injection, not by a fitted parameter or self-citation chain.

full rationale

The paper's central claims are validated by direct measurement rather than derived from their own inputs. The monitor's alert condition (RMin != 0 or RMax != 1, sampled at the falling clock edge) is the designed detection mechanism itself, and the paper then independently tests that mechanism against injected clock glitches of all 12 enumerated types (Fig. 19b, Fig. 20b), voltage glitches (Fig. 21), EM interference (Fig. 22), and rapid temperature changes (Table II). These are empirical silicon measurements with a fabricated 65 nm chip across 50 DUTs, not predictions computed from fitted parameters. The acceptance window is a programmable detection threshold; the paper openly reports that larger windows miss certain glitch types, which is an honest characterization of a tunable sensitivity trade-off, not a circular 'prediction.' The only self-citation is reference [9], the authors' prior ISSCC paper, used in the sentence 'This article extends [9]' and as background for the basic monitor concept. That citation is not load-bearing here because the present paper provides the full design details, locking FSM, automation framework, and new 28 nm and 65 nm measurement results. The statement that 'the only possible way to bypass the monitor is to change the delay of the gates and then match that delay with the pulse width of the clock accordingly' is a security-assumption argument about replica-DUT coupling, not a circular reduction: it is a correctness/coverage concern, and under the paper's stated attack model the detection claim follows from the measured behavior of the fabricated monitors. No equation in the derivation chain reduces to its own input, and no fitted parameter is renamed as a prediction. Accordingly, the circularity score is 0.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

The listed assumptions and parameters are the load-bearing extras the reader must accept: the attack taxonomy, the replica-to-DUT delay coupling, the threshold-setting premise, and the monotonicity of synthesized delay lines. The paper provides silicon data for 65nm but does not independently justify these assumptions beyond the presented tests.

free parameters (3)
  • Acceptance window width = 100-1600 ps tested; <=400 ps required for all 12 glitch types at 250 MHz
    Programmable threshold set by the user. The paper's all-glitch coverage claim holds only for narrower windows, and the choice trades detection sensitivity against false alarms.
  • Configurable delay line skip steps = 1 medium + 9 fine steps skipped per coarse step; 6 fine steps per medium step
    Introduced in Section III.E to guarantee monotonic delay after automatic place and route. Values are derived from post-layout simulations and are an ad hoc correction.
  • Fine-stage coverage margin = 50% margin
    The framework uses a 50% margin when sizing the fine stage to cover one coarse step. This is a design choice in the automation flow, not derived from performance requirements.
assumptions (4)
  • ad hoc to paper The twelve clock-glitch waveforms T1-T12 exhaust all possible clock glitches.
    Stated in Section II.A as 'without losing generality' but not proven. Coverage claims are relative to this taxonomy.
  • domain assumption A timing FIA either changes the clock pulse width or changes the replica delay line's delay relative to the clock.
    Used in Section III.A bypass argument. Assumes voltage, EM, and temperature affect standard-cell replica paths similarly to DUT critical paths.
  • domain assumption Clock jitter is smaller than the acceptance window, and false alarms can be avoided by choosing the window.
    Section V.C-D relies on this to separate glitches from noise, but no jitter histogram or quantitative false-alarm rate is reported.
  • domain assumption Standard-cell-only delay lines with programmable skips remain monotonic after automatic place and route across PVT.
    Section III.E and Section IV use post-layout simulation to choose skips, but silicon verification is limited to 65nm.

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Cite this review

Pith. "Pith review of Design-Agnostic Distributed Timing Fault Injection Monitor With End-to-End Design Automation." pith.science (2026). https://pith.science/paper/LS47SB4D

@misc{pith2026250109665,
  author       = {Pith},
  title        = {Pith review of: Design-Agnostic Distributed Timing Fault Injection Monitor With End-to-End Design Automation},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/LS47SB4D}},
  note         = {Machine review of arXiv:2501.09665}
}
read the original abstract

Fault injection attacks induce hardware failures in circuits and exploit these faults to compromise the security of the system. It has been demonstrated that FIAs can bypass system security mechanisms, cause faulty outputs, and gain access to secret information. Certain types of FIAs can be mounted with little effort by tampering with clock signals and or the chip operating conditions. To mitigate such low cost, yet powerful attacks, we propose a fully synthesizable and distributable in situ fault injection monitor that employs a delay locked loop to track the pulsewidth of the clock. We further develop a fully automated design framework to optimize and implement the FIA monitors at any process node. Our design is fabricated and verified in 65 nm CMOS technology with a small footprint of 1500 um2. It can lock to clock frequencies from 2 MHz to 1.26 GHz while detecting all 12 types of possible clock glitches, as well as timing FIA injections via the supply voltage, electromagnetic signals, and chip temperature.

Figures

Figures reproduced from arXiv: 2501.09665 by the authors.

Figure 2
Figure 2. A summary of twelve possible types of clock glitches. [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. To alter the logic gates’ delay, an attacker may (a) fault the power [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. (a) WNeg and WPos determine the acceptance window and normal clock jitters should fall inside this window. (b) and (c) depict the scenarios where the clock’s pulse width is shorter or longer than the expected value. the overhead. In summary, adaptive design techniques were developed with highly relevant but different goals as timing FIA monitors. They inspire the design of FIA countermeasures but are not optimal or … view at source ↗
Figures from the paper (15 more)
Figure 6
Figure 6. Figure 6: Implementation of the clock replica and the acceptance window. [PITH_FULL_IMAGE:figures/full_fig_p004_6.png]
Figure 9
Figure 9. Figure 9: Schematic of the Configurable Delay Line (CDL). [PITH_FULL_IMAGE:figures/full_fig_p005_9.png]
Figure 8
Figure 8. Figure 8: (a) A pair of monitors are required to detect all clock glitch types. (b) [PITH_FULL_IMAGE:figures/full_fig_p005_8.png]
Figure 10
Figure 10. Figure 10: (a) The FSM and (b) the locking process to lock to the clock signal. [PITH_FULL_IMAGE:figures/full_fig_p005_10.png]
Figure 12
Figure 12. Figure 12: The end-to-end automated workflow to generate the FIA monitor. [PITH_FULL_IMAGE:figures/full_fig_p006_12.png]
Figure 14
Figure 14. Figure 14: The delay line area breakdown. While the coarse stage’s topology is fixed, the framework still has to optimize the number of stages in RO. A shorter RO leads to a smaller coarse step, which reduces the number of medium cells. However, since the delay line needs to cov…
Figure 13
Figure 13. Figure 13: The flow chart for automating the configurable delay line design. [PITH_FULL_IMAGE:figures/full_fig_p007_13.png]
Figure 16
Figure 16. Figure 16: The locking process is shown in (a) and the delay range and resolution [PITH_FULL_IMAGE:figures/full_fig_p008_16.png]
Figure 17
Figure 17. Figure 17: The locking frequencies across 50 DUTs at 25 [PITH_FULL_IMAGE:figures/full_fig_p008_17.png]
Figure 20
Figure 20. Figure 20: (a) The fast pulse addition circuit. (b) T [PITH_FULL_IMAGE:figures/full_fig_p009_20.png]
Figure 21
Figure 21. Figure 21: (a) Testing setup for the voltage glitch attack. The EMP attack [PITH_FULL_IMAGE:figures/full_fig_p009_21.png]
Figure 24
Figure 24. Figure 24: DUT power across temperature and variations in power across DUTs. [PITH_FULL_IMAGE:figures/full_fig_p010_24.png]
Figure 22
Figure 22. Figure 22: (a) EM attack test setup. (b) Success/fail summary at different RF [PITH_FULL_IMAGE:figures/full_fig_p010_22.png]
Figure 23
Figure 23. Figure 23: The temperature attack testing procedures. [PITH_FULL_IMAGE:figures/full_fig_p010_23.png]
Figure 26
Figure 26. Figure 26: Generated 28nm layout for the fifth row and the sixth row in Table I. [PITH_FULL_IMAGE:figures/full_fig_p011_26.png]

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Pith tools

Reviewed August 10, 2026 · model on record in the stance chip above.