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Supervised Learning for Analog and RF Circuit Design: Benchmarks and Comparative Insights

T0 review · 4 major / 4 minor · reviewed 2026-08-10 · deepseek-v4-flash

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Pith's one-line read This paper argues that supervised machine learning can invert the analog/RF design flow by predicting circuit parameters from performance specifications, with best mean relative errors of 0.30% on an LNA and 0.23% on a receiver.

desk verdict A solid, useful benchmark extension that is undermined by an unsupported headline number and by testing only on the same swept grid used to generate the data. read the letter →

arxiv 2501.11839 v1 pith:WPVRSYJJ submitted 2025-01-21 cs.LG cs.AIcs.AR

Asal Mehradfar , Xuzhe Zhao , Yue Niu , Sara Babakniya , Mahdi Alesheikh , Hamidreza Aghasi , Salman Avestimehr This is my paper · ORCID
classification cs.LGcs.AIcs.AR
keywords analogcircuitdesignRFsupervisedlearninginverseparameterpredictionautomationbenchmarktransformer
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Analog and RF circuit design normally starts with parameters and sweeps them until performance targets are met; this paper inverts that flow and asks a supervised model to predict design parameters directly from a target performance vector. The authors build a simulation dataset covering seven homogeneous circuit blocks and a 28 GHz transmitter/receiver pair, train five model families (MLP, transformer, random forest, k-nearest neighbors, support vector regression), and evaluate not by parameter error but by simulating the predicted parameters and measuring the relative error of the achieved performance. The central result is that the inverse mapping works well on circuits with nearly linear behavior, with mean relative errors of 0.30% for the low-noise amplifier and 0.23% for the receiver when enough training data is available, while strongly nonlinear circuits like power amplifiers remain hard (best mean error around 20%). No model wins everywhere: transformers and MLPs handle simple amplifiers well, random forests win on two-stage amplifiers and VCOs, and k-nearest neighbors is best on large, moderately linear receiver data. The paper's contribution is a comparative evidence base for choosing a model family according to circuit complexity and dataset size.

What carries the argument

The load-bearing object is the supervised inverse map $M: \mathbb{R}^N \to \mathbb{R}^D$ that sends performance specifications to circuit parameters; for heterogeneous circuits the map is a composition of coupled sub-block maps $M_{\text{total}}(X) = f(M_1(x_1), M_2(x_2), M_3(x_3))$, which formalizes why higher dimensionality and block interactions demand more data. The map is trained with an $\ell^1$ loss on parameter values and evaluated through a two-stage pipeline: the model predicts $\hat{y}$, a circuit simulator computes the resulting performance $\hat{x}$, and the reported mean relative error compares $\hat{x}$ to the target $x$. This simulation-in-the-loop evaluation is what makes the accuracy figures meaningful for designers, because it measures end-to-end performance error rather than parameter-space distance.

What would settle it

Take a physically plausible performance target that lies outside the swept range of at least one circuit parameter, or on a combination not representable on the grid, run the trained model, simulate the predicted parameters, and measure the performance relative error; if errors rise sharply (for example, mean error above 10%) across models, the inverse-mapping claim is limited to grid interpolation rather than true design-space coverage.

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Extended reading notes

Core claim

The paper establishes that the conventional analog/RF design loop can be reversed: given a desired performance specification vector $x$, a supervised model $y = M(x)$ predicts a set of circuit parameters, and the predicted parameters are then simulated to verify that the achieved performance matches the request. On the homogeneous benchmark, the low-noise amplifier is effectively solved (0.30% mean relative error with MLP, 100% of errors below 2%), whereas the power amplifier remains the hardest block (19.98% best mean error), showing that circuits with nonlinear trade-offs resist direct inversion. On heterogeneous systems, increasing the training set cuts error by 88%, and the receiver reaches 0.23% mean relative error with k-nearest neighbors, demonstrating that data scale, not model expressivity, is the dominant factor for these systems. The authors also report a model-complexity map: transformers and MLPs dominate on single-stage and cascode amplifiers, random forests on two-stage amplifiers and VCOs, MLP and kNN on the transmitter, and kNN on the receiver; support vector regression is consistently the weakest. The study is presented as a benchmark-oriented extension that turns a dataset into explicit guidelines for when each ML family is appropriate.

Load-bearing premise

The benchmark is generated by sweeping design parameters on a fixed grid and only evaluating on random points from that same grid, so the entire test is interpolation within the swept ranges and nothing is established about requests outside those ranges.

Editorial extensions

If this is right

  • For circuits with near-linear parameter-performance relations, such as the LNA, the paper implies that manual sizing can be replaced by a single forward pass of a supervised model with sub-1% performance error.
  • For complex blocks like the power amplifier, the best observed mean error of about 20% means ML-based sizing is not yet trustworthy for such circuits, and designers should still rely on optimization loops.
  • For heterogeneous systems, the 88% error reduction from more training data shows that investing in simulation data, rather than switching models, is the most direct route to accuracy.
  • The winning model family changes with circuit structure, so a practical workflow needs to select among MLP/transformer, random forest, and kNN based on circuit complexity and dataset size rather than assuming one method is best.
  • The simulation-in-the-loop evaluation protocol should be a standard for future circuit-ML benchmarks, because parameter-space error alone does not tell a designer whether the target performance was met.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial: the reported accuracies are interpolation results on the swept grid; generalizing to arbitrary specification vectors outside the grid is unproven, so the headline 0.23% and 0.30% figures should be read as interpolation quality until an out-of-sample test is run.
  • Editorial: the one-to-many nature of the inverse problem is only implicitly handled; kNN's success on the receiver likely comes from averaging over the many nearby simulated points, which acts as a local regularizer and may explain why it beats global regressors in large datasets.
  • Editorial: a natural next step would be to reformulate the task as constraint satisfaction, with performance ranges as inputs and feasibility as output, reusing the same dataset to measure how often predicted parameter sets actually meet the original specifications.
  • Editorial: the grid-based dataset can be subsampled to produce a sample-efficiency curve for each circuit, giving designers practical guidance on how many simulations they need before an inverse model becomes useful.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 4 minor

Summary. The paper presents a supervised-learning benchmark for analog and RF circuit design, in which models predict circuit parameters from performance specifications. The dataset covers seven homogeneous circuits (common-source amplifier, cascode amplifier, two-stage amplifier, LNA, mixer, VCO, power amplifier) and two heterogeneous 28 GHz systems (transmitter and receiver), generated by sweeping design parameters and simulating performance in Cadence. Five model families are compared: MLP, Transformer, random forest, k-nearest neighbors, and support vector regression, using a random 90/10 train/test split and an end-to-end evaluation where predicted parameters are re-simulated in Cadence to compute relative performance errors. The paper reports best-model selections per circuit and claims that simpler circuits such as the LNA achieve mean relative errors as low as 0.3%, while the receiver achieves 0.23% with kNN, and that the approach reduces errors by 88% with increased training data. The authors provide datasets and code at a GitHub repository.

Significance. If the claims were fully supported, the paper would provide a useful comparative benchmark for ML-assisted analog/RF sizing: it spans a broad set of circuits, applies a consistent simulation-based evaluation that avoids circularity, and makes reproducibility artifacts public. The Cadence-based evaluation is a genuine strength, and the comparison of five model families across nine circuits is a useful empirical resource for practitioners. However, the contribution is primarily empirical; the analytical framing in Section II.A is standard supervised learning, and the headline quantitative claims—especially the 88% error reduction and the best-model selections—require stronger evidence than the paper currently provides. The central limitation is that all test specifications are drawn from the same grid-swept parameter ranges, so the benchmark validates interpolation within that grid rather than prediction for arbitrary or out-of-distribution performance targets.

major comments (4)
  1. [Section V (Experiments) and Section III (Tables I and II)] The evaluation uses a random 90/10 split of datasets generated by sweeping design parameters on fixed grids and simulating the resulting performance metrics. Every test point therefore lies on the image of the training parameter grid, and the reported errors measure interpolation on that grid. This does not validate the central claim, stated in Section II and Eq. (1), that supervised models predict circuit parameters from arbitrary performance specifications. The paper should include at least one held-out evaluation in which target performance vectors are constructed from parameter values not on the swept grid (e.g., continuous random parameters or a held-out parameter region) and re-simulated, or explicitly qualify all accuracy claims as applying only to test specifications that lie on the grid. The issue is load-bearing because Section II itself acknowledges the inverse mapping may be non-unique, making off-grid generalization more important, not less.
  2. [Abstract and Section VI (Discussion)] The abstract's claim of an '88% reduction in errors with increased training data' is not supported by any numerical result reported in the manuscript. Section VI and Figure 15 describe that accuracy improves with more data, but Figure 15 shows only histograms and gives no error values, no training-set sizes, and no baseline from which the 88% reduction is computed. The authors should either report the underlying numbers and define the baseline explicitly, or remove and qualify the claim.
  3. [Section V, Tables V-XIII] The 'best model' selections are often based on tiny differences that may not be statistically meaningful. For example, the Mixer means are 3.22 (Transformer), 3.27 (kNN), 3.28 (MLP), 3.30 (RF and SVR); the VCO means are 6.95 (RF), 7.11 (kNN), 7.42 (SVR), 7.62 (Transformer), 7.70 (MLP), with standard deviations above 50 for several models. Section V states that training was repeated with different random seeds, but no seed variance, confidence intervals, or significance tests are reported anywhere. The best-model narrative in Table XIV should be softened or accompanied by error bars; otherwise readers cannot distinguish systematic superiority from noise.
  4. [Section IV.B, Eq. (4)] The definition of Mean Relative Error is ambiguous. Eq. (4) defines it as an average over N performance metrics for a single performance specification, but the tables report 'Mean' and 'Std' that appear to be statistics over test samples. Please clarify whether the reported mean is the average over the test set of per-sample mean relative errors, and define N and the averaging procedure accordingly. This is needed to reproduce the tables.
minor comments (4)
  1. [Table IV] The Transformer hyperparameter row 'dim_hidden load resistor' appears to be a copy-paste error; it should likely read 'dim_hidden dimension' or similar. The MLP 'dim_layers' value also lists six dimensions for seven layers; please reconcile the layer count.
  2. [Algorithm 2] The evaluation loop is written 'for t = 1 to maxIter', but evaluation is not an iterative training process. This is confusing; a simple 'for each test sample' loop would be clearer.
  3. [Figure 15] The figure caption and text describe the scalability of the approach, but the histograms do not convey quantitative error values or the training-set sizes that were compared. Adding numeric axes or a small table of mean errors versus dataset size would make the scalability claim verifiable.
  4. [Section II.A] The claim that supervised learning provides 'low-variance gradient signals' compared to unsupervised or RL methods is an over-simplification; variance depends on the loss, the model, and the data. This analytical section is not needed for the benchmark contribution and could be shortened.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the benchmark claims are supported by simulator-based closed-loop evaluation, not by a reduction to the training targets.

full rationale

The paper's central claim is that supervised models can map performance specifications x to circuit parameters y, evaluated by simulating the predicted parameters and comparing the resulting performance to the target x (Algorithm 2 and Eq. 3). This evaluation is external to the training loss: the reported mean relative error is computed from Cadence simulation output S(y_hat), not from the fitted y values themselves, so the headline accuracies are not forced by construction. The dataset is generated by sweeping circuit parameters and simulating each point in Cadence (Section III-C), which grounds the data in an independent physical simulator rather than in the model's own predictions. The only self-citation is [19], the authors' prior AICircuit dataset and benchmark, but the present paper adds new models, aggregated comparisons, and new analyses, and the underlying data is externally simulated rather than derived from the cited work's fitted values. The fixed-grid sweeps and random 90/10 split do limit extrapolation claims for off-grid specifications, and the non-unique inverse mapping is acknowledged, but these are generalization or validity concerns, not circular reasoning. No equation defines the target in terms of the fitted quantity, no fitted parameter is renamed as a prediction, and no uniqueness theorem or ansatz is imported from the authors' prior work to force the conclusions.

Assumptions & free parameters 6 free parameters · 4 assumptions · 0 invented entities

The paper's empirical claims rest on the accuracy of Cadence 45nm simulations as ground truth, the completeness of the parameter sweep grids, and smoothness of the performance-to-parameter mapping. These are domain assumptions, not derived results. Model hyperparameters are chosen by hand and are not fitted to the reported error benchmarks.

free parameters (6)
  • Adam learning rate = 0.001
    Fixed for all neural network training, chosen by hand; not tuned per circuit.
  • Transformer hyperparameters = dim_model=200, num_heads=2, dropout=0.1, num_encoder_layers=6
    Chosen by hand, listed in Table IV; not optimized per dataset.
  • MLP architecture = 7 layers, dims [200,300,500,500,300,200]
    Chosen by hand; no architecture search reported.
  • kNN neighbors = 5
    Default choice; no tuning reported.
  • Random forest n_estimators = 100
    Default choice.
  • SVR configuration = rbf kernel, epsilon not explicitly stated
    Standard configuration; multi-output via MultiOutputRegression.
assumptions (4)
  • domain assumption Cadence Virtuoso simulation with 45nm CMOS models provides accurate ground-truth performance values for the generated dataset.
    All labels come from Cadence simulations (Section III-C); if the simulator or process models are inaccurate, reported errors are miscalibrated.
  • domain assumption The parameter sweep ranges [beg:inc:end] in Tables I and II cover the practically useful design space for each circuit.
    The benchmark evaluates only within these sampled ranges; performance specifications outside them are not tested.
  • domain assumption Performance metrics are deterministic and sufficiently smooth functions of the design parameters, so a regression mapping from specs to parameters is learnable.
    The paper notes multiple parameter sets can map to the same specs (Section II) but assumes a single solution is usable; nonlinearities are expected but learnable.
  • standard math The random 90/10 split produces i.i.d. test points representative of the target design task.
    Standard supervised learning assumption from Equation (2); no stratification or temporal split is used.

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Cite this review

Pith. "Pith review of Supervised Learning for Analog and RF Circuit Design: Benchmarks and Comparative Insights." pith.science (2026). https://pith.science/paper/WPVRSYJJ

@misc{pith2026250111839,
  author       = {Pith},
  title        = {Pith review of: Supervised Learning for Analog and RF Circuit Design: Benchmarks and Comparative Insights},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/WPVRSYJJ}},
  note         = {Machine review of arXiv:2501.11839}
}
read the original abstract

Automating analog and radio-frequency (RF) circuit design using machine learning (ML) significantly reduces the time and effort required for parameter optimization. This study explores supervised ML-based approaches for designing circuit parameters from performance specifications across various circuit types, including homogeneous and heterogeneous designs. By evaluating diverse ML models, from neural networks like transformers to traditional methods like random forests, we identify the best-performing models for each circuit. Our results show that simpler circuits, such as low-noise amplifiers, achieve exceptional accuracy with mean relative errors as low as 0.3% due to their linear parameter-performance relationships. In contrast, complex circuits, like power amplifiers and voltage-controlled oscillators, present challenges due to their non-linear interactions and larger design spaces. For heterogeneous circuits, our approach achieves an 88% reduction in errors with increased training data, with the receiver achieving a mean relative error as low as 0.23%, showcasing the scalability and accuracy of the proposed methodology. Additionally, we provide insights into model strengths, with transformers excelling in capturing non-linear mappings and k-nearest neighbors performing robustly in moderately linear parameter spaces, especially in heterogeneous circuits with larger datasets. This work establishes a foundation for extending ML-driven design automation, enabling more efficient and scalable circuit design workflows.

Figures

Figures reproduced from arXiv: 2501.11839 by the authors.

Figure 1
Figure 1. Schematics of homogeneous circuits: (a) Common-Source Voltage Amplifier (CSVA), (b) Cascode Voltage Amplifier (CVA), (c) Two-Stage Voltage [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. Schematics of the heterogeneous transceiver system: (a) Transmitter, (b) Receiver. These circuits represent key components of the transceiver chain, [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figure 3
Figure 3. Heterogeneous architecture of a 28 GHz wireless transceiver [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figures from the paper (11 more)
Figure 4
Figure 4. Figure 4: Procedure for creating dataset including homogeneous and heterogeneous circuits. This pipeline illustrates parameter selection, range sweeping, [PITH_FULL_IMAGE:figures/full_fig_p006_4.png]
Figure 5
Figure 5. Figure 5: Pipeline of the proposed design methodology including three stages: [PITH_FULL_IMAGE:figures/full_fig_p006_5.png]
Figure 7
Figure 7. Figure 7: Relative error histogram of individual performance metrics and [PITH_FULL_IMAGE:figures/full_fig_p009_7.png]
Figure 6
Figure 6. Figure 6: Relative error histogram of individual performance metrics and [PITH_FULL_IMAGE:figures/full_fig_p009_6.png]
Figure 8
Figure 8. Figure 8: Relative error histogram of individual performance metrics and [PITH_FULL_IMAGE:figures/full_fig_p009_8.png]
Figure 10
Figure 10. Figure 10: Relative error histogram of individual performance metrics and [PITH_FULL_IMAGE:figures/full_fig_p010_10.png]
Figure 9
Figure 9. Figure 9: Relative error histogram of individual performance metrics and [PITH_FULL_IMAGE:figures/full_fig_p010_9.png]
Figure 11
Figure 11. Figure 11: Relative error histogram of individual performance metrics and [PITH_FULL_IMAGE:figures/full_fig_p011_11.png]
Figure 13
Figure 13. Figure 13: Relative error histogram of individual performance metrics and mean relative error histogram for Transmitter. The plots illustrate the relative error [PITH_FULL_IMAGE:figures/full_fig_p012_13.png]
Figure 14
Figure 14. Figure 14: Relative error histogram of individual performance metrics and mean relative error histogram for Receiver. The plots depict the relative error [PITH_FULL_IMAGE:figures/full_fig_p012_14.png]
Figure 15
Figure 15. Figure 15: Mean relative error histograms for (a) Transmitter using the MLP [PITH_FULL_IMAGE:figures/full_fig_p013_15.png]

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