Two-dimensional Si spin qubit arrays with multilevel interconnects

Aaron Smith; Bryan J. Thomas; Christi A. Peterson; Christina A. C. Garcia; Clifford E. Plesha; David J. Fialkow; Dominic Daprano; Edwin Acuna; Ian T. Counts; Isaac Khalaf

arxiv: 2502.08861 · v1 · submitted 2025-02-13 · 🪐 quant-ph · cond-mat.mes-hall

Two-dimensional Si spin qubit arrays with multilevel interconnects

Sieu D. Ha , Edwin Acuna , Kate Raach , Zachery T. Bloom , Teresa L. Brecht , James M. Chappell , Maxwell D. Choi , Justin E. Christensen

show 21 more authors

Ian T. Counts Dominic Daprano J.P. Dodson Kevin Eng David J. Fialkow Christina A. C. Garcia Wonill Ha Thomas R. B. Harris nathan holman Isaac Khalaf Justine W. Matten Christi A. Peterson Clifford E. Plesha Matthew J. Ruiz Aaron Smith Bryan J. Thomas Samuel J. Whiteley Thaddeus D. Ladd Michael P. Jura Matthew T. Rakher Matthew G. Borselli

This is my paper

Pith reviewed 2026-05-23 03:47 UTC · model grok-4.3

classification 🪐 quant-ph cond-mat.mes-hall

keywords silicon spin qubitsexchange-only qubitsmultilevel interconnectstwo-dimensional arraysrandomized benchmarkingquantum gates

0 comments

The pith

A three-layer interconnect process builds two-dimensional silicon spin qubit arrays while preserving gate fidelities above 99.9 percent.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper shows that standard semiconductor back-end-of-line interconnect fabrication can be used to create a two-dimensional array of silicon spins in which every nearest-neighbor pair remains fully controllable by exchange. In the demonstrated device the authors encode exchange-only qubits and obtain single-qubit gate fidelities that match those previously measured on single-layer devices, including values above 99.9 percent by blind randomized benchmarking. The same 2D connectivity also permits both linear and right-angle qubit layouts, so that defective sites can be avoided by reconfiguring the array. A reader would care because the result indicates that the wiring bottleneck that has limited spin-qubit demonstrations to one dimension can be removed without sacrificing coherence or control precision.

Core claim

In a device using three interconnect layers, exchange-only qubits are encoded and achieve average single-qubit gate fidelities consistent with single-layer devices, including fidelities greater than 99.9 percent as measured by blind randomized benchmarking; the two-dimensional spin connectivity further enables both linear and right-angle exchange-only qubits with high performance.

What carries the argument

The three-layer back-end-of-line interconnect stack that supplies independent control lines to every nearest-neighbor pair while preserving exchange tunability across the plane.

If this is right

Both linear and right-angle exchange-only qubits can be formed and operated at high fidelity in the same array.
Defective qubits can be bypassed by switching between linear and right-angle encodings.
The same interconnect architecture can be extended to larger arrays without redesign of the qubit layer itself.
Standard industrial semiconductor processes become directly applicable to spin-qubit scaling.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The approach may allow classical control electronics to be integrated on additional metal layers above the qubit plane.
Similar multilayer wiring could be tested on other spin-qubit variants or on superconducting circuits that also require dense nearest-neighbor coupling.
If the noise floor remains unchanged with added layers, the platform could support error-corrected logical qubits whose physical density exceeds current one-dimensional limits.

Load-bearing premise

Adding the extra interconnect layers does not introduce new charge noise, strain, or defects that would lower spin coherence or exchange control beyond the levels already present in single-layer devices.

What would settle it

A direct comparison showing that average single-qubit gate fidelity in the three-layer device falls measurably below the fidelity obtained on an otherwise identical single-layer device would falsify the consistency claim.

Figures

Figures reproduced from arXiv: 2502.08861 by Aaron Smith, Bryan J. Thomas, Christi A. Peterson, Christina A. C. Garcia, Clifford E. Plesha, David J. Fialkow, Dominic Daprano, Edwin Acuna, Ian T. Counts, Isaac Khalaf, James M. Chappell, J.P. Dodson, Justin E. Christensen, Justine W. Matten, Kate Raach, Kevin Eng, Matthew G. Borselli, Matthew J. Ruiz, Matthew T. Rakher, Maxwell D. Choi, Michael P. Jura, nathan holman, Samuel J. Whiteley, Sieu D. Ha, Teresa L. Brecht, Thaddeus D. Ladd, Thomas R. B. Harris, Wonill Ha, Zachery T. Bloom.

**Figure 2.** Figure 2: FIG. 2. (a) A hypothetical 2D array of spins showing avail [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗

**Figure 3.** Figure 3: FIG. 3. Exchange “fingerprint” plots for each of the seven [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

**Figure 4.** Figure 4: FIG. 4. (a) Exchange-only qubit characterization in a 2 [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗

read the original abstract

The promise of quantum computation is contingent upon physical qubits with both low gate error rate and broad scalability. Silicon-based spins are a leading qubit platform, but demonstrations to date have not utilized fabrication processes capable of extending arrays in two dimensions while maintaining complete control of individual spins. Here, we implement an interconnect process, common in semiconductor manufacturing, with multiple back-end-of-line layers to show an extendable two-dimensional array of spins with fully controllable nearest-neighbor exchange interactions. In a device using three interconnect layers, we encode exchange-only qubits and achieve average single-qubit gate fidelities consistent with single-layer devices, including fidelities greater than 99.9%, as measured by blind randomized benchmarking. Moreover, with spin connectivity in two dimensions, we show that both linear and right-angle exchange-only qubits with high performance can be formed, enabling qubit array reconfigurability in the presence of defects. This extendable device platform demonstrates that industrial manufacturing techniques can be leveraged for scalable spin qubit technologies.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

The paper shows a 2D exchange-only silicon spin qubit array fabricated with three interconnect layers, reporting fidelities over 99.9% consistent with single-layer devices.

read the letter

The main point is that this work has built a two-dimensional grid of silicon spin qubits using standard multilevel interconnect technology, and they report single-qubit gate fidelities above 99.9 percent that match what they see in simpler single-layer setups. What stands out as new is the application of back-end-of-line processing with three layers to enable full 2D nearest-neighbor exchange control. This lets them make both linear and right-angle exchange-only qubits, which could allow arrays to route around defects. Using processes already common in chip manufacturing is a plus for eventual scale-up. The paper does a reasonable job of highlighting the reconfigurability benefit and the use of blind randomized benchmarking for the fidelity measurements. Where it is softer is on the quantitative support for the performance claim. The abstract says the fidelities are consistent with single-layer devices but gives no specific numbers, distributions, or direct comparisons like noise spectra or coherence times. The key assumption that the extra interconnect layers do not add charge noise or defects is stated but not backed by data in the summary. That makes the central experimental result harder to evaluate without the full figures and methods. This is the kind of paper for hardware teams working on silicon qubits and scaling strategies. Someone interested in fabrication integration would get the most out of it. It is worth sending to peer review because it is a real device demonstration addressing the wiring issue in 2D arrays, though the reviewers will likely want more detailed performance data.

Referee Report

1 major / 1 minor

Summary. The manuscript reports the implementation of a three-layer back-end-of-line interconnect process for creating two-dimensional arrays of silicon spin qubits with fully controllable nearest-neighbor exchange. Exchange-only qubits are encoded, achieving average single-qubit gate fidelities consistent with single-layer devices and exceeding 99.9% as measured by blind randomized benchmarking. The platform also enables both linear and right-angle qubit configurations for array reconfigurability around defects.

Significance. This work is significant for demonstrating that standard semiconductor manufacturing interconnects can be integrated into spin qubit devices without apparent degradation of performance, addressing a major hurdle in scaling silicon spin qubits to two dimensions. The blind benchmarking and reconfigurability demonstrations are notable strengths if the consistency claim is substantiated.

major comments (1)

[Abstract and Results] The assertion that fidelities are consistent with single-layer devices (Abstract) lacks supporting quantitative data such as direct comparisons of fidelity distributions, T2* coherence times, or exchange coupling histograms between the multilevel interconnect device and single-layer controls; this is load-bearing for the claim that the interconnect process introduces no additional noise or defects.

minor comments (1)

[Abstract] The abstract could more precisely specify the number of qubits or devices tested to support the yield and consistency claims.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for their thorough review and valuable comments. We address the single major comment below.

read point-by-point responses

Referee: [Abstract and Results] The assertion that fidelities are consistent with single-layer devices (Abstract) lacks supporting quantitative data such as direct comparisons of fidelity distributions, T2* coherence times, or exchange coupling histograms between the multilevel interconnect device and single-layer controls; this is load-bearing for the claim that the interconnect process introduces no additional noise or defects.

Authors: We agree that direct quantitative comparisons are needed to fully substantiate the consistency claim. In the revised manuscript we will add a new supplementary figure (or main-text panel) that directly compares the multilevel-interconnect device against single-layer control devices fabricated in the same process flow. The comparison will include (i) histograms of single-qubit gate fidelities obtained from blind randomized benchmarking, (ii) T2* coherence-time distributions, and (iii) exchange-coupling histograms measured on nearest-neighbor pairs. These data will be accompanied by a brief statistical test (e.g., Kolmogorov-Smirnov) to quantify consistency. We believe this addition will address the referee’s concern without altering the central conclusions of the work. revision: yes

Circularity Check

0 steps flagged

No circularity: experimental device demonstration with direct measurements

full rationale

This is an experimental fabrication and characterization paper reporting measured single-qubit gate fidelities via blind randomized benchmarking in a multilevel-interconnect Si spin qubit array. No equations, derivations, or fitted parameters are presented that reduce the reported fidelities (>99.9% or consistency with single-layer devices) to inputs defined by the same data. The central claim rests on empirical RB results rather than any self-definitional, fitted-prediction, or self-citation chain. The assumption that the interconnect stack adds no extra noise is an empirical premise tested by the measurements themselves, not a circular reduction. No load-bearing steps match the enumerated circularity patterns.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

No mathematical derivations or free parameters are present; the work is an experimental device report. No invented entities are introduced.

pith-pipeline@v0.9.0 · 5843 in / 1121 out tokens · 25617 ms · 2026-05-23T03:47:03.070394+00:00 · methodology

discussion (0)

Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

IndisputableMonolith/Foundation/RealityFromDistinction.lean reality_from_one_distinction unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

In a device using three interconnect layers, we encode exchange-only qubits and achieve average single-qubit gate fidelities consistent with single-layer devices, including fidelities greater than 99.9%, as measured by blind randomized benchmarking.
IndisputableMonolith/Cost/FunctionalEquation.lean washburn_uniqueness_aczel unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

Exchange-only qubits are instantiated using a triple-quantum-dot (TQD) decoherence-free subsystem (DFS) encoding

What do these tags mean?

matches: The paper's claim is directly supported by a theorem in the formal canon.
supports: The theorem supports part of the paper's argument, but the paper may add assumptions or extra steps.
extends: The paper goes beyond the formal theorem; the theorem is a base layer rather than the whole result.
uses: The paper appears to rely on the theorem as machinery.
contradicts: The paper's claim conflicts with a theorem or certificate in the canon.
unclear: Pith found a possible connection, but the passage is too broad, indirect, or ambiguous to say the theorem truly supports the claim.

Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

CAbLECAR: efficiently scheduling QLDPC codes on a tileable spin qubit chip with shuttling
quant-ph 2026-04 unverdicted novelty 6.0

CAbLECAR provides a robotics-inspired shuttle scheduler that enables QLDPC codes on tileable spin-qubit hardware, yielding up to 86% faster schedules and orders-of-magnitude gains in encoding efficiency and logical er...

Reference graph

Works this paper leans on

23 extracted references · 23 canonical work pages · cited by 1 Pith paper · 1 internal anchor

[1]

Burkard, T

G. Burkard, T. D. Ladd, J. M. Nichol, A. Pan, and J. R. Petta, Semiconductor spin qubits, Rev. Mod. Phys. 95, 025003 (2023)

work page 2023
[2]

N. D. Stuyck, A. Saraiva, W. Gilbert, J. C. Pardo, R. Li, C. C. Escott, K. D. Greve, S. Voinigescu, D. J. Reilly, and A. S. Dzurak, CMOS compatibility of semiconductor spin qubits (2024), arXiv:2409.03993 [cond-mat.mes-hall]

work page internal anchor Pith review Pith/arXiv arXiv 2024
[3]

Bertrand, B

B. Bertrand, B. Martinez, J. Li, B. C. Paz, V. Mil- lory, V. Labracherie, L. Br´ evard, H. Sahin, G. Rous- sely, A. Sarrazin, T. Meunier, M. Vinet, Y.-M. Niquet, B. Brun, R. Maurand, S. De Franceschi, and H. Niebo- jewski, Tunnel and capacitive coupling optimization in FDSOI spin-qubit devices, in 2023 International Electron Devices Meeting (IEDM) (2023) pp. 1–4

work page 2023
[4]

A. M. J. Zwerver, T. Kr¨ ahenmann, T. F. Watson, L. Lampert, H. C. George, R. Pillarisetty, S. A. Bojarski, P. Amin, S. V. Amitonov, J. M. Boter, R. Caudillo, D. Correas-Serrano, J. P. Dehollain, G. Droulers, E. M. Henry, R. Kotlyar, M. Lodari, F. L¨ uthi, D. J. Michalak, B. K. Mueller, S. Neyens, J. Roberts, N. Samkharadze, G. Zheng, O. K. Zietz, G. Scap...

work page 2022
[5]

Elsayed, M

A. Elsayed, M. M. K. Shehata, C. Godfrin, S. Kubicek, S. Massar, Y. Canvel, J. Jussot, G. Simion, M. Mongillo, D. Wan, B. Govoreanu, I. P. Radu, R. Li, P. Van Dorpe, and K. De Greve, Low charge noise quantum dots with industrial CMOS manufacturing, npj Quantum Informa- tion 10, 70 (2024)

work page 2024
[6]

S. G. J. Philips, M. T. Madzik, S. V. Amitonov, S. L. de Snnoo, M. Russ, N. Kalhor, C. Volk, D. Lawrie, William I. L. anf Brousse, L. Tryputen, B. P. Wuetz, A. Sammak, M. Veldhorst, G. Scappucci, and L. M. K. Vandersypen, Universal control of a six-qubit quantum processor in silicon, Nature 609, 919 (2022)

work page 2022
[7]

Borsoi, N

F. Borsoi, N. W. Hendrickx, V. John, S. Motz, F. van Riggelen, A. Sammak, S. L. de Snoo, G. Scappucci, and M. Veldhorst, Shared control of a 16 semiconductor quan- tum dot crossbar array, Nat. Nanotechnol. 19, 21 (2024)

work page 2024
[8]

W. Ha, S. D. Ha, M. D. Choi, Y. Tang, A. E. Schmitz, M. P. Levendorf, K. Lee, J. M. Chappell, T. S. Adams, D. R. Hulbert, E. Acuna, R. S. Noah, J. W. Matten, M. P. Jura, J. A. Wright, M. T. Rakher, and M. G. Borselli, A Flexible Design Platform for Si/SiGe Exchange-Only Qubits with Low Disorder, Nano Lett. 22, 1443 (2022)

work page 2022
[9]

A. J. Weinstein, M. D. Reed, A. M. Jones, R. W. An- drews, D. Barnes, J. Z. Blumoff, L. E. Euliss, K. Eng, B. Fong, S. D. Ha, R. R. Hulbert, C. Jackson, M. Jura, T. E. Keating, J. Kerckhoff, A. A. Kiselev, J. Matten, G. Sabbir, A. Smith, J. Wright, M. T. Rakher, T. D. Ladd, and M. G. Borselli, Universal logic with encoded spin qubits in silicon, Nature 61...

work page 2023
[10]

Acuna, J

E. Acuna, J. D. Broz, K. Shyamsundar, A. B. Mei, C. P. Feeney, V. Smetanka, T. Davis, K. Lee, M. D. Choi, B. Boyd, J. Suh, W. Ha, C. Jennings, A. S. Pan, D. S. Sanchez, M. D. Reed, and J. R. Petta, Coherent con- trol of a triangular exchange-only spin qubit, Phys. Rev. Appl. 22, 044057 (2024)

work page 2024
[11]

J. Z. Blumoff, A. S. Pan, T. E. Keating, R. W. Andrews, D. W. Barnes, T. L. Brecht, E. T. Croke, L. E. Euliss, J. A. Fast, C. A. Jackson, A. M. Jones, J. Kerckhoff, R. K. Lanza, K. Raach, B. J. Thomas, R. Velunta, A. J. Weinstein, T. D. Ladd, K. Eng, M. G. Borselli, A. T. Hunter, and M. T. Rakher, Fast and high-fidelity state preparation and measurement i...

work page 2022
[12]

D. P. DiVincenzo, D. Bacon, J. Kempe, G. Burkard, and 6 K. B. Whaley, Universal quantum computation with the exchange interaction, Nature 408, 339 (2000)

work page 2000
[13]

R. W. Andrews, C. Jones, M. D. Reed, A. M. Jones, S. D. Ha, M. P. Jura, J. Kerckhoff, M. Levendorf, S. Meenehan, S. T. Merkel, A. Smith, B. Sun, A. J. Weinstein, M. T. Rakher, T. D. Ladd, and M. G. Borselli, Quantifying error and leakage in an encoded Si/SiGe triple-dot qubit, Nat. Nanotechnol. 14, 747 (2019)

work page 2019
[14]

A. M. Jones, E. J. Pritchett, E. H. Chen, T. E. Keating, R. W. Andrews, J. Z. Blumoff, L. A. De Lorenzo, K. Eng, S. D. Ha, A. A. Kiselev, S. M. Meenehan, S. T. Merkel, J. A. Wright, L. F. Edge, R. S. Ross, M. T. Rakher, M. G. Borselli, and A. T. Hunter, Spin-blockade spectroscopy of Si/Si-Ge quantum dots, Phys. Rev. Appl. 12, 014026 (2019)

work page 2019
[15]

Y. P. Kandel, H. Qiao, S. Fallahi, G. C. Gardner, M. J. Manfra, and J. M. Nichol, Coherent spin-state transfer via Heisenberg exchange, Nature 573, 553 (2019)

work page 2019
[16]

M. D. Reed, B. M. Maune, R. W. Andrews, M. G. Borselli, K. Eng, M. P. Jura, A. A. Kiselev, T. D. Ladd, S. T. Merkel, I. Milosavljevic, E. J. Pritchett, M. T. Rakher, R. S. Ross, A. E. Schmitz, A. Smith, J. A. Wright, M. F. Gyure, and A. T. Hunter, Reduced sensitivity to charge noise in semiconductor spin qubits via symmetric operation, Phys. Rev. Lett. 11...

work page 2016
[17]

Martins, F

F. Martins, F. K. Malinowski, P. D. Nissen, E. Barnes, S. Fallahi, G. C. Gardner, M. J. Manfra, C. M. Mar- cus, and F. Kuemmeth, Noise suppression using symmet- ric exchange gates in spin qubits, Phys. Rev. Lett. 116, 116801 (2016)

work page 2016
[18]

Pirati, R

A. Pirati, R. Peeters, D. Smith, S. Lok, M. van Noorden- burg, R. van Es, E. Verhoeven, H. Meijer, A. Minnaert, J.-W. van der Horst, H. Meiling, J. Mallmann, C. Wag- ner, J. Stoeldraijer, G. Fisser, J. Finders, C. Zoldesi, U. Stamm, H. Boom, D. Brandt, D. Brown, I. Fomenkov, and M. Purvis, EUV lithography performance for man- ufacturing: status and outloo...

work page 2016
[19]

D. M. Zajac, T. M. Hazard, X. Mi, E. Nielsen, and J. R. Petta, Scalable gate architecture for a one-dimensional array of semiconductor spin qubits, Phys. Rev. Appl. 6, 054013 (2016)

work page 2016
[20]

J. I. Colless, A. C. Mahoney, J. M. Hornibrook, A. C. Doherty, H. Lu, A. C. Gossard, and D. J. Reilly, Disper- sive readout of a few-electron double quantum dot with fast rf gate sensors, Phys. Rev. Lett. 110, 046805 (2013)

work page 2013
[21]

A. West, B. Hensen, A. Jouan, T. Tanttu, C.-H. Yang, A. Rossi, M. F. Gonzalez-Zalba, F. Hudson, A. Morello, D. J. Reilly, and A. S. Dzurak, Gate-based single-shot readout of spins in silicon, Nature Nanotechnology 14, 437 (2019)

work page 2019
[22]

B. Sun, T. Brecht, B. H. Fong, M. Akmal, J. Z. Blumoff, T. A. Cain, F. W. Carter, D. H. Finestone, M. N. Fire- man, W. Ha, A. T. Hatke, R. M. Hickey, C. A. C. Jack- son, I. Jenkins, A. M. Jones, A. Pan, D. R. Ward, A. J. Weinstein, S. J. Whiteley, P. Williams, M. G. Borselli, M. T. Rakher, and T. D. Ladd, Full-Permutation Dy- namical Decoupling in Triple-...

work page 2024
[23]

Setiawan, H.-Y

F. Setiawan, H.-Y. Hui, J. P. Kestner, X. Wang, and S. D. Sarma, Robust two-qubit gates for exchange-coupled qubits, Phys. Rev. B 89, 085314 (2014)

work page 2014

[1] [1]

Burkard, T

G. Burkard, T. D. Ladd, J. M. Nichol, A. Pan, and J. R. Petta, Semiconductor spin qubits, Rev. Mod. Phys. 95, 025003 (2023)

work page 2023

[2] [2]

N. D. Stuyck, A. Saraiva, W. Gilbert, J. C. Pardo, R. Li, C. C. Escott, K. D. Greve, S. Voinigescu, D. J. Reilly, and A. S. Dzurak, CMOS compatibility of semiconductor spin qubits (2024), arXiv:2409.03993 [cond-mat.mes-hall]

work page internal anchor Pith review Pith/arXiv arXiv 2024

[3] [3]

Bertrand, B

B. Bertrand, B. Martinez, J. Li, B. C. Paz, V. Mil- lory, V. Labracherie, L. Br´ evard, H. Sahin, G. Rous- sely, A. Sarrazin, T. Meunier, M. Vinet, Y.-M. Niquet, B. Brun, R. Maurand, S. De Franceschi, and H. Niebo- jewski, Tunnel and capacitive coupling optimization in FDSOI spin-qubit devices, in 2023 International Electron Devices Meeting (IEDM) (2023) pp. 1–4

work page 2023

[4] [4]

A. M. J. Zwerver, T. Kr¨ ahenmann, T. F. Watson, L. Lampert, H. C. George, R. Pillarisetty, S. A. Bojarski, P. Amin, S. V. Amitonov, J. M. Boter, R. Caudillo, D. Correas-Serrano, J. P. Dehollain, G. Droulers, E. M. Henry, R. Kotlyar, M. Lodari, F. L¨ uthi, D. J. Michalak, B. K. Mueller, S. Neyens, J. Roberts, N. Samkharadze, G. Zheng, O. K. Zietz, G. Scap...

work page 2022

[5] [5]

Elsayed, M

A. Elsayed, M. M. K. Shehata, C. Godfrin, S. Kubicek, S. Massar, Y. Canvel, J. Jussot, G. Simion, M. Mongillo, D. Wan, B. Govoreanu, I. P. Radu, R. Li, P. Van Dorpe, and K. De Greve, Low charge noise quantum dots with industrial CMOS manufacturing, npj Quantum Informa- tion 10, 70 (2024)

work page 2024

[6] [6]

S. G. J. Philips, M. T. Madzik, S. V. Amitonov, S. L. de Snnoo, M. Russ, N. Kalhor, C. Volk, D. Lawrie, William I. L. anf Brousse, L. Tryputen, B. P. Wuetz, A. Sammak, M. Veldhorst, G. Scappucci, and L. M. K. Vandersypen, Universal control of a six-qubit quantum processor in silicon, Nature 609, 919 (2022)

work page 2022

[7] [7]

Borsoi, N

F. Borsoi, N. W. Hendrickx, V. John, S. Motz, F. van Riggelen, A. Sammak, S. L. de Snoo, G. Scappucci, and M. Veldhorst, Shared control of a 16 semiconductor quan- tum dot crossbar array, Nat. Nanotechnol. 19, 21 (2024)

work page 2024

[8] [8]

W. Ha, S. D. Ha, M. D. Choi, Y. Tang, A. E. Schmitz, M. P. Levendorf, K. Lee, J. M. Chappell, T. S. Adams, D. R. Hulbert, E. Acuna, R. S. Noah, J. W. Matten, M. P. Jura, J. A. Wright, M. T. Rakher, and M. G. Borselli, A Flexible Design Platform for Si/SiGe Exchange-Only Qubits with Low Disorder, Nano Lett. 22, 1443 (2022)

work page 2022

[9] [9]

A. J. Weinstein, M. D. Reed, A. M. Jones, R. W. An- drews, D. Barnes, J. Z. Blumoff, L. E. Euliss, K. Eng, B. Fong, S. D. Ha, R. R. Hulbert, C. Jackson, M. Jura, T. E. Keating, J. Kerckhoff, A. A. Kiselev, J. Matten, G. Sabbir, A. Smith, J. Wright, M. T. Rakher, T. D. Ladd, and M. G. Borselli, Universal logic with encoded spin qubits in silicon, Nature 61...

work page 2023

[10] [10]

Acuna, J

E. Acuna, J. D. Broz, K. Shyamsundar, A. B. Mei, C. P. Feeney, V. Smetanka, T. Davis, K. Lee, M. D. Choi, B. Boyd, J. Suh, W. Ha, C. Jennings, A. S. Pan, D. S. Sanchez, M. D. Reed, and J. R. Petta, Coherent con- trol of a triangular exchange-only spin qubit, Phys. Rev. Appl. 22, 044057 (2024)

work page 2024

[11] [11]

J. Z. Blumoff, A. S. Pan, T. E. Keating, R. W. Andrews, D. W. Barnes, T. L. Brecht, E. T. Croke, L. E. Euliss, J. A. Fast, C. A. Jackson, A. M. Jones, J. Kerckhoff, R. K. Lanza, K. Raach, B. J. Thomas, R. Velunta, A. J. Weinstein, T. D. Ladd, K. Eng, M. G. Borselli, A. T. Hunter, and M. T. Rakher, Fast and high-fidelity state preparation and measurement i...

work page 2022

[12] [12]

D. P. DiVincenzo, D. Bacon, J. Kempe, G. Burkard, and 6 K. B. Whaley, Universal quantum computation with the exchange interaction, Nature 408, 339 (2000)

work page 2000

[13] [13]

R. W. Andrews, C. Jones, M. D. Reed, A. M. Jones, S. D. Ha, M. P. Jura, J. Kerckhoff, M. Levendorf, S. Meenehan, S. T. Merkel, A. Smith, B. Sun, A. J. Weinstein, M. T. Rakher, T. D. Ladd, and M. G. Borselli, Quantifying error and leakage in an encoded Si/SiGe triple-dot qubit, Nat. Nanotechnol. 14, 747 (2019)

work page 2019

[14] [14]

A. M. Jones, E. J. Pritchett, E. H. Chen, T. E. Keating, R. W. Andrews, J. Z. Blumoff, L. A. De Lorenzo, K. Eng, S. D. Ha, A. A. Kiselev, S. M. Meenehan, S. T. Merkel, J. A. Wright, L. F. Edge, R. S. Ross, M. T. Rakher, M. G. Borselli, and A. T. Hunter, Spin-blockade spectroscopy of Si/Si-Ge quantum dots, Phys. Rev. Appl. 12, 014026 (2019)

work page 2019

[15] [15]

Y. P. Kandel, H. Qiao, S. Fallahi, G. C. Gardner, M. J. Manfra, and J. M. Nichol, Coherent spin-state transfer via Heisenberg exchange, Nature 573, 553 (2019)

work page 2019

[16] [16]

M. D. Reed, B. M. Maune, R. W. Andrews, M. G. Borselli, K. Eng, M. P. Jura, A. A. Kiselev, T. D. Ladd, S. T. Merkel, I. Milosavljevic, E. J. Pritchett, M. T. Rakher, R. S. Ross, A. E. Schmitz, A. Smith, J. A. Wright, M. F. Gyure, and A. T. Hunter, Reduced sensitivity to charge noise in semiconductor spin qubits via symmetric operation, Phys. Rev. Lett. 11...

work page 2016

[17] [17]

Martins, F

F. Martins, F. K. Malinowski, P. D. Nissen, E. Barnes, S. Fallahi, G. C. Gardner, M. J. Manfra, C. M. Mar- cus, and F. Kuemmeth, Noise suppression using symmet- ric exchange gates in spin qubits, Phys. Rev. Lett. 116, 116801 (2016)

work page 2016

[18] [18]

Pirati, R

A. Pirati, R. Peeters, D. Smith, S. Lok, M. van Noorden- burg, R. van Es, E. Verhoeven, H. Meijer, A. Minnaert, J.-W. van der Horst, H. Meiling, J. Mallmann, C. Wag- ner, J. Stoeldraijer, G. Fisser, J. Finders, C. Zoldesi, U. Stamm, H. Boom, D. Brandt, D. Brown, I. Fomenkov, and M. Purvis, EUV lithography performance for man- ufacturing: status and outloo...

work page 2016

[19] [19]

D. M. Zajac, T. M. Hazard, X. Mi, E. Nielsen, and J. R. Petta, Scalable gate architecture for a one-dimensional array of semiconductor spin qubits, Phys. Rev. Appl. 6, 054013 (2016)

work page 2016

[20] [20]

J. I. Colless, A. C. Mahoney, J. M. Hornibrook, A. C. Doherty, H. Lu, A. C. Gossard, and D. J. Reilly, Disper- sive readout of a few-electron double quantum dot with fast rf gate sensors, Phys. Rev. Lett. 110, 046805 (2013)

work page 2013

[21] [21]

A. West, B. Hensen, A. Jouan, T. Tanttu, C.-H. Yang, A. Rossi, M. F. Gonzalez-Zalba, F. Hudson, A. Morello, D. J. Reilly, and A. S. Dzurak, Gate-based single-shot readout of spins in silicon, Nature Nanotechnology 14, 437 (2019)

work page 2019

[22] [22]

B. Sun, T. Brecht, B. H. Fong, M. Akmal, J. Z. Blumoff, T. A. Cain, F. W. Carter, D. H. Finestone, M. N. Fire- man, W. Ha, A. T. Hatke, R. M. Hickey, C. A. C. Jack- son, I. Jenkins, A. M. Jones, A. Pan, D. R. Ward, A. J. Weinstein, S. J. Whiteley, P. Williams, M. G. Borselli, M. T. Rakher, and T. D. Ladd, Full-Permutation Dy- namical Decoupling in Triple-...

work page 2024

[23] [23]

Setiawan, H.-Y

F. Setiawan, H.-Y. Hui, J. P. Kestner, X. Wang, and S. D. Sarma, Robust two-qubit gates for exchange-coupled qubits, Phys. Rev. B 89, 085314 (2014)

work page 2014