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REVIEW 4 major objections 5 minor 41 references

Neuromorphic Principles for Efficient Large Language Models on Intel Loihi 2

T0 review · 4 major / 5 minor · reviewed 2026-08-08 · deepseek-v4-flash

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Pith's one-line read This paper reports that a 370M-parameter MatMul-free LLM, mapped onto Intel's Loihi 2 neuromorphic processor, generates tokens at 41.5 per second using 405 mJ per token, roughly three times the throughput and half the energy of similarly…

desk verdict A useful engineering paper with a solid quantization study, but the headline 'fully on-chip' efficiency claim is not yet supported by measurements. read the letter →

arxiv 2503.18002 v2 pith:XURSXUWB submitted 2025-02-12 cs.NE cs.AIcs.ARcs.LG

Steven Abreu , Sumit Bam Shrestha , Rui-Jie Zhu , Jason Eshraghian This is my paper · ORCID
classification cs.NEcs.AIcs.ARcs.LG
keywords Loihi2neuromorphiccomputingMatMul-freelanguagemodelsternaryweightsquantizationstatespaceedgeinferenceenergyefficiency
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims that a modern LLM architecture can be made to run efficiently on Intel's Loihi 2 neuromorphic processor if all matrix multiplications are replaced by additions, bit shifts, and elementwise operations. The target is the 370M-parameter MatMul-free language model, quantized to 8-bit weights and 16-bit activations with no measured accuracy loss on six zero-shot tasks. Measured on a 24-chip Loihi 2 system, the 24 transformer blocks generate at 41.5 tokens per second using 405 mJ per token and prefill at 6632 tokens per second using 3.7 mJ per token, with throughput constant across sequence length. Against transformer LLMs on an NVIDIA Jetson Orin Nano, that is almost 3$\times$ higher generation throughput with about 2$\times$ less energy per token, and at least 2$\times$ higher prefill throughput with about 2$\times$ less energy. The authors note that the embedding and un-embedding layers are not yet implemented on-chip; the reported numbers assume those layers add little latency and modest power.

What carries the argument

The load-bearing machinery is the MatMul-free LLM itself: a Metaformer-style stack of BitLinear layers (ternary weight matrices with power-of-two scaling) and an MLGRU recurrent token mixer based on HGRN-style gated linear recurrences. Because every matrix product is replaced by signed accumulation and bit shifts, the entire model reduces to fixed-point additions, elementwise gating, and state updates. Loihi 2 contributes three properties that carry the efficiency argument: 120 programmable neuro-cores per chip with co-located memory, asynchronous event-driven communication that skips zero activations, and a barrier-synchronized time step that allows pipelined prefill or fall-through generation. The paper also contributes operator fusion, including a derivation that collapses two consecutive RMSNorm layers into one, and two execution modes that separately optimize prefill throughput and generation latency.

What would settle it

Build the complete 370M model on 31 or more Loihi 2 chips with the embedding and un-embedding layers included, measure end-to-end generation throughput and energy per token, and compare against Table 2. If time-to-first-token rises materially above 99 ms for 500 tokens, or per-token energy grows well beyond 405 mJ, the central efficiency claim fails. A simpler check is to directly measure the 24-chip system's power rather than extrapolating from single-chip static and dynamic power.

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Extended reading notes

Core claim

The central discovery the paper wants to establish is that neuromorphic hardware is not limited to spiking primitives: a complete, competitive language model can be adapted to Loihi 2 by co-designing the model and the chip. The MatMul-free architecture's ternary BitLinear layers turn matrix multiplication into accumulation of ternary weights, and its MLGRU token mixer is a stateful linear recurrence that matches Loihi 2's local-memory, event-driven execution. With fixed-point quantization (W8A16, power-of-two scaling, a LUT sigmoid, and a fixed-point inverse-square-root), the quantized model matches the FP16 baseline's zero-shot accuracy, and the Loihi 2 implementation tracks the quantized PyTorch simulation. On the hardware, one block per chip across 24 chips yields 41.5 tokens per second generation and 6632 tokens per second prefill, both independent of sequence length, which the paper compares favorably with edge-GPU and H100 transformer baselines. The authors are explicit that these are preliminary, measured mostly on the transformer blocks, with embedding and un-embedding projections expected to add little latency.

Load-bearing premise

The reported Loihi 2 numbers come from the 24 transformer blocks only; the paper assumes the embedding and un-embedding layers, which are not yet implemented on the chip, will add negligible latency and modest power, so the full 370M model still generates at roughly 41.5 tokens per second and 405 mJ per token.

Editorial extensions

If this is right

  • Generation throughput on Loihi 2 stays at 41.5 tokens per second whether the sequence is 500 or 16,000 tokens, so longer contexts do not degrade generation speed.
  • Time-to-first-token on a 500-token prompt is 99 ms, about 6.6$\times$ lower than the measured Llama-style transformer on the Jetson, with the gap widening at longer sequences.
  • Running the same MatMul-free model on Loihi 2 uses at least 14$\times$ less energy per generated token than on an H100 GPU, while giving 3$\times$ higher generation throughput.
  • The W8A16 quantization recipe with a raised RMSNorm epsilon retains the model's zero-shot accuracy, suggesting fixed-point hardware need not cost accuracy for this architecture.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the un-embedding layer really fits on 7 additional Loihi 2 chips with negligible latency, a single 32-chip Alia Point system could serve the full 370M model on-chip; the obvious next experiment is to measure that complete 31-chip system and check that per-token energy stays near the 24-chip value.
  • The same mapping recipe (ternary BitLinear layers, power-of-two scaling, LUT nonlinearities, double-RMSNorm fusion) could be applied to other subquadratic recurrent LLMs, not just MatMul-free ones, on Loihi-like hardware.
  • Because throughput is constant in sequence length, the advantage over quadratic-attention transformers should grow beyond the tested 16k context, which is directly testable by running longer prompts once embedding and un-embedding are implemented.
  • The single-chip estimate outperforms the 24-chip measurement, so closing the inter-chip communication and static-power gap is a concrete optimization target that would push generation energy per token well below 405 mJ.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper adapts the 370M-parameter MatMul-free language model of Zhu et al. (2024) to Intel's Loihi 2. It quantizes the model on GPU to 8-bit weights and 16-bit activations, adjusts the RMSNorm epsilon to 1e-3, and reports no average accuracy loss on six zero-shot tasks. It implements the transformer-block stack of the model on Loihi 2, first on a single chip and then on 24 chips of a 32-chip Alia Point system, and reports throughput and energy per token in prefill and generation modes, comparing against transformer LLMs on an NVIDIA Jetson Orin Nano and against a transformer baseline on an H100. The headline result is up to 3x higher generation throughput and approximately 2x lower energy per token on Loihi 2. Additional contributions include a fixed-point sigmoid look-up table, a fixed-point inverse-square-root implementation, and a derivation for fusing two RMSNorm layers.

Significance. The appeal of the paper is clear: if the full 370M MatMul-free LLM really runs on Loihi 2 at 41.5 tokens/s and 405 mJ/token in generation, that would be an important data point for neuromorphic LLM inference. The paper has real strengths: a 24-block implementation on a physical 32-chip Loihi 2 system with direct power measurement for those blocks, a careful quantization ablation, and an explicit multi-chip scaling experiment showing that time-per-step flattens after about five chips. These are concrete, reproducible contributions. The reason I cannot accept the paper in its current form is not the hardware platform or the architecture choice; it is that the measured system is only the 24 transformer blocks, while the abstract and introduction claim a complete 370M model. That gap, plus the absence of end-to-end hardware verification of the full model, makes the headline efficiency numbers extrapolated rather than demonstrated. The paper is best positioned as a workshop-scale feasibility study if the claims are scoped accordingly.

major comments (4)
  1. [4, Table 2, Appendix A.4.1] Section 4 and Table 2 present the Loihi 2 rows as 'MMF (370M) Loihi 2' and the abstract states 'up to 3x higher throughput with 2x less energy', but Appendix A.4.1 explicitly says the embedding and unembedding layers were never implemented on Loihi 2, and that the 1024x32000 ternary unembedding layer alone would require seven additional chips. The statement 'we expect throughput to stay as reported' is an assumption, not a measurement, and it is load-bearing because the claimed advantage is for the complete 370M model. Please either implement the full stack on the 31-chip system and report measured numbers, or relabel every Loihi 2 result as '24 transformer blocks only' and remove the full-model wording from the abstract, intro, and conclusion.
  2. [1] The introduction's assertion that 'we are able to run the MMF model fully on-chip' is directly contradicted by Appendix A.4.1, which states that the embedding and unembedding layers have not been implemented on the Loihi 2 chip. Since the abstract repeats the full-model framing, this is more than a wording slip; it misdescribes what was actually executed. The paper must either implement those layers or explicitly define 'fully on-chip' to mean the 24-block core only.
  3. [4] Section 4 says that 'verification of the model on Loihi 2 indicates close alignment with the quantized PyTorch simulation,' but the preceding sentence specifies that only 'a single block' was implemented and verified on a single chip. Table 2 then reports full-model throughput and energy for the 370M model, implicitly assuming that all 24 blocks behave identically and that no cross-block verification was performed. Please report an end-to-end accuracy or perplexity measurement on the 24-chip system, or state clearly that the hardware accuracy was verified only for a single block and that the Table 2 numbers are extrapolations from block-level measurements.
  4. [3, Table 1] The 'no accuracy loss' claim in the abstract is supported by one row of Table 1 (PT + W8A16 with epsilon_rms raised to 1e-3), but the epsilon change is a free parameter that was apparently selected after observing its effect on the same six benchmark tasks, and the adjacent row (W8A8 + epsilon_rms) shows a 10.7% drop. To make the claim robust, report sensitivity of the result to epsilon (e.g., 1e-4, 1e-2) and either use a held-out set or explicitly label the configuration as post-hoc tuned on these benchmarks. This does not invalidate the quantization study, but it changes the strength of the 'no accuracy loss' statement.
minor comments (5)
  1. [Table 1] In the last row, the average column reads '39.8%' with a stray percent sign, while other rows use plain numbers; please make the formatting consistent.
  2. [Appendix A.3] After Eq. (15), the sentence 'since the denominator depends on mu_x, it may not be possible to express epsilon_combined independently' is confusing because Eq. (15) does express epsilon_combined independently and the derivation is exact; please clarify whether the combined form is exact or approximate.
  3. [4] The note 'All current comparisons are performed with FP16 baselines on non-Loihi hardware' is too terse and should be moved into the experimental setup, where it can explain why the MatMul-free baseline was not run on the Jetson.
  4. [A.5] The body text refers to 'Figure A.5' for the RMSNorm computational graph, but the appendix figure is labeled Figure 7; please align cross-references.
  5. [5] Section 5 describes this as 'the first demonstration of a modern LLM architecture on neuromorphic hardware'; given that only the block stack was implemented and that prior spiking LLM work exists, please qualify this claim or drop the 'first' phrasing.

Circularity Check

0 steps flagged · score 1.0 of 10

No meaningful circularity: the hardware measurements, fixed-point implementation, and quantization comparisons are independent of the paper's headline claims, with only benign same-group citations.

full rationale

The central efficiency claims rest on measured or explicitly extrapolated Loihi 2 results rather than on the claims themselves. Appendix A.4.1 reports single-chip measurements, a 24-chip multi-chip implementation on an Alia Point system, and direct measurement of power and energy for that system, so the Table 2 numbers for the 24-block model are not derived by assuming the conclusion. The quantization claim is an empirical evaluation in Table 1: the authors reimplement the model, compare the PyTorch baseline against several quantization schemes, and select W8A16 after observing its 0.0% average difference; this is model selection from measured results, not a fitted parameter being renamed as a prediction. The architecture is taken from Zhu et al. (2024), whose author list overlaps with this paper, but the paper does not use that work as an unverified uniqueness theorem or as the justification for the hardware result; it uses it as a base architecture to port, and the Loihi mapping, fixed-point approximations, and benchmark measurements are new experiments. Self-citations to Abreu et al. (2024) and Pierro & Abreu (2024) support expectations about quantization of state space models but are not load-bearing for the Loihi comparison. The inconsistency between the Introduction's 'run the MMF model fully on-chip' and Appendix A.4.1's statement that embedding and un-embedding layers were not implemented is a completeness or extrapolation concern, not a circular one. No claim in the paper reduces by construction to one of its inputs, and no fitted value is presented as an independent prediction.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

The central hardware comparison rests on the completeness of the measured Loihi 2 system, on the fidelity of the PyTorch fake-quantization to the hardware fixed-point arithmetic, and on the fairness of the transformer baselines. These are assumptions rather than fitted numbers; the only hand-chosen numeric constant that directly tunes the quantization claim is epsilon_rms.

free parameters (3)
  • epsilon_rms = 1e-3 (changed from 1e-6)
    Raised to 1e-3 so that the RMSNorm variance term does not underflow with 12 fractional bits; the choice is reported in Section 3 and Table 1 as necessary for the W8A16 result, so the 'no accuracy loss' claim is contingent on this hand-set value.
  • sigmoid LUT precision (xexp=6, N_sigma=8) = xexp=6, N_sigma=8
    Chosen for the fixed-point sigmoid lookup table in Appendix A.2.1; no sensitivity analysis is given, so the Loihi 2 numerical equivalence depends on this manual choice.
  • inv_sqrt LUT size and Newton iterations = 24 LUT entries, 5 iterations
    Chosen for the fixed-point inverse square root in Appendix A.2.2; again without sensitivity analysis, it is a manual approximation parameter.
assumptions (4)
  • domain assumption Symmetric power-of-two quantization with fake quantization in PyTorch accurately models Loihi 2 fixed-point arithmetic.
    Section 3 states 'fake quantization' is used and then the Loihi 2 implementation is verified as 'close alignment'; no formal equivalence is given.
  • domain assumption Close alignment between a single-block Loihi 2 implementation and the PyTorch simulation suffices to guarantee full 24-block model accuracy.
    Section 4 reports verification only for 'a single block', but the accuracy claim in the abstract refers to the full 370M model.
  • ad hoc to paper Adding embedding and unembedding layers on 7 extra Loihi 2 chips will not materially change throughput or energy.
    Appendix A.4.1 says 'we expect throughput to stay as reported... The system will draw more power due to the additional layers, but we expect further performance optimizations to outweigh the power of two extra layers.' This is an unmeasured expectation.
  • domain assumption The Jetson Orin Nano transformer baselines (Alireo-400M and Qwen2.5-500M) are representative edge GPU comparators for a 370M MatMul-free model.
    Section 4 chooses these models because they are 'similarly-sized', but they have different parameter counts, context windows, and training data; Alireo is Italian-only.

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Cite this review

Pith. "Pith review of Neuromorphic Principles for Efficient Large Language Models on Intel Loihi 2." pith.science (2026). https://pith.science/paper/XURSXUWB

@misc{pith2026250318002,
  author       = {Pith},
  title        = {Pith review of: Neuromorphic Principles for Efficient Large Language Models on Intel Loihi 2},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/XURSXUWB}},
  note         = {Machine review of arXiv:2503.18002}
}
read the original abstract

Large language models (LLMs) deliver impressive performance but require large amounts of energy. In this work, we present a MatMul-free LLM architecture adapted for Intel's neuromorphic processor, Loihi 2. Our approach leverages Loihi 2's support for low-precision, event-driven computation and stateful processing. Our hardware-aware quantized model on GPU demonstrates that a 370M parameter MatMul-free model can be quantized with no accuracy loss. Based on preliminary results, we report up to 3x higher throughput with 2x less energy, compared to transformer-based LLMs on an edge GPU, with significantly better scaling. Further hardware optimizations will increase throughput and decrease energy consumption. These results show the potential of neuromorphic hardware for efficient inference and pave the way for efficient reasoning models capable of generating complex, long-form text rapidly and cost-effectively.

Figures

Figures reproduced from arXiv: 2503.18002 by the authors.

Figure 1
Figure 1. Model architecture of the MatMul-free language model from Zhu et al. (2024). [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Different Loihi 2 systems are available to cover a wide range of applications from the edge [PITH_FULL_IMAGE:figures/full_fig_p011_2.png] view at source ↗
Figure 3
Figure 3. Different execution modes on Loihi 2 that either optimize throughput or latency. In the [PITH_FULL_IMAGE:figures/full_fig_p012_3.png] view at source ↗
Figures from the paper (4 more)
Figure 4
Figure 4. Figure 4: Power of one MatMul-free block on a single-chip Loihi 2 system. [PITH_FULL_IMAGE:figures/full_fig_p014_4.png]
Figure 5
Figure 5. Figure 5: Scaling of time per step (inversely proportional to throughput, see text), power per chip [PITH_FULL_IMAGE:figures/full_fig_p015_5.png]
Figure 6
Figure 6. Figure 6: Hardware results for transformer-based LLMs running on the NVIDIA Jetson Orin Nano. [PITH_FULL_IMAGE:figures/full_fig_p016_6.png]
Figure 7
Figure 7. Figure 7: Left: Computational graph of a single MatMul-free LM layer, simplified from the actual computational graph that is mapped on the Loihi 2 chip. The RMSNorm is visualized as a single node. Right: Computational graph of the RMSNorm layer implemented on the Loihi 2 chip. F…

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Reference graph

Works this paper leans on

41 extracted references · 11 canonical work pages

  1. [1]

    Pedersen, Kade M

    Steven Abreu, Jens E. Pedersen, Kade M. Heckel, and Alessandro Pierro. Q- S5 : Towards Quantized State Space Models , June 2024. URL http://arxiv.org/abs/2406.09477. arXiv:2406.09477 [cs]

    arXiv 2024

  2. [2]

    PIQA : Reasoning about Physical Commonsense in Natural Language

    Yonatan Bisk, Rowan Zellers, Ronan Le Bras, Jianfeng Gao, and Yejin Choi. PIQA : Reasoning about Physical Commonsense in Natural Language . Proceedings of the AAAI Conference on Artificial Intelligence, 34 0 (05): 0 7432--7439, April 2020. ISSN 2374-3468. doi:10.1609/aaai.v34i05.6239. URL https://ojs.aaai.org/index.php/AAAI/article/view/6239. Number: 05

    doi:10.1609/aaai.v34i05.6239 2020

  3. [3]

    Quamba: A Post - Training Quantization Recipe for Selective State Space Models , October 2024

    Hung-Yueh Chiang, Chi-Chih Chang, Natalia Frumkin, Kai-Chiang Wu, and Diana Marculescu. Quamba: A Post - Training Quantization Recipe for Selective State Space Models , October 2024. URL http://arxiv.org/abs/2410.13229. arXiv:2410.13229

    arXiv 2024

  4. [4]

    Learning Phrase Representations using RNN Encoder – Decoder for Statistical Machine Translation

    Kyunghyun Cho, Bart van Merriënboer, Caglar Gulcehre, Dzmitry Bahdanau, Fethi Bougares, Holger Schwenk, and Yoshua Bengio. Learning Phrase Representations using RNN Encoder – Decoder for Statistical Machine Translation . In Alessandro Moschitti, Bo Pang, and Walter Daelemans (eds.), Proceedings of the 2014 Conference on Empirical Methods in Natural Langua...

    doi:10.3115/v1/d14-1179 2014

  5. [5]

    Think you have Solved Question Answering ? Try ARC , the AI2 Reasoning Challenge , March 2018

    Peter Clark, Isaac Cowhey, Oren Etzioni, Tushar Khot, Ashish Sabharwal, Carissa Schoenick, and Oyvind Tafjord. Think you have Solved Question Answering ? Try ARC , the AI2 Reasoning Challenge , March 2018. URL http://arxiv.org/abs/1803.05457. arXiv:1803.05457

    arXiv 2018

  6. [6]

    Binarized Neural Networks : Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1, March 2016

    Matthieu Courbariaux, Itay Hubara, Daniel Soudry, Ran El-Yaniv, and Yoshua Bengio. Binarized Neural Networks : Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1, March 2016. URL http://arxiv.org/abs/1602.02830. arXiv:1602.02830 [cs]

    arXiv 2016

  7. [7]

    Dauphin, Angela Fan, Michael Auli, and David Grangier

    Yann N. Dauphin, Angela Fan, Michael Auli, and David Grangier. Language modeling with gated convolutional networks. In Proceedings of the 34th International Conference on Machine Learning - Volume 70 , ICML '17, pp.\ 933--941, Sydney, NSW, Australia, August 2017. JMLR.org

    work page 2017

  8. [8]

    Fonseca Guerra, Prasad Joshi, Philipp Plank, and Sumedh R

    Mike Davies, Andreas Wild, Garrick Orchard, Yulia Sandamirskaya, Gabriel A. Fonseca Guerra, Prasad Joshi, Philipp Plank, and Sumedh R. Risbud. Advancing Neuromorphic Computing With Loihi : A Survey of Results and Outlook . Proceedings of the IEEE, 109 0 (5): 0 911--934, May 2021. doi:10.1109/jproc.2021.3067593. Publisher: Institute of Electrical and Elect...

    arXiv 2021

Show all 41 references
  1. [9]

    DeepSeek-AI, Daya Guo, Dejian Yang, Haowei Zhang, Junxiao Song, Ruoyu Zhang, Runxin Xu, Qihao Zhu, Shirong Ma, Peiyi Wang, Xiao Bi, Xiaokang Zhang, Xingkai Yu, Yu Wu, Z. F. Wu, Zhibin Gou, Zhihong Shao, Zhuoshu Li, Ziyi Gao, Aixin Liu, Bing Xue, Bingxuan Wang, Bochao Wu, Bei F...

    2025 arXiv

  2. [10]

    LLM .int8(): 8-bit Matrix Multiplication for Transformers at Scale , November 2022

    Tim Dettmers, Mike Lewis, Younes Belkada, and Luke Zettlemoyer. LLM .int8(): 8-bit Matrix Multiplication for Transformers at Scale , November 2022. URL http://arxiv.org/abs/2208.07339. arXiv:2208.07339 [cs]

    2022 arXiv

  3. [11]

    GPTQ : Accurate Post - Training Quantization for Generative Pre -trained Transformers , March 2023

    Elias Frantar, Saleh Ashkboos, Torsten Hoefler, and Dan Alistarh. GPTQ : Accurate Post - Training Quantization for Generative Pre -trained Transformers , March 2023. URL http://arxiv.org/abs/2210.17323. arXiv:2210.17323 [cs]

    2023 arXiv

  4. [12]

    Mamba: Linear-time sequence modeling with selective state spaces

    Albert Gu and Tri Dao. Mamba: Linear-time sequence modeling with selective state spaces. arXiv preprint arXiv:2312.00752, 2023

    2023 arXiv

  5. [13]

    Diagonal state spaces are as effective as structured state spaces

    Ankit Gupta, Albert Gu, and Jonathan Berant. Diagonal state spaces are as effective as structured state spaces. Advances in Neural Information Processing Systems, 35: 0 22982--22994, 2022

    2022

  6. [14]

    Multiplication- Free Transformer Training via Piecewise Affine Operations , October 2023

    Atli Kosson and Martin Jaggi. Multiplication- Free Transformer Training via Piecewise Affine Operations , October 2023. URL http://arxiv.org/abs/2305.17190. arXiv:2305.17190 [cs]

    2023 arXiv

  7. [15]

    The Era of 1-bit LLMs : All Large Language Models are in 1.58 Bits , February 2024

    Shuming Ma, Hongyu Wang, Lingxiao Ma, Lei Wang, Wenhui Wang, Shaohan Huang, Li Dong, Ruiping Wang, Jilong Xue, and Furu Wei. The Era of 1-bit LLMs : All Large Language Models are in 1.58 Bits , February 2024. URL http://arxiv.org/abs/2402.17764. arXiv:2402.17764 [cs]

    2024 arXiv

  8. [16]

    Can a Suit of Armor Conduct Electricity ? A New Dataset for Open Book Question Answering

    Todor Mihaylov, Peter Clark, Tushar Khot, and Ashish Sabharwal. Can a Suit of Armor Conduct Electricity ? A New Dataset for Open Book Question Answering . In EMNLP , 2018

    2018

  9. [17]

    Alireo-400m: A lightweight italian language model, 2024

    Michele Montebovi. Alireo-400m: A lightweight italian language model, 2024. URL https://huggingface.co/DeepMount00/Alireo-400m-instruct-v0.1

    2024

  10. [18]

    Dnnfusion: accelerating deep neural networks execution with advanced operator fusion

    Wei Niu, Jiexiong Guan, Yanzhi Wang, Gagan Agrawal, and Bin Ren. Dnnfusion: accelerating deep neural networks execution with advanced operator fusion. In Proceedings of the 42nd ACM SIGPLAN International Conference on Programming Language Design and Implementation, PLDI 2021, ...

    2021

  11. [19]

    Efficient neuromorphic signal processing with loihi 2

    Garrick Orchard, E Paxon Frady, Daniel Ben Dayan Rubin, Sophia Sanborn, Sumit Bam Shrestha, Friedrich T Sommer, and Mike Davies. Efficient neuromorphic signal processing with loihi 2. In 2021 IEEE Workshop on Signal Processing Systems (SiPS), pp.\ 254--259. IEEE, 2021 a

    2021

  12. [20]

    Paxon Frady, Daniel Ben Dayan Rubin, Sophia Sanborn, Sumit Bam Shrestha, Friedrich T

    Garrick Orchard, E. Paxon Frady, Daniel Ben Dayan Rubin, Sophia Sanborn, Sumit Bam Shrestha, Friedrich T. Sommer, and Mike Davies. Efficient Neuromorphic Signal Processing with Loihi 2. In 2021 IEEE Workshop on Signal Processing Systems ( SiPS ) . IEEE, October 2021 b . doi:10...

    2021

  13. [21]

    Mamba- PTQ : Outlier Channels in Recurrent Large Language Models , July 2024

    Alessandro Pierro and Steven Abreu. Mamba- PTQ : Outlier Channels in Recurrent Large Language Models , July 2024. URL http://arxiv.org/abs/2407.12397. arXiv:2407.12397 [cs]

    2024 arXiv

  14. [22]

    Hierarchically Gated Recurrent Neural Network for Sequence Modeling

    Zhen Qin, Songlin Yang, and Yiran Zhong. Hierarchically Gated Recurrent Neural Network for Sequence Modeling . Advances in Neural Information Processing Systems, 36: 0 33202--33221, December 2023

    2023

  15. [23]

    HGRN2 : Gated Linear RNNs with State Expansion , April 2024

    Zhen Qin, Songlin Yang, Weixuan Sun, Xuyang Shen, Dong Li, Weigao Sun, and Yiran Zhong. HGRN2 : Gated Linear RNNs with State Expansion , April 2024. URL http://arxiv.org/abs/2404.07904. arXiv:2404.07904 [cs]

    2024 arXiv

  16. [24]

    Qwen2.5: A party of foundation models, September 2024

    Qwen Team . Qwen2.5: A party of foundation models, September 2024. URL https://qwenlm.github.io/blog/qwen2.5/

    2024

  17. [25]

    WinoGrande : an adversarial winograd schema challenge at scale

    Keisuke Sakaguchi, Ronan Le Bras, Chandra Bhagavatula, and Yejin Choi. WinoGrande : an adversarial winograd schema challenge at scale. Commun. ACM, 64 0 (9): 0 99--106, August 2021. ISSN 0001-0782. doi:10.1145/3474381. URL https://dl.acm.org/doi/10.1145/3474381

    2021 doi

  18. [26]

    Efficient Video and Audio Processing with Loihi 2

    Sumit Bam Shrestha, Jonathan Timcheck, Paxon Frady, Leobardo Campos-Macias, and Mike Davies. Efficient Video and Audio Processing with Loihi 2. In ICASSP 2024 - 2024 IEEE International Conference on Acoustics , Speech and Signal Processing ( ICASSP ) , pp.\ 13481--13485, April...

    2024

  19. [27]

    Gomez, Lukasz Kaiser, and Illia Polosukhin

    Ashish Vaswani, Noam Shazeer, Niki Parmar, Jakob Uszkoreit, Llion Jones, Aidan N. Gomez, Lukasz Kaiser, and Illia Polosukhin. Attention Is All You Need . June 2017. URL https://nlp.seas.harvard.edu/2018/04/03/attention.html. \_eprint: 1706.03762

    2017 arXiv

  20. [28]

    Convfusion: A model for layer fusion in convolutional neural networks

    Luc Waeijen, Savvas Sioutas, Maurice Peemen, Menno Lindwer, and Henk Corporaal. Convfusion: A model for layer fusion in convolutional neural networks. IEEE Access, 9: 0 168245--168267, 2021. doi:10.1109/ACCESS.2021.3134930

    2021

  21. [29]

    SmoothQuant : Accurate and Efficient Post - Training Quantization for Large Language Models , March 2024

    Guangxuan Xiao, Ji Lin, Mickael Seznec, Hao Wu, Julien Demouth, and Song Han. SmoothQuant : Accurate and Efficient Post - Training Quantization for Large Language Models , March 2024. URL http://arxiv.org/abs/2211.10438. arXiv:2211.10438 [cs]

    2024 arXiv

  22. [30]

    Qwen2 technical report

    An Yang, Baosong Yang, Binyuan Hui, Bo Zheng, Bowen Yu, Chang Zhou, Chengpeng Li, Chengyuan Li, Dayiheng Liu, Fei Huang, Guanting Dong, Haoran Wei, Huan Lin, Jialong Tang, Jialin Wang, Jian Yang, Jianhong Tu, Jianwei Zhang, Jianxin Ma, Jin Xu, Jingren Zhou, Jinze Bai, Jinzheng...

    2024 arXiv

  23. [31]

    ShiftAddLLM : Accelerating Pretrained LLMs via Post - Training Multiplication - Less Reparameterization , July 2024

    Haoran You, Yipin Guo, Yichao Fu, Wei Zhou, Huihong Shi, Xiaofan Zhang, Souvik Kundu, Amir Yazdanbakhsh, and Yingyan Celine Lin. ShiftAddLLM : Accelerating Pretrained LLMs via Post - Training Multiplication - Less Reparameterization , July 2024. URL http://arxiv.org/abs/2406.0...

    2024 arXiv

  24. [32]

    Metaformer is actually what you need for vision

    Weihao Yu, Mi Luo, Pan Zhou, Chenyang Si, Yichen Zhou, Xinchao Wang, Jiashi Feng, and Shuicheng Yan. Metaformer is actually what you need for vision. In Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR), pp.\ 10819--10829, June 2022

    2022

  25. [33]

    Rowan Zellers, Ari Holtzman, Yonatan Bisk, Ali Farhadi, and Yejin Choi. HellaSwag : Can a Machine Really Finish Your Sentence ? In Anna Korhonen, David Traum, and Lluís Màrquez (eds.), Proceedings of the 57th Annual Meeting of the Association for Computational Linguistics , pp...

    2019 doi

  26. [34]

    Root Mean Square Layer Normalization

    Biao Zhang and Rico Sennrich. Root Mean Square Layer Normalization . In Advances in Neural Information Processing Systems , volume 32. Curran Associates, Inc., 2019

    2019

  27. [35]

    Binarized Neural Machine Translation , February 2023

    Yichi Zhang, Ankush Garg, Yuan Cao, Lukasz Lew, Behrooz Ghorbani, Zhiru Zhang, and Orhan Firat. Binarized Neural Machine Translation , February 2023. URL http://arxiv.org/abs/2302.04907. arXiv:2302.04907 [cs]

    2023 arXiv

  28. [36]

    Spikegpt: Generative pre-trained language model with spiking neural networks

    Rui-Jie Zhu, Qihang Zhao, Guoqi Li, and Jason K Eshraghian. Spikegpt: Generative pre-trained language model with spiking neural networks. arXiv preprint arXiv:2302.13939, 2023

    2023 arXiv

  29. [37]

    Eshraghian

    Rui-Jie Zhu, Yu Zhang, Ethan Sifferman, Tyler Sheaves, Yiqiao Wang, Dustin Richmond, Peng Zhou, and Jason K. Eshraghian. Scalable MatMul -free Language Modeling , 2024. URL http://arxiv.org/abs/2406.02528. arXiv:2406.02528 [cs]

    2024 arXiv

  30. [38]

    write newline

    " write newline "" before.all 'output.state := FUNCTION n.dashify 't := "" t empty not t #1 #1 substring "-" = t #1 #2 substring "--" = not "--" * t #2 global.max substring 't := t #1 #1 substring "-" = "-" * t #2 global.max substring 't := while if t #1 #1 substring * t #2 gl...

  31. [39]

    @esa (Ref

    \@ifxundefined[1] #1\@undefined \@firstoftwo \@secondoftwo \@ifnum[1] #1 \@firstoftwo \@secondoftwo \@ifx[1] #1 \@firstoftwo \@secondoftwo [2] @ #1 \@temptokena #2 #1 @ \@temptokena \@ifclassloaded agu2001 natbib The agu2001 class already includes natbib coding, so you should ...

  32. [40]

    \@lbibitem[] @bibitem@first@sw\@secondoftwo \@lbibitem[#1]#2 \@extra@b@citeb \@ifundefined br@#2\@extra@b@citeb \@namedef br@#2 \@nameuse br@#2\@extra@b@citeb \@ifundefined b@#2\@extra@b@citeb @num @parse #2 @tmp #1 NAT@b@open@#2 NAT@b@shut@#2 \@ifnum @merge>\@ne @bibitem@firs...

  33. [41]

    @open @close @open @close and [1] URL: #1 \@ifundefined chapter * \@mkboth \@ifxundefined @sectionbib * \@mkboth * \@mkboth\@gobbletwo \@ifclassloaded amsart * \@ifclassloaded amsbook * \@ifxundefined @heading @heading NAT@ctr thebibliography [1] @ \@biblabel @NAT@ctr \@bibset...

Pith tools

Reviewed August 8, 2026 · model on record in the stance chip above.