Pith. sign in

REVIEW 6 cited by

UB-Mesh: a Hierarchically Localized nD-FullMesh Datacenter Network Architecture

Not yet reviewed by Pith; the record is open.

This paper has not been read by Pith yet. Machine review is queued; the pith claim, tier, and objections will appear here once it completes.

SPECIMEN: schema-true, not a live event

T0 review · schema-true

One-sentence machine reading of the paper's core claim.

pith:XXXXXXXX · record.json · timestamp

arxiv 2503.20377 v3 pith:BRN6XW3Y submitted 2025-03-26 cs.AR cs.NI

UB-Mesh: a Hierarchically Localized nD-FullMesh Datacenter Network Architecture

classification cs.AR cs.NI
keywords architectureub-meshdesignnetworkbandwidthdatand-fullmeshtopology
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
0 comments
Share X Bluesky LinkedIn Reddit HN
read the original abstract

As the Large-scale Language Models (LLMs) continue to scale, the requisite computational power and bandwidth escalate. To address this, we introduce UB-Mesh, a novel AI datacenter network architecture designed to enhance scalability, performance, cost-efficiency and availability. Unlike traditional datacenters that provide symmetrical node-to-node bandwidth, UB-Mesh employs a hierarchically localized nD-FullMesh network topology. This design fully leverages the data locality of LLM training, prioritizing short-range, direct interconnects to minimize data movement distance and reduce switch usage. Although UB-Mesh's nD-FullMesh topology offers several theoretical advantages, its concrete architecture design, physical implementation and networking system optimization present new challenges. For the actual construction of UB-Mesh, we first design the UB-Mesh-Pod architecture, which is based on a 4D-FullMesh topology. UB-Mesh-Pod is implemented via a suite of hardware components that serve as the foundational building blocks, including specifically-designed NPU, CPU, Low-Radix-Switch (LRS), High-Radix-Switch (HRS), NICs and others. These components are interconnected via a novel Unified Bus (UB) technique, which enables flexible IO bandwidth allocation and hardware resource pooling. For networking system optimization, we propose advanced routing mechanism named All-Path-Routing (APR) to efficiently manage data traffic. These optimizations, combined with topology-aware performance enhancements and robust reliability measures like 64+1 backup design, result in 2.04x higher cost-efficiency, 7.2% higher network availability compared to traditional Clos architecture and 95%+ linearity in various LLM training tasks.

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Forward citations

Cited by 6 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. A Switch-Centric In-Network Architecture for Accelerating LLM Inference in Shared-Memory Network

    cs.AR 2026-03 unverdicted novelty 7.0

    SCIN uses an in-switch accelerator for direct memory access and 8-bit in-network quantization during All-Reduce, delivering up to 8.7x faster small-message reduction and 1.74x TTFT speedup on LLaMA-2 models.

  2. StrataCL: Fabric-Native Communication Library for Production Supernodes

    cs.DC 2026-07 conditional novelty 6.0

    On Huawei CloudMatrix384, StrataCL's registration-on-allocation and fabric-native operators raise collective bus bandwidth up to 1.6x and LLM inference throughput by 1.9x versus HCCL baselines.

  3. Switching Efficiency: A Novel Framework for Dissecting AI Data Center Network Efficiency

    cs.NI 2026-04 unverdicted novelty 6.0

    Introduces Switching Efficiency (η) decomposed into data, routing efficiency, and port utilization factors to analyze and improve communication bottlenecks in AI data center networks for LLM training.

  4. TENT: A Declarative Slice Spraying Engine for Performant and Resilient Data Movement in Disaggregated LLM Serving

    cs.DC 2026-04 conditional novelty 6.0

    A telemetry-driven slice-spraying transfer engine with late-binding path selection improves LLM serving throughput and self-heals from link failures in tens of milliseconds.

  5. Demystifying the Design Space and Best Practices for Heterogeneous LLM Inference and Serving

    cs.DC 2026-06 unverdicted novelty 5.0

    The paper organizes heterogeneous prefill-decode LLM serving into a four-axis design space and identifies three recurring boundary decisions that require joint choices.

  6. Demystifying the Design Space and Best Practices for Heterogeneous LLM Inference and Serving

    cs.DC 2026-06 unverdicted novelty 5.0

    Organizes the heterogeneous LLM prefill-decode design space along four axes and extracts three boundary decisions with guidance on precision, KV representation, and ownership.