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LASHED: LLMs And Static Hardware Analysis for Early Detection of RTL Bugs
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While static analysis is useful in detecting early-stage hardware security bugs, its efficacy is limited because it requires information to form checks and is often unable to explain the security impact of a detected vulnerability. Large Language Models can be useful in filling these gaps by identifying relevant assets, removing false violations flagged by static analysis tools, and explaining the reported violations. LASHED combines the two approaches (LLMs and Static Analysis) to overcome each other's limitations for hardware security bug detection. We investigate our approach on four open-source SoCs for five Common Weakness Enumerations (CWEs) and present strategies for improvement with better prompt engineering. We find that 87.5% of instances flagged by our recommended scheme are plausible CWEs. In-context learning and asking the model to 'think again' improves LASHED's precision.
Forward citations
Cited by 2 Pith papers
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CHARGE: Leveraging CWE Hierarchies for Hardware Security SystemVerilog Assertion Generation
Using CWE hierarchy-aware LLM prompts, CHARGE generates security SVAs from unverified RTL, detecting 27 of 42 Hack@DAC bugs and one new key-reuse flaw.
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Hardware Design and Security in the Era of Chiplets and LLMs
A survey uniting chiplet-hardware security and LLM-driven EDA security that identifies a missing bridge: LLM-based security tools are not yet tailored to 2.5D/3D chiplet systems.
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