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REVIEW 2 major objections 7 minor 52 references

Erasure Minesweeper: exploring hybrid-erasure surface code architectures for efficient quantum error correction

T0 review · 2 major / 7 minor · reviewed 2026-08-16 · deepseek-v4-flash

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Pith's one-line read A hybrid surface code with strategically placed erasure qubits reaches lower logical error rates than all-standard or all-erasure designs at the same transmon budget.

desk verdict A useful, honest first pass at hybrid erasure placement for surface codes; the transmon-budget advantage is plausible but hinges on perfect erasure checks, so read it as a best-case architecture study. read the letter →

arxiv 2505.00066 v2 pith:NKGRKGI7 submitted 2025-04-30 quant-ph

Jason D. Chadwick , Mariesa H. Teo , Joshua Viszlai , Willers Yang , Frederic T. Chong This is my paper · ORCID
classification quant-ph PACS 03.67.Pp
keywords quantumerrorcorrectionerasurequbitssurfacecodedual-railtransmonhybridarchitectureeffectivedistancelogicalratequbitplacement
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper tries to establish that you do not need every qubit to be an erasure qubit to capture most of the benefit. It proposes a hybrid surface code in which a selected subset of data qubits are dual-rail erasure qubits, each costing three transmons, while the rest remain standard. With erasure qubits placed in full central rows and columns, effective distance and threshold improve steadily as the erasure fraction grows, and for certain fixed transmon budgets the hybrid layout beats both an all-standard and an all-erasure chip. This matters because fabrication yield and refrigerator cooling limit the number of transmons available, so spending transmons where they buy the most logical performance is a practical architectural choice.

What carries the argument

The load-bearing object is the hybrid-erasure architecture $A(d,f_e,P)$: a distance-$d$ surface-code patch with erasure fraction $f_e$ placed on data-qubit subset $P$. The argument decomposes logical errors into lattice-traversing paths, connected chains of errors crossing the patch, and shows that once $k$ full rows and columns are filled with erasure qubits, every such path must cross at least $k$ erasure qubits. This reduces the effective-distance analysis to a repetition-code-like chain with $k$ clean barriers and yields the bound in Eq. 2. In circuit-level decoding, the machinery is the erasure flag: when an erasure check fires, the correlated error set's decoding-graph edges are reweighted, and when it does not fire, those edges are removed from the graph, so the decoder has strictly more information than the syndrome alone provides.

What would settle it

Run the same circuit-level sweep with finite erasure-check false-positive and false-negative rates, for example 1% and 5%, and check whether any transmon budget still favors the hybrid layout over both all-standard and all-erasure chips; if the hybrid curve never falls below both homogeneous curves at fixed transmon count, the central claim is refuted.

Watch

Extended reading notes

Core claim

The paper's central claim is that a distance-$d$ surface-code patch with a chosen subset of data qubits as dual-rail erasure qubits—optimally arranged in full rows and columns radiating from the center—achieves effective distance at least $\lfloor(d(2-\sqrt{1-f_e})+1)/2\rfloor-\epsilon_d$ for erasure fraction $f_e$, interpolating between the standard surface code and the all-erasure surface code. Code-capacity analysis and circuit-level simulations for distances 3, 5, and 7 show effective distance and threshold rising with erasure fraction, and for fixed transmon budgets near 70–100 and 150–190 transmons the hybrid chip reaches lower logical error rates than either homogeneous extreme. The mechanism is that erasure qubits supply the decoder with certified information about where errors did and did not occur, converting a blind error-guessing problem into a Minesweeper-like deduction.

Load-bearing premise

The argument depends on erasure checks never being wrong and on every erasure-qubit error being announced; if real checks miss detections or falsely flag, the decoder's special knowledge is corrupted, and the claimed transmon-budget advantage could shrink or disappear.

Editorial extensions

If this is right

  • Effective distance and threshold rise monotonically with erasure fraction, interpolating between the standard surface code and the all-erasure surface code.
  • Placement is decisive: central rows and columns outperform random placement at intermediate erasure fractions, with the largest gains on qubits that appear in the most lattice-traversing paths.
  • For fixed transmon budgets around 70–100 and 150–190 transmons, a hybrid chip can reach lower logical error rates than either an all-standard or an all-erasure chip at the same cost.
  • The hybrid advantage shrinks as system size grows, so the payoff is largest for near-term small-distance patches and for concatenated-code settings that rely on small surface-code patches.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Beyond the paper: because filled rows and columns of erasure qubits block logical error paths, the same placement heuristic should give tunable asymmetric protection under biased noise, offering a cheaper alternative to nonsquare or XZZX surface codes.
  • Beyond the paper: if imperfect erasure checks are included, the optimal erasure fraction should drop and the transmon-budget window should narrow; sweeping false-positive and false-negative rates would map exactly where the hybrid design still wins.
  • Beyond the paper: the placement heuristic could be repurposed for defect tolerance, reserving erasure positions on known-bad or high-error transmon locations rather than allocating them before fabrication data is known.
  • Beyond the paper: the circuit-level checkerboard correlation pattern suggests that CNOT scheduling, not just placement, controls which error channel benefits; rotating the stabilizer schedule could make the hybrid gain channel-specific and testable in simulation.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

2 major / 7 minor

Summary. This paper proposes a hybrid-erasure surface code architecture in which a strategically chosen subset of data qubits are implemented as dual-rail erasure qubits while the remaining qubits are standard transmons. The authors derive a code-capacity effective-distance bound (Eq. 2) based on the number of full rows and columns of erasure qubits that any lattice-traversing error path must cross, propose a center-first placement heuristic, and validate the heuristic through circuit-level simulations using Stim and PyMatching. They then compare logical error rates as a function of transmon budget for hybrid, all-standard, and all-erasure architectures (Figures 9 and 10), concluding that hybrid layouts can outperform both homogeneous layouts for certain intermediate transmon budgets, particularly at near-term system sizes. The paper is explicitly exploratory and includes a limitations section (Section IV.D) that acknowledges the main idealizations.

Significance. The hybrid-interpolation idea is timely and practically motivated. The paper has several genuine strengths: Eq. (2) is an explicit closed-form bound with no fitted constants; the placement heuristic is derived from an error-path counting argument and is then checked against independent circuit-level simulations; the simulation methodology uses widely available open-source tools (Stim and PyMatching), making the results reproducible; and the authors are transparent about the assumptions behind their noise model. If the stated idealized noise model is accepted, the central transmon-budget conclusion is credible for small to intermediate code distances. The main caveat is that the advantage rests on perfect erasure checks and fully heralded erasure errors, both acknowledged but not modeled, so the quantitative scope of the headline claim remains conditional.

major comments (2)
  1. [Section IV.A/IV.B/IV.D] The decoder's treatment of erasure flags is load-bearing for the headline claim. In Section IV.B, edges are removed from the decoding graph when no erasure flag is observed, which is equivalent to treating an unflagged erasure qubit as certified error-free. This is justified only under the Section IV.A assumption that erasure checks are perfect, with no false positives or false negatives, and under the Section IV.B assumption that every error on an erasure qubit is a heralded erasure followed by a maximally mixed replacement. Section IV.D acknowledges that real checks are imperfect and that unheralded Pauli errors exist, but these are not modeled. A false negative or an unheralded Pauli error would corrupt the 'no-erasure' information and make the edge-deletion step incorrect, potentially shrinking or eliminating the transmon-budget advantage claimed in Section V.B. I request either a sensitivity analysis with nonzero erasure-check error rates and unheralded Pauli fractions, or a clearly stated set of conditions under which the advantage persists. The abstract and conclusion should also carry this qualifier.
  2. [Table I, Section IV.D, Section V.B] The transmon-budget comparisons are computed at a single parameter point: the noise ratios in Table I and the three-transmon cost per erasure qubit. Section IV.D concedes that the results are sensitive to these ratios and that reducing the cost or error-rate ratio would contract the regions where hybrid architectures outperform the homogeneous alternatives. Because the central claim is specifically about 'certain transmon budgets', the paper should provide a quantitative sensitivity scan over the erasure-to-standard error-rate ratio and over the erasure-qubit cost (for example, the two-transmon cavity-readout implementation mentioned in Section IV.D). Without such a scan, the reader cannot tell whether the observed hybrid advantage is robust or an artifact of the chosen parameter point.
minor comments (7)
  1. [Section III.A/III.D] The epsilon term in Eq. (2) is not defined consistently: Section III.A writes 'epsilon_d approximately -d/log p < 1', while Section III.D defines 'epsilon = -d/log_2 p'. The notation should be unified and the sign/convergence statement clarified.
  2. [Section III.A] The sentence 'Indeed, when epsilon_k < 1...' appears to contain a typo: the subscript should likely be 'd' rather than 'k'.
  3. [Section IV.B] The passage 'In Stim, the erasure flag is' ends mid-sentence; the description of how the erasure flag is implemented in Stim should be completed.
  4. [Section V.A] The sentence 'Figure ?? shows the extracted surface code thresholds...' has an unresolved figure reference; presumably the right panel of Figure 8 is intended.
  5. [Section V.B] The sentence 'Again, we can that hybrid-erasure schemes allow...' is missing a verb, likely 'see'.
  6. [Section V.C] The text refers to '(Top, Figure 9)' and '(Bottom, Figure 9)' when describing the panels of Figure 10; the figure references appear to be incorrect.
  7. [Section III.A] The word 'prove' in the summary of results is stronger than the leading-order error-path argument that follows in Sections III.C and III.D. Consider rephrasing to 'derive' or 'argue' to match the level of rigor actually supplied.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the analytical bound, placement heuristic, and circuit-level simulations are self-contained and independently cross-checked; self-citations are background only.

full rationale

I examined the derivation chain for Section III's code-capacity bound, the placement heuristic, and the circuit-level evaluation. Equation (2) is derived from a repetition-code logical-error calculation (Section III-B) and a union bound over lattice-traversing paths (Section III-D); the only inputs are d, f_e, p, and the combinatorial path count, and the bound explicitly reduces to the standard d-qubit and all-erasure edge cases. The optimized placement P* is derived prior to simulation from path-frequency and row/column interception arguments (Section III-C and Section VI) and then independently tested against circuit-level Stim/PyMatching simulations in Figure 15, so the validation is not fitting the same quantity. The deff and threshold extractions in Section IV-C are standard curve fits used to summarize simulation data, and Section V-C's large-system projections are labeled as extrapolations with an analytical lower bound (Eq. 2) and an empirical upper bound, not as new predictions drawn from the claim itself. The self-citations ([30], [31]) occur only in the Introduction as background on chiplet/defect motivations and are not load-bearing for the QEC performance claims. Section IV.A and Section IV.D explicitly state the perfect-erasure-check and fully-heralded assumptions as limitations; acknowledging unmodeled hardware imperfections is a correctness or robustness caveat, not a circular step. No derivation step was found that reduces by construction to its own input or to a self-citation.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

The central results rest on an idealized noise model, including perfect erasure checks and fully heralded errors, plus hand-picked cost and error ratios that the paper flags in Section IV.D. No new physical entities are introduced; the hybrid architecture is a configuration choice, not a new force or particle.

free parameters (2)
  • Noise model error-rate ratios = standard single-qubit gate p/10; dual-rail init/readout 2p; dual-rail single-qubit gate p; erasure check p
    Chosen by hand in Table I; the paper states in Section IV.D that results are sensitive to these ratios and that different ratios contract the hybrid-advantage regions.
  • Transmon cost per dual-rail erasure qubit = 3
    Assumed three-transmon implementation from reference [15]; Section IV.D notes a cavity-readout variant would lower the cost to 2 and change the transmon-budget comparisons.
assumptions (4)
  • domain assumption Erasure checks are perfect: no false positive or false negative detection events.
    Invoked in Section IV.A after Table I; the decoder graph modifications in Section IV.B rely on clean erasure flags.
  • domain assumption Every error on an erasure qubit is a heralded erasure; failed gates produce an erasure flag plus a uniformly random Pauli replacement.
    Section IV.B error model; Section IV.D acknowledges unheralded Pauli errors exist in reality.
  • domain assumption In code-capacity analysis, syndrome extraction is perfect and only minimum-length lattice-traversing paths contribute at leading order.
    Section III.C: 'We will only include minimum-length paths in our analysis, since we are most interested in leading-order effects.'
  • domain assumption A two-qubit gate between a dual-rail erasure qubit and a standard transmon exists with error rate p, and a gate error simultaneously erases the dual-rail and fully depolarizes the standard qubit.
    Section IV.A: 'We assume that such a gate would also have error rate p...'

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Pith. "Pith review of Erasure Minesweeper: exploring hybrid-erasure surface code architectures for efficient quantum error correction." pith.science (2026). https://pith.science/paper/NKGRKGI7

@misc{pith2026250500066,
  author       = {Pith},
  title        = {Pith review of: Erasure Minesweeper: exploring hybrid-erasure surface code architectures for efficient quantum error correction},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/NKGRKGI7}},
  note         = {Machine review of arXiv:2505.00066}
}
abstract

Dual-rail erasure qubits can substantially improve the efficiency of quantum error correction, allowing lower error rates to be achieved with fewer qubits, but each erasure qubit requires $3\times$ more transmons to implement compared to standard qubits. In this work, we introduce a hybrid-erasure architecture for surface code error correction where a carefully chosen subset of qubits is designated as erasure qubits while the rest remain standard. Through code-capacity analysis and circuit-level simulations, we show that a hybrid-erasure architecture can boost the performance of the surface code -- much like how a game of Minesweeper becomes easier once a few squares are revealed -- while using fewer resources than a full-erasure architecture. We study strategies for the allocation and placement of erasure qubits through analysis and simulations. We then use the hybrid-erasure architecture to explore the trade-offs between per-qubit cost and key logical performance metrics such as threshold and effective distance in surface code error correction. Our results show that the strategic introduction of dual-rail erasure qubits in a transmon architecture can enhance the logical performance of surface codes for a fixed transmon budget, particularly for near-term-relevant transmon counts and logical error rates.

Figures

Figures reproduced from arXiv: 2505.00066 by the authors.

Figure 1
Figure 1. Viewing a hybrid-erasure architecture as a game of Minesweeper. [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. A d = 7 rotated surface code patch, consisting of d 2 = 49 data qubits (black) and d 2 − 1 = 48 ancilla qubits (white) in a degree-four planar grid. X and Z stabilizers are represented by light and dark plaquettes, indicating weight-two or weight-four parity checks. The X¯ and Z¯ logical operators are highlighted in light and dark blue lines at the boundary. In the “Erasure Minesweeper” game of [PITH_FULL_IMAGE:fig… view at source ↗
Figure 3
Figure 3. Decoding an example set of errors (a) in the surface code. (b) Syndrome information available in a standard, erasure-free surface code. (c) Decoder [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (11 more)
Figure 4
Figure 4. Figure 4: Examples of hybrid-erasure architecture. (a) [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]
Figure 6
Figure 6. Figure 6: The fraction of error strings (X or Z) that contain each physical qubit in a d = 7 surface code. polynomial time, and is often known as the number of unique ways a king can cross a n × m chessboard [45]. We can interpret logical errors on a surface code in a dynamic vi…
Figure 7
Figure 7. Figure 7: Logical memory performance of surface code of varying distance [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]
Figure 8
Figure 8. Figure 8: Error suppression characteristics for hybrid erasure architectures [PITH_FULL_IMAGE:figures/full_fig_p007_8.png]
Figure 9
Figure 9. Figure 9: Achievable logical error rate for hybrid-erasure surface codes as [PITH_FULL_IMAGE:figures/full_fig_p008_9.png]
Figure 10
Figure 10. Figure 10: Scaling of costs in Figure [PITH_FULL_IMAGE:figures/full_fig_p008_10.png]
Figure 11
Figure 11. Figure 11: Effect of spatial placement of erasure qubits in a [PITH_FULL_IMAGE:figures/full_fig_p009_11.png]
Figure 12
Figure 12. Figure 12: Placing erasure qubits in a way that intercepts as many traversing [PITH_FULL_IMAGE:figures/full_fig_p010_12.png]
Figure 13
Figure 13. Figure 13: Placing lines of erasure qubits in different orientations has a small [PITH_FULL_IMAGE:figures/full_fig_p010_13.png]
Figure 14
Figure 14. Figure 14: Gains in effective distance are slightly higher when lines of erasures d [PITH_FULL_IMAGE:figures/full_fig_p010_14.png]
Figure 15
Figure 15. Figure 15: Comparing code-capacity model from Section [PITH_FULL_IMAGE:figures/full_fig_p011_15.png]

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Pith tools

Reviewed August 16, 2026 · model on record in the stance chip above.