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REVIEW 4 major objections 5 minor 18 references

Scalable Asynchronous Single Flux Quantum Up-Down Counter using Josephson Trapping Lines and {\alpha}-Cells

T0 review · 4 major / 5 minor · reviewed 2026-08-15 · deepseek-v4-flash

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Pith's one-line read This paper claims that a clockless SFQ up-down counter built from Josephson trapping lines and alpha-SPL cells correctly increments, decrements, and reads over a [-4, +4] state range at 4 GHz in circuit-level simulation.

desk verdict A genuinely new asynchronous SFQ counter cell with credible nominal simulations, but the read mechanism rests on an unquantified timing race and 'robust' outruns the evidence. read the letter →

arxiv 2505.04069 v1 pith:3VLNIPN5 submitted 2025-05-07 cond-mat.supr-con

Mustafa Altay Karamuftuoglu , Beyza Zeynep Ucpinar , Sasan Razmkhah , Massoud Pedram This is my paper · ORCID
classification cond-mat.supr-con
keywords singlefluxquantumSFQlogicasynchronouscounterup-downJosephsontrappinglinepersistentcurrentstoragesuperconductingelectronicscryogenicdigital
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper proposes an asynchronous, clockless up-down counter for single-flux-quantum (SFQ) superconducting logic. The central claim is that the counter, built from Josephson Trapping Lines and alpha-SPL cells, correctly executes increment, decrement, and read operations over the state range -4 to +4, including transitions that a plain state circuit cannot express on its own. The design matters because it removes the clocked storage elements normally used to hold counts and replaces them with persistent circulating currents that need no clock to remain stored. If the claim holds, superconducting digital systems gain a compact, scalable, event-driven counting primitive for qubit control, spiking neural networks, and cryogenic sensor readout.

What carries the argument

The load-bearing object is the Josephson Trapping Line (JTrL): a Josephson transmission line in which one SQUID loop has enlarged inductance so an incoming SFQ pulse settles into a persistent circulating current instead of propagating onward. That trapped current is the stored bit; a later pulse on the same side passes through unhindered, while a pulse from the opposite side annihilates the stored current and clears the cell. Around this cell, the paper assembles alpha-SPL lines (a splitter plus two alpha-cells) that route SFQ pulses bidirectionally with fan-out, an upper JTrL bank for negative states and a lower bank for positive states, and a control unit whose state reader performs a read by applying Inc and Dec simultaneously and whose state updater emits modified Inc and Dec signals when the bare state circuit would stay silent.

What would settle it

Apply simultaneous Inc and Dec while the count is +1 or -1 and sweep their relative arrival times, or run Monte Carlo variation of junction and inductor parameters; if any allowed skew makes Dec arrive after Inc, or makes the read produce the wrong count, the central functional claim fails.

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Extended reading notes

Core claim

The paper's discovery is a storage and counting mechanism: a Josephson Trapping Line (JTrL) is a Josephson transmission line whose storage SQUID loop has enlarged inductance, so the first SFQ pulse entering from the trapping side is captured as a persistent circulating current while subsequent pulses pass through, and a pulse entering from the opposite side annihilates that stored current and clears the cell. Wired together with alpha-SPL cells that propagate pulses bidirectionally and provide fan-out, banks of JTrLs form a state circuit whose trapped-pulse count is the counter value. The paper reports SPICE-level simulation of the complete architecture across the full [-4, +4] range at an operating frequency of 4 GHz, with a control unit supplying the increment, decrement, and read behavior the raw state circuit cannot produce by itself.

Load-bearing premise

The load-bearing premise is that during a read, the Dec pulse always reaches the storage cell before the Inc pulse; the paper supports this only by saying the structure is symmetric, without quantifying a timing margin or simulating parameter variations.

Editorial extensions

If this is right

  • An SFQ counter can hold its state without any clock tree, removing clock distribution area and power from superconducting digital layouts.
  • The counter range can be widened by appending more JTrLs and alpha-SPL cells, so the design offers a modular path to larger counters.
  • The persistent trapped current gives a storage element that can keep a count between operations without refreshing, effectively nonvolatile within cryogenic operation.
  • The read operation produces no output at state zero and is declared unpredictable there, so surrounding control logic must know that zero is not a readable state.
  • Because the full counter was verified only in circuit simulation at 4 GHz, the concrete claim to check in hardware is correct bidirectional behavior across the full state range.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • An implication left implicit is that the read-while-zero restriction forces surrounding control logic to track whether the counter is at zero separately, since applying a read at zero is explicitly described as unpredictable.
  • A testable extension would be a Monte Carlo sweep of junction critical currents and inductances: the Dec-before-Inc ordering that the read depends on is justified only by symmetry and has no stated timing margin.
  • If the JTrL's trapped current remains stable over long idle periods, the same cell could serve as a building block for nonvolatile SFQ memory or asynchronous state machines beyond counters.
  • At larger counter ranges the path through more alpha-SPLs and JTrLs may desynchronize the simultaneous Inc and Dec read pulses, so the scalability claim becomes a timing question rather than a wiring question.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper proposes an asynchronous (clockless) up-down counter for single-flux quantum (SFQ) logic, using Josephson Trapping Lines (JTrLs) for persistent pulse storage and α-cells with splitters (α-SPL) for bidirectional, multi-fanout pulse propagation. The design includes a state circuit with four JTrLs for positive and four for negative states (range [-4,+4]) and a control unit composed of a state reader and a state updater. The state reader implements read by simultaneously applying Inc and Dec pulses, while the state updater handles output generation for Inc-in-negative and Dec-in-positive states. The correctness claims are supported by JSIM circuit simulations of the JTrL, α-SPL, state circuit, state reader, state updater, and the full counter at a nominal 4 GHz operating frequency. The authors further claim that the architecture scales to larger ranges by adding more JTrLs and α-SPLs.

Significance. If the reported functionality is robust, the counter offers a useful clockless building block for superconducting digital systems, avoiding clock distribution overhead and enabling persistent state storage. The paper's strengths are that it provides direct JSIM simulations of the integrated state circuit and control unit, that the trapping mechanism is experimentally grounded in the JTrL cell, and that the simulation does not rely on parameter fitting to match an external target. The architectural integration of α-SPL cells to achieve bidirectional propagation is also noteworthy. However, the validation is limited to nominal parameter values; no bias margins, process-variation analysis, or temperature sensitivity studies are reported, and the read operation relies on an unquantified timing skew. The scalability claim is currently supported only by a single 3-bit demonstration. These limitations prevent the current evidence from fully supporting the paper's 'robust' and 'scalable' claims, though the core idea remains plausible and worth revising.

major comments (4)
  1. [II-B1] The read operation is built on an unquantified timing assumption. The manuscript states 'Due to the symmetrical structure of the state circuit, Dec reaches the cell earlier than Inc,' but provides no delay calculation, SPICE-measured delay, or margin sweep for this skew. The ordering is load-bearing: in state +4, if the Inc pulse arrives before the Dec pulse, the Inc pulse cannot be trapped and may be directed to the sink, corrupting the read output and the stored state; an analogous failure exists at -4. Please provide a quantitative timing analysis and bias/process margin sweeps for the read path, or explicitly restrict the claimed operating conditions.
  2. [III] The central claim of robustness is not supported by the reported simulations. All waveforms in Figs. 8-13 are nominal-parameter runs; the paper reports no bias margins, no Monte Carlo or process-variation analysis, and no sensitivity study of JTrL and α-SPL parameters. Bias margins are a standard validation requirement for SFQ circuits. Without them, the abstract's phrase 'robust bidirectional functionality' overstates what has been demonstrated; please add margin sweeps or temper the wording to 'functionality at nominal parameter values.'
  3. [IV] The scalability claim that additional JTrLs and α-SPLs extend the counter range without increasing complexity is not substantiated by simulation. Only the 3-bit [-4,+4] configuration is demonstrated. Since the state-reader timing race depends on path delays that change as JTrLs are added, the extension to larger ranges requires either a simulation at a larger width (e.g., 4-bit) or a timing/load analysis showing that the Dec-before-Inc ordering is preserved. Please provide one such demonstration or restate the scalability claim as a design proposal rather than a validated property.
  4. [II-B2] The state updater is simulated only for the negative-state/Inc case (Fig. 12); the claimed symmetric behavior for Dec in positive states is not shown. Moreover, no exhaustive state-transition table or formal verification is provided for the full 9-state counter under all input combinations (Inc, Dec, Read). Given the abstract's statement that the control unit 'guarantees correct output behavior across all valid state transitions,' please either provide complete functional coverage results or replace the word 'guarantees' with a weaker claim consistent with the demonstrated evidence.
minor comments (5)
  1. [II-B1] The read-at-zero restriction is a functional limitation: the text states 'The read signal should not be applied when the state is zero.' This should be disclosed in the abstract, since the design otherwise claims general read support.
  2. [II-A] The caption of Fig. 4 says 'half of the JTLs and intermediate delay elements have been removed from the diagrams'; the text should specify which elements are omitted and how they are accounted for in simulation, otherwise the reader cannot reproduce the circuit.
  3. [II-A] The α-SPL behavior is described verbally ('A pulse from Input 1 generates output pulses at Output 1 and 3'), but the circuit-level parameters (bias currents, junction critical currents, inductances) for the α-SPL and for the state reader/updater cells are not reported, making the simulations difficult to reproduce. Please include a full parameter table.
  4. [III] The description of the JTrL simulation in Fig. 8 is contradictory: the text says 'the first Input 2 pulse is observed at Output 2' and later 'The Input 2 pulse at 275 ps does not produce an output.' Please clarify which pulses are trapped and which propagate, and whether these refer to the same or different Input 2 pulses.
  5. [References] There are typographical issues in the reference list, e.g., 'Sympsoium' in reference [2]; the JSIM citation [13] also appears to refer to a specific readout application rather than the JSIM simulator itself, so the reference should be corrected or expanded.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the counter's behavior is verified by direct JSIM simulation of the disclosed circuits; the only self-citation (Soma cell) is not load-bearing because the integrated circuit is simulated in this paper.

full rationale

The paper's central claim—that the proposed JTrL-based asynchronous up-down counter correctly increments, decrements, and reads over the [-4, +4] range at 4 GHz—is established by direct circuit-level SPICE/JSIM simulation of each disclosed block: the JTrL (Fig. 8), the α-SPL (Fig. 9), the state circuit (Fig. 10), the state reader (Fig. 11), the state updater (Fig. 12), and the full integrated counter (Fig. 13). These simulations are not fitted to a target output and no quantity is defined in terms of the claimed result. The JTrL trapping behavior is specified by concrete circuit parameters (L1=0.93 pH, L2=7.64 pH, etc.) and then observed in simulation, rather than being assumed from a self-cited result. The only self-citation is the Soma cell described in [14], but that cell is embedded in the state updater, and the state updater itself is simulated in this paper, so the citation is not the load-bearing evidence for the counter's correctness. The state-reader timing assumption that 'Due to the symmetrical structure of the state circuit, Dec reaches the cell earlier than Inc' is an unquantified timing-margin robustness concern, not a circular dependency; the read behavior is explicitly simulated and the paper also acknowledges the zero-state race ('the outcome depends on which pulse triggers a junction first at the intermediate point of the data path'). Because every load-bearing functional claim is backed by in-paper simulations of the proposed circuits, no step reduces to its own input by construction or to a self-citation chain. Score 0.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

The design depends on hand-picked Josephson junction and bias parameters, on the correctness of prior alpha-cell and Soma cells, and on the accuracy of the JSIM simulator. No new physical entities are postulated; the JTrL is a circuit configuration, not a new force or particle.

free parameters (4)
  • JTrL storage inductance L2 = 7.64 pH
    Sets the inductance of the storage SQUID loop that traps a circulating current.
  • JTrL bias currents IB1-IB3 = 237.64, 125.25, 182.35 µA
    Bias levels chosen so that a single pulse is trapped without triggering J2 and later released by an opposite pulse.
  • JTrL junction critical currents J1-J3 = 303, 318, 282 µA
    Junction thresholds chosen by hand to achieve trap and propagate behavior.
  • Remaining circuit parameters (alpha-SPL, control unit) = not reported
    Parameters for the rest of the counter are not given, so a key part of the design is a free choice for any replicator.
assumptions (4)
  • domain assumption Resistively shunted junction (RSJ) model accurately describes the Josephson junctions in the simulations
    The JSIM simulations rely on this standard model for SFQ circuit behavior.
  • domain assumption The alpha-cell, as introduced in the authors' prior work, has the described bidirectional propagation and fan-in behavior
    The counter design relies on the alpha-cell and alpha-SPL operating as claimed in Ref. [14] and [16].
  • domain assumption The Soma cell, cited from Ref. [14], functions as a threshold gate with a threshold of two SFQ pulses
    The state updater depends on this threshold behavior.
  • domain assumption JSIM simulator is a faithful SPICE-level model for SFQ circuits at 4 GHz
    All functional claims rest on the accuracy of the simulator.

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Cite this review

Pith. "Pith review of Scalable Asynchronous Single Flux Quantum Up-Down Counter using Josephson Trapping Lines and {\alpha}-Cells." pith.science (2026). https://pith.science/paper/3VLNIPN5

@misc{pith2026250504069,
  author       = {Pith},
  title        = {Pith review of: Scalable Asynchronous Single Flux Quantum Up-Down Counter using Josephson Trapping Lines and \alpha-Cells},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/3VLNIPN5}},
  note         = {Machine review of arXiv:2505.04069}
}
abstract

We present a scalable, clockless up-down counter architecture implemented using single-flux quantum (SFQ) logic to enable efficient state management in superconductor digital systems. The proposed design eliminates the reliance on clocked storage elements by introducing the Josephson Trapping Line (JTrL). This bidirectional pulse-trapping structure enables persistent, non-volatile state storage without clocking. The counter integrates $\upalpha$-cells with a splitter (SPL) element to make bidirectional data propagation possible and support multi-fanout connectivity. The design supports increment, decrement, and read operations and includes a control unit that guarantees correct output behavior across all valid state transitions. Circuit-level simulations based on SPICE models demonstrate robust bidirectional functionality across a 3-bit state range [-4 to +4] at an operating frequency of 4 GHz. The proposed counter offers a modular and scalable solution suitable for integration into larger superconducting systems targeting quantum computing, neuromorphic processing, and cryogenic sensing applications.

Figures

Figures reproduced from arXiv: 2505.04069 by the authors.

Figure 1
Figure 1. Integration of up-down counter. The up-down counter [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Josephson Trapping Line with unidirectional trap. The [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Bidirectional multifanout line with α-SPL. To build the state circuit, we combine α-SPLs with JTrL cells to control the storage and removal of pulses. Inc pulses arriving at the circuit eliminate any previously stored Dec pulses. If no Dec pulses are present in the upper JTrLs, the Inc pulses move to the lower JTrLs, where they get trapped. Before trapping occurs in JTrL, α-SPL generates an output where each pulse r… view at source ↗
Figures from the paper (8 more)
Figure 5
Figure 5. Figure 5: Control Unit. 1) State Reader: Since the state circuit only operates with Inc and Dec, introducing an additional read signal would in￾crease the complexity of the design. Therefore, simultaneously applying Inc and Dec signals can perform the read operation. If the syst…
Figure 4
Figure 4. Figure 4: State Circuit. Pulses from Inc neutralize any trapped [PITH_FULL_IMAGE:figures/full_fig_p003_4.png]
Figure 7
Figure 7. Figure 7: State Updater. Since the up-down module cannot [PITH_FULL_IMAGE:figures/full_fig_p004_7.png]
Figure 8
Figure 8. Figure 8: Simulation of the JTrL, showing unidirectional trap [PITH_FULL_IMAGE:figures/full_fig_p004_8.png]
Figure 10
Figure 10. Figure 10: State circuit simulation for a [-4, +4] range, showing [PITH_FULL_IMAGE:figures/full_fig_p005_10.png]
Figure 9
Figure 9. Figure 9: Simulation of the α-SPL cell, demonstrating bidirec￾tional propagation and multifanout behavior. A pulse from Input 1 reaches Outputs 1 and 3, while a pulse from Input 2 propagates only to Output 2, validating directional control and fanout functionality. The output pu…
Figure 12
Figure 12. Figure 12: Simulation of the state updater circuit. The circuit [PITH_FULL_IMAGE:figures/full_fig_p006_12.png]
Figure 13
Figure 13. Figure 13: Full design simulation of the asynchronous up-down [PITH_FULL_IMAGE:figures/full_fig_p006_13.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

18 extracted references · 18 canonical work pages

  1. [13]

    Current Resolution of a Single-Flux-Quantum Readout Circuit Based on Current- to-Time Conversion Toward a Flux Qubit System,

    S. Nakamura, H. Numabe, A. Bozbey, and A. Fujimaki, “Current Resolution of a Single-Flux-Quantum Readout Circuit Based on Current- to-Time Conversion Toward a Flux Qubit System,” Applied Supercon- ductivity, IEEE Transactions on , vol. 19, p. 973–976, 2009

    work page 2009

  2. [1]

    Long and fast up/down counters,

    M. R. Stan, A. F. Tenca, and M. D. Ercegovac, “Long and fast up/down counters,” IEEE Transactions on Computers, vol. 47, no. 7, pp. 722–735, 1998

    work page 1998

  3. [2]

    Synchronous up/down counter with clock period independent of counter size,

    M. Stan, “Synchronous up/down counter with clock period independent of counter size,” in Proceedings 13th IEEE Sympsoium on Computer Arithmetic, 1997, pp. 274–281

    work page 1997

  4. [3]

    Design of up-down counter as SAR logic for high speed SAR ADC used in health care system,

    C. S. Ragit and S. Badjate, “Design of up-down counter as SAR logic for high speed SAR ADC used in health care system,” in 2016 Conference on Advances in Signal Processing (CASP) , 2016, pp. 465–468

    work page 2016

  5. [4]

    A high-speed and low-power up/down counter in 0.18-mum CMOS technology,

    T. Zhang and Q. Hu, “A high-speed and low-power up/down counter in 0.18-mum CMOS technology,” in 2012 International Conference on Wireless Communications and Signal Processing (WCSP) , 2012, pp. 1– 3

    work page 2012

  6. [5]

    Design of memristor- based up-down counter using material implication logic,

    A. Chakraborty, A. Dhara, and H. Rahaman, “Design of memristor- based up-down counter using material implication logic,” in 2016 International Conference on Advances in Computing, Communications and Informatics (ICACCI) , 2016, pp. 269–274. 7

    work page 2016

  7. [6]

    Hybrid Memristor-CMOS Based Up-Down Counter Design,

    K. Alammari, A. Ahmadi, and M. Ahmadi, “Hybrid Memristor-CMOS Based Up-Down Counter Design,” in 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) , 2020, pp. 1–4

    work page 2020

  8. [7]

    RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems,

    K. Likharev and V . Semenov, “RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems,” IEEE Transactions on Applied Superconductivity , vol. 1, p. 3–28, 1991

    work page 1991

Show all 18 references
  1. [8]

    Superconducting Quantum Electronics,

    S. Razmkhah and P. Febvre, “Superconducting Quantum Electronics,” in Beyond-CMOS, 2023, ch. 8, pp. 295–391

    2023

  2. [9]

    Energy-Efficient Single Flux Quantum Technology,

    O. A. Mukhanov, “Energy-Efficient Single Flux Quantum Technology,” IEEE Transactions on Applied Superconductivity , vol. 21, no. 3, pp. 760–769, 2011

    2011

  3. [10]

    Design of Digital DROS With SFQ Up/Down Counter for Wide Dynamic Operation Range,

    H. Myoren, Y . Kimimoto, K. Terui, and T. Taino, “Design of Digital DROS With SFQ Up/Down Counter for Wide Dynamic Operation Range,” IEEE Transactions on Applied Superconductivity , vol. 21, no. 3, pp. 387–390, 2011

    2011

  4. [11]

    Implementation of High-Speed Single Flux-Quantum Up/Down Counter for the Neural ComputationUs- ing Stochastic Logic,

    T. Onomi, T. Kondo, and K. Nakajima, “Implementation of High-Speed Single Flux-Quantum Up/Down Counter for the Neural ComputationUs- ing Stochastic Logic,” IEEE Transactions on Applied Superconductivity , vol. 19, no. 3, pp. 626–629, 2009

    2009

  5. [12]

    Binary Counters Using Adi- abatic Quantum-Flux-Parametron Logic,

    T. Yamae, N. Takeuchi, and N. Yoshikawa, “Binary Counters Using Adi- abatic Quantum-Flux-Parametron Logic,” IEEE Transactions on Applied Superconductivity, vol. 31, no. 2, pp. 1–5, 2021

    2021

  6. [14]

    JJ-Soma: Toward a spiking neuromorphic processor architecture,

    M. A. Karamuftuoglu, A. Bozbey, and S. Razmkhah, “JJ-Soma: Toward a spiking neuromorphic processor architecture,” IEEE Transactions on Applied Superconductivity, vol. 33, no. 8, pp. 1–7, 2023

    2023

  7. [15]

    Sfq control circuits for josephson junction qubits,

    V . Semenov and D. Averin, “Sfq control circuits for josephson junction qubits,” IEEE Transactions on Applied Superconductivity , vol. 13, no. 2, pp. 960–965, 2003

    2003

  8. [16]

    Unsupervised SFQ-Based Spiking Neural Network,

    M. A. Karamuftuoglu, B. Z. Ucpinar, S. Razmkhah, M. Kamal, and M. Pedram, “Unsupervised SFQ-Based Spiking Neural Network,” in IEEE Transactions on Applied Superconductivity , vol. 34, no. 3, 2024, pp. 1–8

    2024

  9. [17]

    Synchronous SFQ Address Encoder for Superconductor Detector Arrays,

    A. Bozbey, E. C. Aydo ˘gan, K. ¨Us ¸enmez, S. Razmkhah, M. Tanaka, and A. Fujimaki, “Synchronous SFQ Address Encoder for Superconductor Detector Arrays,” IEEE Transactions on Applied Superconductivity , vol. 31, no. 4, pp. 1–5, 2021

    2021

  10. [18]

    Experimental digital squid with integrated feedback circuit,

    U. Fath, R. Hundhausen, T. Fregin, P. Gerigk, W. Eschner, A. Schindler, and F. Uhlmann, “Experimental digital squid with integrated feedback circuit,” IEEE transactions on applied superconductivity , vol. 7, no. 2, pp. 2747–2751, 1997

    1997

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