VO$_2$ oscillator circuits optimized for ultrafast, 100 MHz-range operation

Alberto Piqu\'e; Andr\'as B\"ukkfejes; Andr\'as Halbritter; Heungsoo Kim; J\'anos Volk; Jeurg Leuthold; L\'aszl\'o P\'osa; Mikl\'os Csontos; Sebastian Werner Schmid; T\'imea N\'ora T\"or\"ok

REVIEW 3 major objections 4 minor 1 cited by

VO$_2$ oscillator circuits optimized for ultrafast, 100 MHz-range operation

T0 review · 3 major / 4 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read The paper demonstrates a record 167 MHz oscillation in passive VO2 relaxation oscillators and argues that the reset relaxation time under oscillator bias sets a practical speed ceiling near this value.

desk verdict Credible 167 MHz record for passive VO2 oscillators, but the paired speed-ceiling claim lacks transition-time data at the record frequency — a fixable gap, not a fatal flaw. read the letter →

arxiv 2506.01139 v1 pith:VYELSX3J submitted 2025-06-01 cond-mat.mes-hall cond-mat.mtrl-sci

Zsigmond Pollner , Tímea Nóra Török , László Pósa , Miklós Csontos , Sebastian Werner Schmid , Zoltán Balogh , András Bükkfejes , Heungsoo Kim

show 4 more authors

Alberto Piqué Jeurg Leuthold János Volk András Halbritter

This is my paper

classification cond-mat.mes-hallcond-mat.mtrl-sci

keywords vanadiumdioxideMottmemristorrelaxationoscillatorresistiveswitchingoscillatingneuralnetworktransmissionlinecircuitultrafastoscillation

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that nanoscale VO2 memristors can be made to oscillate at 167 MHz, more than an order of magnitude beyond the previous 9 MHz record, by shrinking the switching region, cutting stray capacitance, and arranging the oscillator as a transmission-line circuit with the series resistor close to the device. It further claims that this is close to the practical ceiling: under oscillator bias the device voltage is clamped between Vset and Vreset, so the ultrafast 15 ps set and 600 ps reset seen with optimized single pulses cannot be reached. Instead, set and reset take nanoseconds, with reset relaxation the limiting factor, and the fastest oscillation is set by matching the circuit-induced voltage build-up delay to this internal relaxation time. If true, VO2-based oscillating neural networks can operate in the 100 MHz range with simple passive circuits, but GHz operation is not realistic in this design.

What carries the argument

The central object is the nanoscale VO2 Mott memristor with a V-shaped electrode that confines switching to a roughly 30 nm spot, combined with an in-line oscillator circuit in which the memristor and series resistor are connected by a short transmission line of length d and the transmitted current is measured through a matched 50 Ω load. The argument is carried by an analytic voltage build-up time $\tau_{0\to V_{\mathrm{set}}} = \frac{d}{v}\left[\frac{\ln\left(1 - V_{\mathrm{set}}\frac{1-R_M R_S}{2V_0 T_S R_M}\right)}{\ln(R_M R_S)} - 1\right]$ that counts how many back-and-forth reflections between the resistor and the memristor are needed to reach Vset, and by pulsed resistance-relaxation measurements that show how set and reset times lengthen under oscillator-like conditions. LTspice hysteresis-switch and Simulink relaxation models reproduce the observed frequencies and the failure of ultra-short-distance oscillators without a parallel capacitor.

What would settle it

Feed an oscillating VO2 circuit with a drive waveform that adds a short overvoltage at each set phase and record the oscillation frequency and the device voltage with a probe of at least 100 GHz bandwidth; a sustained oscillation well above 167 MHz, or set and reset edges remaining sub-nanosecond under oscillation bias, would falsify the claimed ceiling.

Watch

Extended reading notes

Core claim

The paper demonstrates a record 167 MHz self-oscillation in a passive VO2 relaxation oscillator and argues that this sits near a fundamental practical ceiling for this class of circuits. With the switching confined to an ultrasmall, roughly 30 nm wide active region and the circuit rebuilt as a transmission-line arrangement where only the distance d between the series resistor and the memristor limits the signal build-up, the authors show that oscillation frequencies above 100 MHz are achievable and that the normalized frequency f·d/v collapses onto a single curve across distances. The limiting step is identified by pulsed experiments that mimic oscillator bias: because the device voltage is clamped near Vset and Vreset during oscillation, set and reset times stretch from the 15 ps and 600 ps of optimized single pulses to nanoseconds, with reset relaxation consistently the slower process. The conclusion is that an oscillation significantly faster than the demonstrated 167 MHz is not realistic for this passive-circuit design.

Load-bearing premise

During oscillation the voltage on the VO2 element is assumed to stay clamped between Vset and Vreset, so switching never sees the large overvoltages that produce 15 ps set and 600 ps reset times in optimized single pulses; if that clamp fails or is engineered away, the speed ceiling would move.

Editorial extensions

If this is right

Oscillation frequency becomes tunable by the memristor-to-resistor distance d and the parallel capacitance C, with the normalized product f·d/v collapsing to a single curve across geometries.
The previous 9 MHz ceiling for VO2 oscillators is not fundamental; optimized devices routinely reach 75–100 MHz and have reached 167 MHz.
Since reset relaxation under oscillator bias is the slow step, circuit designs that shorten or assist the reset transition while preserving oscillation would be the route to higher frequencies.
Integrated on-chip resistors with very short d fail to oscillate without a parallel capacitor, because the voltage passes through the switching window too quickly for the memristor to complete set and reset.
VO2-based oscillating neural networks stand to operate at roughly 100 MHz, about an order of magnitude faster than previously demonstrated, which would speed up and make more energy-efficient the computations they perform.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

If overshoot beyond Vset could be engineered deliberately during oscillation, for instance with pulsed drive or a nonlinear load, set times might approach the 15 ps single-pulse value, potentially lifting the ceiling toward GHz.
The paper's conclusion concerns purely passive series-resistor circuits; active or hybrid circuits, such as the transistor-assisted TaOx benchmark the authors compare against, are a separate route that may bypass the reset-limited ceiling.
The normalized f·d/v scaling suggests a testable design rule: choose d so that the voltage build-up delay roughly matches the internal relaxation time, and the optimum should shift with temperature or device stoichiometry that changes Vset and Vreset.
For oscillating neural networks, the coupling network itself must be transmission-line compatible, otherwise the interconnect reflections that were removed inside the oscillator will reappear at the network level.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

The thing to know up front: the 167 MHz record is real, directly measured, and the best part of the paper. The softer spot is the universal ceiling claim attached to it. The paper concludes that oscillation significantly faster than 167 MHz is not realistic, but the load-bearing transition times come from a 103 MHz trace, not from the record trace. That gap is genuine, and it is a gap in the ceiling claim, not in the record.

What is new: a passive VO2 relaxation oscillator at 167 MHz, over an order of magnitude above the previous 9 MHz best; the in-line transmission-line geometry that enables it; the f·d/v scaling collapse across different memristor-to-resistor distances and its breakdown above 75 MHz; and the identification of oscillator-condition reset relaxation as the practical speed limiter. The 100 GHz real-time traces (1.2 ns rise, 3.4 ns fall) are strong evidence for the relaxation-limited picture, and the d = 1.5 mm failure with recovery via a 1 pF capacitor is a nice confirmation of their stabilization argument. The authors are honest with the reader: they flag device-to-device variation and full relaxation dynamics as out of scope, report the scaling breakdown instead of hiding it, and let Eq. 3 be tested against experiment, failing honestly at high frequencies.

Soft spots, in proportion. The Simulink model uses hand-picked tau_set = 600 ps and tau_reset = 1.5 ns to reproduce the 167 MHz trace; that makes it a fit, not an independent bound. The pulse experiments give far longer times (up to 54 ns), but the authors correctly note those overestimate oscillator-condition switching. So the only direct oscillator-condition numbers are from the 103 MHz trace. The stress-test suggestion is exactly right: the 167 MHz trace was recorded at 10 GS/s, and its falling edges contain the reset time at the record condition. Report that number. If it is around 3 ns, the ceiling claim holds up; if it is sub-nanosecond, the ceiling is higher. The voltage-clamp argument itself is explicit and reasonable, so the missing measurement, not the assumption, is what needs attention. Also minor: no error bars or statistics on the frequencies, and no released simulation code or data.

This paper is for anyone working on VO2 or Mott-oxide oscillators, neuromorphic hardware, or the speed limits of relaxation oscillators. It deserves a serious referee: the record and the scaling data merit publication, and the ceiling claim is worth arguing about, but it needs either softening or direct support at the record frequency.

Recommendation: send it to peer review, with a request for transition-time analysis of the 167 MHz trace and more statistics.

Referee Report

3 major / 4 minor

Summary. The paper reports VO2 relaxation oscillators with a record 167 MHz oscillation frequency, more than an order of magnitude above the previous 9 MHz state of the art. The improvement is attributed to three factors: nanoscale devices with a confined active region and minimized stray capacitance, a transmission-line-based circuit layout with an in-line series resistor and matched 50-ohm readout, and the identification of internal VO2 relaxation times as the practical speed limit. The authors support these claims with LTspice transmission-line simulations, an analytic voltage build-up formula, measurements of oscillation frequency versus drive voltage and memristor-to-resistor distance, pulsed switching experiments, and Matlab Simulink models with finite set/reset time constants. They conclude that under oscillator bias the reset relaxation time is the key limiting factor and that oscillations significantly faster than 167 MHz are not realistic.

Significance. If the central claim holds, this is a substantial advance for VO2-based oscillatory neural networks: it moves individual passive VO2 oscillators from the few-MHz range into the 100 MHz range and identifies a concrete physical bottleneck, namely the reset relaxation time under oscillator conditions rather than circuit capacitance or wiring alone. The paper's strengths include direct time-domain observation of the 167 MHz oscillation, an independent 100 GHz-bandwidth measurement showing 1.2 ns rise and 3.4 ns fall times at 103 MHz, the collapse of the measured frequency data under v/d normalization, and an analytic voltage build-up formula that is tested against experiment. The authors are also honest about the limits of the simplest model: the scaling fails above about 75 MHz, and the 167 MHz record is stated to rely on a fine interplay of device parameters that is not reproduced in every circuit.

major comments (3)

[Investigation of the internal relaxation time-scales (Fig. 6)] The speed-ceiling claim—that an oscillation 'significantly faster than the fastest 167 MHz oscillation achieved is not realistic'—rests on a 3.4 ns reset fall time measured on a 103 MHz oscillation, not on the 167 MHz record trace. The 167 MHz trace in Fig. 1d was recorded at 10 GS/s and contains reset edges; reporting their 10–90% fall time (and the corresponding set rise time) would directly test whether the ceiling is supported at the actual maximum frequency. If those edges are much faster than 3.4 ns, the ceiling would need to be revised upward; if they are approximately 3 ns, the claim is strongly supported. This is the most load-bearing missing datum in the paper.
[Supporting Information S3] The Simulink model reproduces 173 MHz using tau_set = 600 ps and tau_reset = 1.5 ns, but these constants are not independently measured; they are selected so that the simulated frequency matches the experimentally observed 167 MHz. The model is therefore a consistency check, not an independent bound on the maximum oscillation frequency. To make the model load-bearing for the ceiling claim, the authors should extract tau_set and tau_reset from the 100 GHz oscillator trace, or from voltage-resolved measurements during oscillation, rather than from frequency matching alone.
[Investigation of the internal relaxation time-scales, first paragraph] The premise that oscillator-condition voltages are clamped between Vset and Vreset is stated rather than verified: in the in-line circuit only the current is measured, and the authors themselves allow that 'minor overshoots or undershoots are possible.' Since the pulse experiments show that switching times depend strongly on overvoltage and undervoltage, the claim that oscillator set/reset times are order(s) of magnitude longer than the 15 ps/600 ps pulsed values would be considerably stronger with a direct high-bandwidth measurement of Vbias, or an indirect reconstruction from the current trace, during oscillation.

minor comments (4)

[Fig. 1d] The 167 MHz oscillation is difficult to read from the compressed multi-period trace; a zoomed single-period view with marked rise and fall times would help the reader verify the claimed frequency.
[Eq. 3] The typeset form of Eq. (3) appears to have an unbalanced parenthesis in the argument of the logarithm; please check the mathematical expression.
[Fig. 5] The notation tA1, tO1, tP1 and related labels is introduced in the text but not all of these times are marked in the figure panels; adding direct labels to the arrows would improve readability.
[Methods, meander resistor fabrication] The estimate '150 µm·18/2 + 150 µm = 1.5 mm' for the effective memristor-to-resistor distance is not self-evident; a sentence explaining the factor 18/2 would make the calculation transparent.

Circularity Check

1 steps flagged · score 4.0 of 10

The Simulink 'reproduction' of the 167 MHz record is achieved by hand-picked switch time constants, but the central speed-ceiling claim still rests on direct 100 GHz and pulsed measurements - partial, localized circularity.

fitted input called prediction [Supporting Information Section S3 (Eq. 5), cited in main text, 'Experimental observation of ultrafast oscillations']
"These simulations reproduce the experimentally reached 167 MHz frequency maximum (see Section S3 of the Supporting Information) ... The oscillation frequency of the resulting simulated waveform yields fSim. = 173 MHz, assuming reasonable relaxation timescales of tau_set = 600 ps and tau_reset = 1.5 ns. The simulation resembles the oscillation of the fastest experiment with fExp. = 167 MHz."

In the relaxation-oscillator model of SI S3, the simulated period is a direct function of the chosen time constants, and tau_set/tau_reset are not measured at the 167 MHz operating point but merely 'assumed reasonable'. The same model family in SI S5, using the directly measured oscillator-condition reset fall time tau_reset = 3.4 ns (Fig. 6), yields 89 MHz at d = 6.5 mm; SI S3 obtains 173 MHz only after lowering tau_reset to 1.5 ns. Thus the simulated frequency lands on the record value by construction, and the main text cites that match ('reproduce the experimentally reached 167 MHz frequency maximum') as support. The qualitative stabilization mechanism of S4/S5 is independent theory, but the quantitative reproduction is a parameter-tuned fit, not a prediction.

full rationale

One localized circular step was found: the Simulink model of SI S3 matches the 167 MHz record only because 'reasonable' tau_set/tau_reset values were selected to land on it, with tau_reset = 1.5 ns set below the directly measured 3.4 ns oscillator-condition fall time (Fig. 6); the match is then presented in the main text as if it reproduced and supported the experimental maximum. This is a fitted input presented as reproduction. The central speed-ceiling claim, however, does not reduce to this fit. It rests on (i) the stated voltage-clamp argument for oscillator operation, (ii) direct pulsed measurements (Fig. 5) showing multi-ns set/reset times under near-threshold driving, and (iii) a direct 100 GHz-bandwidth oscillator measurement (Fig. 6) giving 1.2 ns rise and 3.4 ns fall times. The Fig. 6 data are new measurements, not quoted results; the authors' prior Ref. 31 is cited only as a contrast baseline (15 ps set, 600 ps reset under optimized single pulses) and as the shared measurement setup, which is not load-bearing for the ceiling. Eq. 3 (voltage build-up) is derived from telegrapher's equations and is tested against experiment with an honestly reported failure of the f.d/v scaling above 75 MHz; no uniqueness theorem or cosh-type ansatz is imported from the authors' prior work. Two support gaps are flagged as correctness risk rather than circularity: the only direct oscillator-condition transition-time measurement is at 103 MHz, not at the 167 MHz record, and the paper does not report the reset fall time of the 167 MHz trace itself, even though it was digitized at 10 GS/s. If that fall time were much shorter than 3.4 ns, the conclusion that 'an oscillation significantly faster than the fastest 167 MHz oscillation achieved is not realistic' would be weakened. Overall: partial, localized circularity in one supporting simulation; central claim retains independent experimental content.

Assumptions & free parameters 2 free parameters · 5 assumptions · 0 invented entities

No new physical entities (particles, forces, dimensions) are introduced. The paper's new elements are an in-line circuit topology, a V-shaped device geometry, and a heuristic rate-equation device model, which are design and modeling choices rather than invented entities.

free parameters (2)

tau_set (Simulink set time constant) = 600 ps (SI S3; also S5)
Chosen by hand in the Matlab Simulink model to reproduce the experimental 167 MHz waveform (S3) and the 89/72 MHz scenarios (S5); not a directly measured input.
tau_reset (Simulink reset time constant) = 1.5 ns (S3), 3.4 ns (S5), 5 ns (S4)
Adjusted between simulations to match the measured traces; together with tau_set it fixes the simulated oscillation frequency and tail shapes.

assumptions (5)

domain assumption The VO2 memristor is purely resistive over the relevant band (ZM = RM), with stray capacitance below 55 fF (2 fF in prior work).
Invoked after Eq. (2) to justify frequency-independent transmission coefficients and the transmission-line model; supported by the pulse-shape test in SI S1, but not measured at the actual oscillation frequencies for all devices.
domain assumption During oscillation the memristor voltage is confined between Vreset and Vset, with only minor overshoot.
Stated in 'Investigation of the internal relaxation time-scales'; load-bearing for the conclusion that switching in oscillators is far slower than optimized pulsed switching, and hence for the ~100 MHz ceiling.
domain assumption Cables and the resistor-to-memristor segment behave as lossless 50 ohm transmission lines with propagation speed 2e8 m/s.
Used for the LTspice models and the analytic voltage build-up formula Eq. (3); standard for the described coax/PCB geometry, but resistor junction parasitics are not modeled.
ad hoc to paper The reset and set dynamics of VO2 follow the heuristic rate equations dRM/dt = (RM,OFF-RM)/tau_reset * ((Vset-Vbias)/DeltaV)^2 and analog for set (Eq. 6).
A phenomenological model introduced in SI S5 to reproduce the disappearance of oscillation at d=1.5 mm and its recovery with C=1 pF; the quadratic voltage dependence is chosen, not derived.
domain assumption Pulsed driving with a readout offset adequately mimics oscillator voltage conditions.
Assumed in 'Investigation of the internal relaxation time-scales' to measure set/reset times that represent oscillator operation; the paper notes that a comprehensive dynamics analysis is beyond scope.

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Cite this review

Pith. "Pith review of VO$_2$ oscillator circuits optimized for ultrafast, 100 MHz-range operation." pith.science (2026). https://pith.science/paper/VYELSX3J

@misc{pith2026250601139,
  author       = {Pith},
  title        = {Pith review of: VO$_2$ oscillator circuits optimized for ultrafast, 100 MHz-range operation},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/VYELSX3J}},
  note         = {Machine review of arXiv:2506.01139}
}

abstract

Oscillating neural networks are promising candidates for a new computational paradigm, where complex optimization problems are solved by physics itself through the synchronization of coupled oscillating circuits. Nanoscale VO$_2$ Mott memristors are particularly promising building blocks for such oscillating neural networks. Until now, however, not only the maximum frequency of VO$_2$ oscillating neural networks, but also the maximum frequency of individual VO$_2$ oscillators has been severely limited, which has restricted their efficient and energy-saving use. In this paper, we show how the oscillating frequency can be increased by more than an order of magnitude into the 100 MHz range by optimizing the sample layout and circuit layout. In addition, the physical limiting factors of the oscillation frequencies are studied by investigating the switching dynamics. To this end, we investigate how much the set and reset times slow down under oscillator conditions compared to the fastest switching achieved with single dedicated pulses. These results pave the way towards the realization of ultra-fast and energy-efficient VO$_2$-based oscillating neural networks.

Figures

Figures reproduced from arXiv: 2506.01139 by the authors.

**Figure 2.** FIG. 2 [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗

**Figure 3.** f) correspond to a ∆t = d/v ≈ 32 ps signal propagation time from the resistor to the memristor, where v ≈ 2 · 108 m/s is the signal propagation speed in the transmission lines. This short propagation time seemingly contradicts the two orders of magnitude larger period time of the oscillation at ≈ 100 MHz frequency. This V0 V0RS V0TSRMTS V0 V0RS Resistor Resistor Memristor Memristor V0TSRM V0TSRM V0TS V0TSRMRS V0T… view at source ↗

Figures from the paper (4 more)

**Figure 4.** Figure 4: e). We explain this as follows. Either a properly chosen parallel capacitor, or a properly distant resistor in series helps to slow-down the voltage variation in the circuit, such that after reaching the set (reset voltage) these voltage levels are kept for a while to …

**Figure 5.** Figure 5: FIG. 5 [PITH_FULL_IMAGE:figures/full_fig_p007_5.png]

**Figure 6.** Figure 6: FIG. 6 [PITH_FULL_IMAGE:figures/full_fig_p008_6.png]

**Figure 7.** Figure 7: FIG. 7 [PITH_FULL_IMAGE:figures/full_fig_p010_7.png]

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Forward citations

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Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.

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