Pith. sign in

REVIEW 3 major objections 4 minor 43 references

Dual-Material Double-Gate Source-Pocket Tunnel Field Effect Transistor with Homogeneous Gate Dielectric: Computational Analysis of Structural and Material Parameters for Enhanced Performance

T0 review · 3 major / 4 minor · reviewed 2026-08-07 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

Pith's one-line read This computational paper claims a silicon tunnel FET with a source pocket, dual-metal gates, and a single HfO2 dielectric reaches 6.29 mV/decade and a 2.05e13 ON/OFF ratio.

desk verdict A competent TCAD parameter study of a pocketed dual-material TFET; the architecture is genuinely new in combination, but the headline ION/IOFF/SS numbers are uncalibrated and should be read as model projections, not measured facts. read the letter →

arxiv 2506.08556 v1 pith:CYQYI6IZ submitted 2025-06-10 physics.app-ph

Ramisa Fariha , Saikat Das , Labiba Tanjil Nida , Abeer Khan , Md Tashfiq Bin Kashem This is my paper
classification physics.app-ph
keywords Tunnelfield-effecttransistorSource-pocketTFETDual-materialgateDouble-gateHomogeneousdielectricBand-to-bandtunnelingTCADsimulationLow-powerelectronics
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish that a silicon tunnel field-effect transistor can carry the performance benefits of source-pocket and dual-metal-gate engineering on a single uniform HfO2 gate insulator, avoiding the harder fabrication of hetero-dielectric stacks. In 2-D TCAD simulation, the pocket alone raises ON current by $6.7\times$ and lowers subthreshold swing by $1.7\times$, and dual-material gates add another 45% ON current and 59% ON/OFF ratio improvement. With optimized doping and work functions, the device is reported at $V_{GS}=V_{DS}=1$ V to reach $I_{ON}=3.16\times10^{-4}$ A/$\mu$m, $I_{OFF}=1.54\times10^{-17}$ A/$\mu$m, $I_{ON}/I_{OFF}=2.05\times10^{13}$, and subthreshold swing of 6.29 mV/decade. If those numbers hold, a single-dielectric silicon TFET could serve ultra-low-power logic. Because the evidence is entirely simulation, the quantitative claim rests on the accuracy of the tunneling model.

What carries the argument

The load-bearing mechanism is band-to-band tunneling at the source-pocket junction, shaped by the p-n-p-n layer sequence and a dual-material gate. The n+ pocket creates a local minimum in the conduction band and a steep lateral electric field that thins the tunneling barrier; the tunneling gate metal with lower work function $\Phi_{M1}$ helps pull the pocket bands down, while the auxiliary gate metal with higher $\Phi_{M2}$ suppresses drain-side ambipolar tunneling. The homogeneous HfO2 dielectric's role is strong gate coupling without a stacked insulator, so the pocket and dual-metal advantages are obtained in a simpler, more manufacturable stack. The reported numbers come from 2-D TCAD simulation using a nonlocal band-to-band tunneling model with bandgap narrowing.

What would settle it

Fabricate the exact optimized structure — 12 nm Si film, 2 nm HfO2, $N_{source}=5\times10^{20}$ cm$^{-3}$, $N_{drain}=10^{18}$ cm$^{-3}$, $\Phi_{M1}=4.3$ eV, $\Phi_{M2}=4.5$ eV, 6 nm pocket at $3\times10^{19}$ cm$^{-3}$ — and measure the transfer curve at $V_{DS}=1$ V. If the measured subthreshold swing exceeds 60 mV/decade, or the ON/OFF ratio is more than an order of magnitude below $2.05\times10^{13}$, the paper's central quantitative claim is contradicted.

Watch

Extended reading notes

Core claim

The central claim is that a p-n-p-n silicon TFET — a heavily n-doped pocket between the p+ source and the p channel — combined with two gate metals sharing one homogeneous HfO2 dielectric, narrows the band-to-band tunneling barrier enough to outperform pocket-free dual-material TFETs and single-material pocket TFETs. After optimizing $N_{source}=5\times10^{20}$ cm$^{-3}$, $N_{drain}=10^{18}$ cm$^{-3}$, $\Phi_{M1}=4.3$ eV, and $\Phi_{M2}=4.5$ eV, the authors report at $V_{GS}=V_{DS}=1$ V a 3 nm tunneling barrier width, a peak junction electric field of 3.75 MV/cm, $I_{ON}=3.16\times10^{-4}$ A/$\mu$m, $I_{OFF}=1.54\times10^{-17}$ A/$\mu$m, $I_{ON}/I_{OFF}=2.05\times10^{13}$, and a subthreshold swing of 6.29 mV/decade. The paper presents this as matching or exceeding the performance previously achieved with hetero-dielectric pocket DMDG TFETs while simplifying the gate stack.

Load-bearing premise

The load-bearing assumption is that the nonlocal band-to-band tunneling and bandgap-narrowing models in the TCAD simulator are quantitatively accurate for this 12 nm silicon film without calibration against any fabricated device; every reported current and swing value inherits that assumption.

Editorial extensions

If this is right

  • If the simulation is right, a silicon DMDG-SP TFET with one HfO2 insulator can match or beat hetero-dielectric pocket TFETs, removing a fabrication and interface-reliability hurdle.
  • Pocket doping and length act as direct tuning knobs for tunneling current: in the studied range, heavier doping and longer pockets raise ON current and improve ON/OFF ratio while lowering subthreshold swing.
  • Work-function engineering can substitute for dielectric engineering: the dual-material gate adds 45% ON current and 59% ON/OFF ratio on top of the pocket gain.
  • The optimized 1 V device would switch with sub-10 mV/decade slope, a regime that would permit very low supply voltages in ultra-low-power digital circuits.
  • The parameter sweep provides concrete design rules: high source doping, light short drain, high-k gate dielectric, larger tunneling-to-auxiliary gate length ratio, and a longer pocket within the tested window.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Editorial inference: the exact $I_{OFF}$ and subthreshold-swing values are likely optimistic because the TCAD tunneling model is uncalibrated, but the comparative gains (pocket vs no pocket, dual vs single gate) are more robust than the absolute numbers.
  • Editorial inference: the same pocket plus dual-metal plus single-dielectric recipe transfers naturally to heterojunction or two-dimensional TFETs, where band-edge alignment makes tunneling even more sensitive to the local electric field.
  • Editorial inference: the decisive next test is a fabricated 12 nm silicon film device, or a full-band quantum transport calculation, to see whether a sub-60 mV/decade swing survives without model calibration.
Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The paper proposes a silicon homojunction dual-material double-gate tunnel field-effect transistor with a source pocket and a homogeneous HfO2 gate dielectric (DMDG-SP TFET), and investigates it via 2-D Silvaco Atlas TCAD simulations. It reports that the pocket increases ON current by 6.7x and improves subthreshold swing by 1.7x relative to a pocket-less device, and that dual-material gates increase ON current by 45% and ON/OFF ratio by 59% relative to single-material gates. After sweeping gate metal work functions, gate lengths, dielectric constants, channel/source/drain doping, and pocket parameters, the authors claim an optimized device with ION = 3.16e-4 A/um, IOFF = 1.54e-17 A/um, ION/IOFF = 2.05e13, and SS = 6.29 mV/decade at VGS = VDS = 1 V (Sec. 4.4.9).

Significance. If the quantitative results are reliable, the work demonstrates a manufacturable-simpler TFET design that matches or exceeds more complex hetero-dielectric pocket TFETs, which would be of interest for low-power logic. The systematic parameter sweeps (Secs. 4.4.1-4.4.8) also provide useful design guidance for the source-pocket DMDG architecture. The comparative claims about the benefits of the pocket and of dual-material gates are internally consistent and follow expected TFET physics. However, the paper's headline numbers are entirely dependent on uncalibrated TCAD models, and no sensitivity or mesh-convergence evidence is provided, so the central quantitative claim is not yet established.

major comments (3)
  1. [Sec. 3 and Sec. 4.4.9] The simulation methodology (Sec. 3) lists the nonlocal band-to-band tunneling model and the bandgap narrowing model but does not specify the tunneling effective mass, Kane or WKB prefactor parameters, BGN parameters, or mesh density. These inputs set the WKB exponent that determines ION and IOFF. The headline values in Sec. 4.4.9 (ION = 3.16e-4 A/um, IOFF = 1.54e-17 A/um, SS = 6.29 mV/dec) are therefore not reproducible from the paper alone, and the claimed quantitative superiority over hetero-dielectric pocket TFETs is not established. The authors should report the exact model parameters, provide a mesh convergence study, and show sensitivity of ION and IOFF to the tunneling mass and BGN parameters.
  2. [Sec. 4.4.9 and Fig. 11] The paper does not define how IOFF and SS are computed. IOFF is presumably taken at VGS = 0 V and VDS = 1 V, but this is never stated, and the value 1.54e-17 A/um would be meaningless without a precise bias definition. Similarly, SS in a TFET varies with VGS; the single value 6.29 mV/dec is reported without stating whether it is a point slope at a particular VGS, an average over a specific range, or an extrapolation. Without these definitions, comparison with published TFET data is ambiguous. The authors should state the extraction procedure for all figures of merit in the methodology.
  3. [Sec. 2 and Sec. 4.4.9] The simulations assume uniform doping profiles with ideal abrupt junctions (Sec. 2, Table 1) and include no interface traps, band tails, or series resistance. At the optimized source doping of 5e20 cm-3, BGN strongly modifies the band alignment, and the absence of calibration against any measured Si TFET transfer curve means that the absolute current values, especially IOFF and SS, are model-dependent to a degree that is not quantified. The qualitative design trends are likely robust, but the quantitative claims require either comparison with experimental TFET data or at least a sensitivity analysis demonstrating that the reported values do not hinge on default Atlas parameters.
minor comments (4)
  1. [Fig. 6 and Fig. 7 captions] The captions for Figs. 6 and 7 each contain a duplicated label: the first '(b)' appears twice, and the right-hand panel in each figure should be labeled '(d)' to match the subplot references in the text.
  2. [Sec. 4.4.1] The sentence 'Metals such as Aluminum, Titanium, Chromium, Tungsten, and Silver represent work functions in the 4.3–4.7 eV range' is imprecise; each metal has a specific work function, and the text should clarify which work-function value corresponds to which metal rather than implying a range.
  3. [Abstract and Sec. 4.2] The claim '1.7x lower subthreshold swing' is ambiguous because subthreshold swing is not a multiplicative quantity that is naturally described as 'lower by a factor'; the authors should define whether this is the ratio of SS values or a percentage reduction.
  4. [Fig. 11] In Fig. 11 the color contours are labeled in mA for ION and in units of 1e-17 A for IOFF, whereas the text reports ION in A/um and IOFF in A/um; the figure units and the text units should be made consistent, and the current normalization to device width should be stated.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the reported device metrics are direct TCAD simulation outputs from fixed physical models and parameter sweeps, not fitted or self-referential predictions.

full rationale

The paper's derivation chain is a Silvaco Atlas TCAD simulation study. Section 3 specifies the physical models used (nonlocal band-to-band tunneling, bandgap narrowing, field- and doping-dependent mobility, SRH and Auger recombination). Section 4 reports simulated energy bands, electric fields, transfer characteristics, and parametric sweeps. Section 4.4.9 simply runs one more simulation at the parameter values that the preceding sweeps identified as favorable, and reports the resulting ION, IOFF, ION/IOFF, and subthreshold swing. These numbers are outputs of the simulator for a fixed input deck; they are not fitted to match target values, nor is any equation defined in terms of the reported result. Choosing the parameter set that gives the best simulated figure of merit is standard engineering optimization, not circular reasoning. There is also no load-bearing self-citation: the cited prior works are external TFET studies and do not supply a conclusion that this paper merely re-imports. The uncalibrated nature of the Atlas default models is a real validation and correctness risk, but it is not a circularity of the kind defined here, because the model assumptions do not include the reported headline metrics. Therefore the circularity score is 0.

Assumptions & free parameters 5 free parameters · 5 assumptions · 0 invented entities

The central performance numbers rest on four hand-chosen optimized parameters (source/drain doping, two gate work functions, pocket doping/length) plus the simulator's uncalibrated physics models. These are not free in a derivation sense because they are explicit design variables, but they are chosen by the authors from the same simulations that produce the final claims, so the reported optimum is partly a product of the search. No new entities are introduced.

free parameters (5)
  • Optimized source doping Nsource = 5e20 cm^-3
    Selected in Section 4.4.4 and 4.4.9 as the best of the swept values; directly sets the tunneling barrier width and ON current.
  • Optimized drain doping Ndrain = 1e18 cm^-3
    Selected to reduce ambipolar OFF current while retaining ON current (Sections 4.4.4 and 4.4.9).
  • Tunneling gate work function Phi_M1 = 4.3 eV
    Chosen in Sections 4.4.1 and 4.4.9 as the value giving lowest threshold voltage and highest ON current.
  • Auxiliary gate work function Phi_M2 = 4.5 eV
    Chosen in Sections 4.4.1 and 4.4.9 as a compromise between ON current and ambipolar suppression.
  • Pocket doping and length Npocket, Lpocket = 3e19 cm^-3, 6 nm
    Chosen in Section 4.4.8; higher value and length gave lower SS and higher ION/IOFF within the swept range.
assumptions (5)
  • domain assumption Silvaco Atlas nonlocal BTB tunneling model quantitatively predicts Si TFET currents without calibration.
    Invoked in Section 3; all ION/IOFF/SS values depend on it.
  • domain assumption Uniform doping and abrupt source/pocket/channel/drain junctions.
    Table 1 states uniform doping; no diffusion gradients are modeled.
  • domain assumption Bandgap narrowing, SRH, Auger, and field/impurity-dependent mobility models with simulator defaults are appropriate.
    Listed in Section 3; no parameter values or calibration are given.
  • domain assumption 2-D simulation is sufficient to represent the device.
    Figure 1(b) shows the 2-D structure used; 3-D and fringing effects are ignored.
  • domain assumption Ideal metal/HfO2 interfaces with no traps or fixed charge.
    No interface trap model is included, although the introduction cites reliability issues with hetero-dielectrics.

how reviews work

0 comments
Cite this review

Pith. "Pith review of Dual-Material Double-Gate Source-Pocket Tunnel Field Effect Transistor with Homogeneous Gate Dielectric: Computational Analysis of Structural and Material Parameters for Enhanced Performance." pith.science (2026). https://pith.science/paper/CYQYI6IZ

@misc{pith2026250608556,
  author       = {Pith},
  title        = {Pith review of: Dual-Material Double-Gate Source-Pocket Tunnel Field Effect Transistor with Homogeneous Gate Dielectric: Computational Analysis of Structural and Material Parameters for Enhanced Performance},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/CYQYI6IZ}},
  note         = {Machine review of arXiv:2506.08556}
}
read the original abstract

Dual-material double-gate tunnel field effect transistor (DMDG TFET) is a promising candidate for low-power, high-speed electronics due to enhanced electrostatic control and superior switching characteristics. Integrating a pocket region between the source and channel-doped oppositely to the source-further improves tunneling efficiency by modulating the electric field at the tunneling junction. This combined architecture, termed the DMDG source-pocket TFET (DMDG-SP TFET), achieves higher ON current and reduced subthreshold swing compared to conventional TFETs. Previous DMDG-SP TFET designs primarily use heterogeneous gate dielectrics, composed of two stacked insulators to enhance gate control and tunneling modulation. However, such hetero gate dielectrics increase fabrication complexity and may degrade device reliability due to material incompatibility. This work proposes a silicon-based DMDG-SP TFET employing a homogenous gate dielectric, investigated through Silvaco Atlas-based 2-D TCAD simulations, aiming to simplify fabrication without compromising performance. Presence of the pocket results in 6.7x higher ON current and 1.7x lower subthreshold swing compared to pocket-less devices. Dual-material gates boost ON current by 45% and improve the ON/OFF current ratio by 59% compared to single-material gates in pocket-based devices. Detailed simulations analyze effects of gate metal work functions and lengths, gate dielectric constant, and doping densities and lengths of all regions. The optimized device achieves an ON current of 3.16*10^-4 A/um, OFF current of 1.54*10^-17 A/um, ON/OFF ratio of 2.05*10^13, and subthreshold slope of 6.29 mV/decade. These findings offer critical insights for designing manufacturable, high-performance homojunction silicon-based DMDG-SP TFETs with homogeneous gate dielectrics for next-generation low-power integrated circuits.

Discussion (0). Sign in to comment.

Reference graph

Works this paper leans on

43 extracted references · 41 canonical work pages

  1. [1]

    Mater Sci Semicond Process 134:106002

    Ratnesh RK, Goel A, Kaushik G, et al (2021) Advancement and challenges in MOSFET scaling. Mater Sci Semicond Process 134:106002. https://doi.org/10.1016/j.mssp.2021.106002

    work page arXiv 2021

  2. [2]

    J Semicond 41:061401

    Mendiratta N, Tripathi SL (2020) A review on performance comparison of advanced MOSFET structures below 45 nm technology node. J Semicond 41:061401. https://doi.org/10.1088/1674-4926/41/6/061401

    work page doi:10.1088/1674-4926/41/6/061401 2020

  3. [3]

    Nanoelectronics : Physics, Materials and Devices

    Equbal MS, Sahay S (2023) Scaling the MOSFET: detrimental short channel effects and mitigation techniques. Nanoelectronics : Physics, Materials and Devices. Elsevier, pp 11 –37

    work page 2023

  4. [4]

    Int J Appl Eng Res 11:4922- -4929

    Turkane, S, and Kureshi A (2016) Review of Tunnel Field Effect Transistor. Int J Appl Eng Res 11:4922- -4929

    work page 2016

  5. [5]

    Jpn J Appl Phys 31:L455

    Baba T (1992) Proposal for Surface Tunnel Transistors. Jpn J Appl Phys 31:L455

    work page 1992

  6. [6]

    Silicon 15:2385–2405

    Hannah Blessy P, Shenbagavalli A, Arun Samuel TS (2023) A Comprehensive Review on the Single Gate, Double Gate, Tri -Gate, and Heterojunction Tunnel FET for Future Generation Devices. Silicon 15:2385–2405. https://doi.org/10.1007/s12633-022-02189-2

    work page doi:10.1007/s12633-022-02189-2 2023

  7. [7]

    2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

    Visciarelli M, Gnani E, Gnudi A, et al (2017) Investigation of the combined effect of traps and strain on optimized n - and p -type TFETs. 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS). IEEE, pp 13–16

    work page 2017

  8. [8]

    IEEE Trans Electron Devices 59:292 –301

    Kao K-H, Verhulst AS, Vandenberghe WG, et al (2012) Direct and Indirect Band -to-Band Tunneling in Germanium-Based TFETs. IEEE Trans Electron Devices 59:292 –301. https://doi.org/10.1109/TED.2011.2175228

    work page arXiv 2012

Show all 43 references
  1. [9]

    2010 IEEE International Conference of Electron Devices and Solid- State Circuits (EDSSC)

    Shengxi Huang, Ximeng Guan, Jinyu Zhang, et al (2010) Design of complementary GAA-NW tunneling- FETs of axial Si-Ge heterostructure. 2010 IEEE International Conference of Electron Devices and Solid- State Circuits (EDSSC). IEEE, pp 1–4

    2010

  2. [10]

    Wiley Encyclopedia of Electrical and Electronics Engineering

    Verreck D, Groeseneken G, Verhulst A (2016) The Tunnel Field‐ Effect Transistor. Wiley Encyclopedia of Electrical and Electronics Engineering. Wiley, pp 1–24

    2016

  3. [11]

    IEEE Electron Device Lett 35:1170–1172

    Abdi DB, Kumar MJ (2014) In -Built N+ Pocket p -n-p-n Tunnel Field-Effect Transistor. IEEE Electron Device Lett 35:1170–1172. https://doi.org/10.1109/LED.2014.2362926

    2014

  4. [12]

    IEEE Trans Electron Devices 54:1725–1733

    Boucart K, Ionescu AM (2007) Double -Gate Tunnel FET With High - Gate Diel ectric. IEEE Trans Electron Devices 54:1725–1733. https://doi.org/10.1109/TED.2007.899389

    2007

  5. [13]

    J Integr Circuits Syst 19:1–12

    Pavan Kumar C, Sivani K (2024) Design of a Double Gate Tunneling Field Effect Transistor (DG-TFET) and Performance Analysis. J Integr Circuits Syst 19:1–12. https://doi.org/10.29292/jics.v19i2.762

    2024 doi

  6. [14]

    Appl Phys A 125:353

    Kumar S, Singh KS, Nigam K, et al (2019) Dual-material dual-oxide double-gate TFET for improvement in DC characteristics, analog/RF and linearity performance. Appl Phys A 125:353. https://doi.org/10.1007/s00339-019-2650-5

    2019 doi

  7. [15]

    IEEE Trans Electron Devices 58:404–410

    Saurabh S, Kumar MJ (2011) Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field -Effect Transistor. IEEE Trans Electron Devices 58:404–410. https://doi.org/10.1109/TED.2010.2093142

    2011

  8. [16]

    Silicon 14:10101–10113

    Kavi KK, Tripathi S, Mishra RA, Kumar S (2022) Design, Simulation, and Work Function Trade for DC and Analog/RF Performance Enhancement in Dual Material Hetero Dielectric Double Gate Tunnel FET. Silicon 14:10101–10113. https://doi.org/10.1007/s12633-022-01765-w

    2022 doi

  9. [17]

    Int J Numer Model Electron Networks, Devices Fields 30:

    Noor SL, Safa S, Khan MZR (2017) A si licon‐based dual‐material double‐gate tunnel field‐effect transistor with optimized performance. Int J Numer Model Electron Networks, Devices Fields 30:. https://doi.org/10.1002/jnm.2220

    2017 doi

  10. [18]

    J Comput Electron 15:763–769

    Noor SL, Safa S, Khan MZR (2016) Dual -material double -gate tunne l FET: gate threshold voltage modeling and extraction. J Comput Electron 15:763–769. https://doi.org/10.1007/s10825-016-0816-3

    2016 doi

  11. [19]

    2015 IEEE International WIE Co nference on Electrical and Computer Engineering (WIECON -ECE)

    Noor SL, Safa S, Khan MZR (2015) Two -dimensional model of Dual Met al double gate tunnel FETs. 2015 IEEE International WIE Co nference on Electrical and Computer Engineering (WIECON -ECE). IEEE, pp 70–73

    2015

  12. [20]

    IEEE Trans Electron Devices 61:2515 –

    Guin S, Chattopadhyay A, Karmakar A, Mallik A (2014) Impact of a Pocket Doping on the Device Performance of a Schottky Tunneling Field -Effect Transistor. IEEE Trans Electron Devices 61:2515 –

    2014

  13. [21]

    IEEE Trans Electron Devices 60:212 8–2134

    Verreck D, Verhulst AS, Kao K-H, et al (2013) Quantum Mechanical Performance Predictions of p-n-i-n Versus Pocketed Line Tunnel Field -Effect Transistors. IEEE Trans Electron Devices 60:212 8–2134. https://doi.org/10.1109/TED.2013.2260237

    2013

  14. [22]

    IEEE Trans Electron Devices 55:1013 –1019

    Nagavarapu V, Jhaveri R, Woo JCS (2008) The Tunnel Source (PNPN) n -MOSFET: A Novel High Performance Transistor. IEEE Trans Electron Devices 55:1013 –1019. https://doi.org/10.1109/TED.2008.916711

    2008

  15. [23]

    Curr Appl Phys 12:673 –677

    Cho S, Kang IM (2012) Design optimization of tunneling field-effect transistor based on silicon nanowire PNPN structure and its radio frequency characteristics. Curr Appl Phys 12:673 –677. https://doi.org/10.1016/j.cap.2011.10.003

    2012 doi

  16. [24]

    IEEE Trans Electron Devices 58:80 –86

    Jhaveri R, Nagavarapu V, Woo JCS (2011) Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field -Effect Transistor. IEEE Trans Electron Devices 58:80 –86. https://doi.org/10.1109/TED.2010.2089525

    2011

  17. [25]

    IEEE Trans Electron Devices 58:1907 –1913

    Tura A, Zhang Z, Liu P, et al (2011) Vertical Silicon p-n-p-n Tunnel nMOSFET With MBE -Grown Tunneling Junction. IEEE Trans Electron Devices 58:1907 –1913. https://doi.org/10.1109/TED.2011.2148118

    2011

  18. [26]

    IEEE Trans Electron Devices 60:92–96

    Chang H-Y, Adams B, Chien P -Y, et al (2013) Improved Subthreshold and Output Characteristics of Source-Pocket Si Tunnel FET by the Application of Laser Annealing. IEEE Trans Electron Devices 60:92–96. https://doi.org/10.1109/TED.2012.2228006

    2013

  19. [27]

    IEEE Trans Electron Devices 58:2122 –2126

    Cao W, Yao CJ, Jiao GF, et al (2011) Improvement in Reliability of Tunneling Field -Effect Transistor With p -n-i-n Struc ture. IEEE Trans Electron Devices 58:2122 –2126. https://doi.org/10.1109/TED.2011.2144987

    2011

  20. [28]

    Microelectronics J 129:105587

    Rasheed G, Sridevi S (2022) Design and analysis of a dual gate tunnel FET with InGaAs source pockets for improved performance. Microelectronics J 129:105587. https://doi.org/10.1016/j.mejo.2022.105587

    2022

  21. [29]

    Silicon 16:1273 –1282

    Kavi KK, Tripathi S, Mishra RA, Kumar S (2024) Analytical Modeling for Electrical Characteristics of Source Pocket -Based Hetero Dielectric Double -Gate TFETs. Silicon 16:1273 –1282. https://doi.org/10.1007/s12633-023-02754-3

    2024 doi

  22. [30]

    Silicon 14:1593 –

    Priyadarshani KN, Singh S, Naugarhiya A (2022) Dual Metal Double Gate Ge-Pocket TFET (DMG-DG- Ge-Pocket TFET) with Hetero Dielectri c: DC and Analog Performance Projections. Silicon 14:1593 –

    2022

  23. [31]

    2017 14th IEEE India Council International Conference (INDICON)

    Singh PK, Kumar S, Chander S, et al (2017) Impact of Strain on Electrical Characteristic of Double-Gate TFETs with a SiO2/RfO2 Stacked Gate -Oxide Structure. 2017 14th IEEE India Council International Conference (INDICON). IEEE, pp 1–5

    2017

  24. [32]

    IEEE Trans Device Mater Reliab 16:227 –234

    Madan J, Chauj ar R (2016) Interfacial Charge Analysis of Heterogeneous Gate Dielectric -Gate All Around-Tunnel FET for Improved Device Reliability. IEEE Trans Device Mater Reliab 16:227 –234. https://doi.org/10.1109/TDMR.2016.2564448

    2016

  25. [33]

    IEEE Trans Device Mater Reliab 17:245–252

    Venkatesh P, Nigam K, Pandey S, e t al (2017) Impact of Interface Trap Charges on Performance of Electrically Doped Tunnel FET With Heterogeneous Gate Dielectric. IEEE Trans Device Mater Reliab 17:245–252. https://doi.org/10.1109/TDMR.2017.2653620

    2017

  26. [34]

    Silicon 14:3185 –3197

    Jeyanthi JE, Samuel TSA, Geege AS, Vi mala P (2022) A Detailed Roadmap from Single Gate to Heterojunction TFET for Next Generation Devices. Silicon 14:3185 –3197. https://doi.org/10.1007/s12633-021-01148-7

    2022 doi

  27. [35]

    SILVACO Int, Santa Clara, CA, USA

    ATLAS (2019) 2-D Device Simulator. SILVACO Int, Santa Clara, CA, USA

    2019

  28. [36]

    J Sci Technol 53:

    Vinh LT, Chien ND (2015) Effects Of Source Doping Profile On Device Characteristics Of Lateral And Vertical Tunnel Field -Effect Transistors. J Sci Technol 53:. https://doi.org/10.15625/0866 - 708X/53/1/3805

    2015 doi

  29. [37]

    Superlattices Microstruct 102:284–

    Chien ND, Shih C -H (2017) Oxide thickness -dependent effe cts of source doping profile on the performance of single- and double-gate tunnel field-effect transistors. Superlattices Microstruct 102:284–

    2017

  30. [38]

    Microelectron Reliab 55:31–37

    Chien ND, Shih C-H (2015) Short-channel effect and device design of extremely scaled tunnel field-effect transistors. Microelectron Reliab 55:31–37. https://doi.org/10.1016/j.microrel.2014.09.028

    2015 doi

  31. [39]

    Solid State Electron 52:1318–1323

    Boucart K, Ionescu AM (2008) A new definition of threshold voltage in Tunnel FETs. Solid State Electron 52:1318–1323. https://doi.org/10.1016/j.sse.2008.04.003

    2008 doi

  32. [40]

    Micro and Nanostructures 195:207951

    Yadav N, Jadav S, Saini G (2024) Steep subthreshold swing Double - Gate tunnel FET using source pocket engineering: Design guidelines. Micro and Nanostructures 195:207951. https://doi.org/10.1016/j.micrna.2024.207951

    2024

  33. [299]

    https://doi.org/10.1016/j.spmi.2016.12.048

    2016 doi

  34. [1604]

    https://doi.org/10.1007/s12633-021-00955-2

    doi

  35. [2522]

    https://doi.org/10.1109/TED.2014.2325068

    2014

Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.