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REVIEW 4 major objections 6 minor 2 cited by

Multi-FPGA Synchronization and Data Communication for Quantum Control and Measurement

T0 review · 4 major / 6 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read A multi-FPGA clock synchronization and fiber data link makes cross-board quantum feed-forward practical on open-source RFSoC control systems.

desk verdict A credible, useful engineering report on multi-board RFSoC synchronization and data links for QubiC; the demo works, but the headline time-alignment claim is one direct cross-board measurement short of being fully nailed. read the letter →

arxiv 2506.09856 v1 pith:G3P443JC submitted 2025-06-11 quant-ph

Yilun Xu , Abhi D. Rajagopala , Neelay Fruitwala , Gang Huang This is my paper
classification quant-ph
keywords multi-FPGAsynchronizationRFSoCquantumcontrolclockdistributionPrecisionTimeProtocolAurora64B/66Bmid-circuitmeasurementfeed-forward
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Quantum processors with more than about ten qubits outgrow a single FPGA control board, and commercial multi-board control systems are expensive and proprietary. This paper claims to close that gap with an open-source method for synchronizing multiple RFSoC boards so their qubit-control pulses are time-aligned, and for moving readout results between boards over fiber quickly enough for mid-circuit measurement and feed-forward. The authors report 1.8 ps RMS jitter on a 6.50 GHz output, a 16-hour test with clock counters staying at zero offset across three boards, and a cross-board conditional pulse about 1600 ns after a 1 µs readout. If these bench results hold on real chips, academic labs could build large-scale quantum control systems from commodity evaluation boards.

What carries the argument

The load-bearing object is the clock-synchronization chain: a shared 10 MHz reference is distributed on matched-length cables into each board's LMK04828 clock chip, whose nested PLLs run in zero-delay mode with SYSREF as feedback, after which Xilinx multi-tile synchronization aligns DAC/ADC tiles on each board. A separate minimal PTP exchange over copper adjusts the counter offsets between neighboring boards in a ring. Data rides on Aurora 64B/66B at 10.3125 Gbps over SFP fiber, managed by readout and feed-forward finite-state machines that format quantum results into 64-bit frames.

What would settle it

Measure the phase of a continuous 6.5 GHz tone generated simultaneously on two boards against the same reference: if the residual inter-board phase skew exceeds the few-picosecond level implied by the jitter numbers, or drifts beyond the timing tolerance of the qubit controls over a 16-hour run, the central synchronization claim is refuted.

Watch

Extended reading notes

Core claim

The paper's central claim is that a nested dual phase-locked loop configured in zero-delay mode, driven by a shared 10 MHz reference over matched-length cables and corrected by a minimal Precision Time Protocol exchange, makes the RF phase plane of separate boards common, while a 10.3125 Gbps Aurora fiber link carries measurement results between boards with about 450 ns latency. Together these enable time-aligned qubit drive pulses across boards and conditional pulses on one board based on a readout on another, demonstrated with a room-temperature readout emulator using a two-qubit mid-circuit measurement and feed-forward program.

Load-bearing premise

The time-alignment claim assumes that matched-length reference clock cables plus the zero-delay PLL configuration make the 10 MHz clock arrive at every board with equal, deterministic phase, and that the software counter correction aligns the RF phase plane across boards.

Editorial extensions

If this is right

  • Academic labs can assemble multi-board control systems from three ZCU216-class boards without proprietary backplanes or vendor licensing.
  • Mid-circuit measurement and feed-forward, including cross-board conditional operations, complete in about 1.6 µs, comfortably inside tens-of-microseconds qubit coherence times.
  • The ring topology with identical bitstreams per board means adding another board does not require redesigning the synchronization logic.
  • The 64-bit frame format supports results for up to 21 qubits per frame, with frame count and inter-frame delay customizable for larger chips.
  • Because the data link uses standard Aurora and AXI4-Stream, the communication module can interoperate with general-purpose high-speed networking equipment.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The 16-hour zero-counter-offset result validates the counter-alignment loop, but it does not directly bound residual RF phase skew between two boards' outputs; a direct inter-board phase-noise measurement would be the next validation step.
  • The reported 450 ns communication latency likely includes protocol overhead and FIFO crossings; an optimized version might approach the hundreds-of-nanoseconds target needed for tighter feedback loops, such as real-time decoders.
  • Ring-topology offset corrections propagate node-to-node, so error growth with many boards is untested; a star-sync or tree-sync variant might scale better beyond a handful of boards.
  • The bench tests use a room-temperature readout emulator, so the next testable extension is the same mid-circuit measurement and feed-forward circuit on a real superconducting chip with multiple control boards.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. The paper presents a clock synchronization and data-communication framework for multi-FPGA RFSoC-based quantum control, integrated into the open-source QubiC system. Clock synchronization is achieved by distributing a 10 MHz reference over matched-length cables, using zero-delay PLL and multi-tile synchronization on each board, and running a minimal PTP protocol over copper links in a ring topology to align clock counters. Data communication uses the Aurora 64B/66B protocol over four SFP fiber links in a star topology, with readout and feed-forward state machines that broadcast measurement results across boards. The authors report single-output RF jitter of 1.8 ps RMS (10 Hz--100 MHz) and 7.4 ps RMS (0.1 Hz--100 MHz) at 6.50 GHz, a 16-hour test with zero counter offset across boards, and a room-temperature qubit readout emulator demonstration of mid-circuit measurement and conditional feed-forward in which Board 2 emits pulses conditioned on Board 1 measurement results, with an observed start-to-conditional-pulse interval of about 1600 ns. The paper claims to provide the first open-source solution for multi-FPGA time synchronization and data communication for quantum control.

Significance. If the central synchronization claim holds, the work is a valuable open-source building block for scaling superconducting-qubit control beyond a single RFSoC board. The manuscript has concrete strengths: it reports measured jitter numbers, a 16-hour stability test, a working end-to-end feed-forward demonstration on emulated readout, and detailed engineering choices (Aurora configuration, GPIO-based minimal PTP, ring topology, star data network) that are directly useful to practitioners. The integration with QubiC also makes the contribution easier to adopt. However, the load-bearing claim that RF pulses on different boards are time-aligned and 'perfectly phase-synchronized' is supported only indirectly: the jitter measurement is per-board, and the 16-hour test is a digital counter comparison. A direct cross-board RF phase or skew measurement is absent, so the central contribution is plausible but not yet demonstrated at the level the paper claims.

major comments (4)
  1. [Section V, Experiments] The central claim of time-aligned RF pulses across multiple boards is not directly measured. The reported 1.8 ps and 7.4 ps RMS jitter values are measured on individual output signals with a signal source analyzer; they characterize single-output noise, not the relative phase between two boards' RF outputs. The 16-hour counter-offset test is a digital counter comparison, and synchronized counters do not by themselves guarantee synchronized DAC sample-clock phases unless the PLL/SYSREF alignment is also verified. Please add a direct cross-board measurement, for example capturing the RF outputs of two boards on a high-bandwidth oscilloscope and reporting the measured channel-to-channel phase or time skew (with cable delays calibrated out), or report the measured SYSREF alignment and PLL lock phase across boards. Without such a measurement, the phrase 'perfectly phase-synchronized' in Section III is stronger than the evidence in Section V supports.
  2. [Section V, 16-hour test] The statement that 'all boards remained synchronized with a counter offset of zero' over 16 hours is reported without stating the counter resolution, tick period, or the method used to measure the offset. A zero offset could mean simply that the offset is less than one counter tick, and if the counter tick is, for example, a sample clock period of a few nanoseconds, the bound on timing error would be far looser than the sub-picosecond jitter quoted elsewhere. Please state the counter clock frequency and the resolution of the offset measurement, and clarify whether the PTP offset correction was applied once at boot or periodically during the test. This is necessary to interpret the test as evidence for sustained RF phase alignment.
  3. [Section V, data communication latency] The paper quotes a data-communication latency of approximately 450 ns (Section V, 'hold latency') but does not present an isolated measurement of that latency. The observed 1600 ns interval between the start pulse and the conditional pulse on Board 2 is the sum of the 1 microsecond readout pulse, the 600 ns hold, and the actual communication/demodulation latency, so it does not independently verify the 450 ns figure. Please provide a direct latency measurement, for example a loopback test with timestamps at the transmitting and receiving boards, and report the link jitter and CRC error behavior. This is needed to support the 'hundreds of nanoseconds' latency claim that motivates the feed-forward architecture.
  4. [Section III, minimal PTP] The minimal PTP offset calculation assumes symmetric transit times between the two GPIO ports, but the paper provides no measurement or calibration of the asymmetry of the copper link. Any fixed asymmetry in the transmit or receive paths directly biases the computed clock offset and hence the counter alignment. Please report the measured or estimated asymmetry of the synchronization link, or at least quantify the residual offset after correction. With the current presentation, the accuracy of the PTP-based counter synchronization is not bounded independently of the unsupported assumption of symmetric transit times.
minor comments (6)
  1. [Section II, Related Work] There are typographical and naming inconsistencies: 'synotization' should be 'synchronization', 'Prestol' appears to be 'Presto', and 'Linayage et al.' should likely be 'Liyanage et al.'.
  2. [Section V, Experiments] The phrase 'prolong period' should be 'prolonged period'.
  3. [Listing 1] The indentation of the else and if statements in the pseudocode makes the control-flow nesting ambiguous; please clarify which else corresponds to which if, or use explicit braces or labels.
  4. [Figure 3] The caption states that the pulses generated by Board 2 are 'shown in red', but the figure description does not identify which trace is Board 1's readout pulse and which are Board 2's conditional pulses; please label the traces explicitly.
  5. [Section IV, Data Communication] The sentence 'connects to the rest of the design through a 64-bit data and a valid signal interface, two per lane' is incomplete and awkward; please rephrase to state clearly how many interfaces per lane are used and how they connect to the control system.
  6. [Section VI, Conclusion] The claim of being 'the first open-source solution for multi-FPGA time synchronization and data communication in the quantum domain' should be qualified, since open-source systems such as ARTIQ/DRTIO already provide distributed real-time I/O; the comparison in Section II should more clearly state what is new relative to those systems, e.g., the RFSoC-specific implementation and the integration with QubiC.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the synchronization and data-communication claims are backed by measured bench results and standard protocol formulas, with self-citations only providing project context.

full rationale

The paper's central claims are hardware demonstrations rather than derived predictions. The minimal PTP offset formula in Section III, offset = ((t2-t1)-(t4-t3))/2, is the standard symmetric-transit-time relation, and the measured 16-hour zero counter offset is a stability result after an initial one-time correction, not a fitted quantity that is later renamed a prediction. The jitter figures (1.8 ps and 7.4 ps at 6.50 GHz) are obtained from a signal source analyzer on individual outputs, again independent measurements. The mid-circuit measurement and feed-forward demo in Section V is an end-to-end self-consistency check in which the emulator supplies expected bit patterns and the oscilloscope shows the conditional pulses matching those expectations; this tests the hardware's timing and data path rather than reducing the performance claim to the emulator's inputs. The self-citations to QubiC and QubiC 2.0 identify the open-source system being extended and are not used to import an unverified theorem or to forbid alternative designs; the synchronization and communication modules are new, externally testable contributions. The paper's main weakness, that it never directly measures residual RF phase skew between two boards' outputs and does not state the counter resolution, is an evidentiary gap about how strong the alignment claim is, not a circularity of reasoning. No equation or fitted parameter is shown to be equivalent by construction to a claimed result, so the appropriate circularity score is 0.

Assumptions & free parameters 3 free parameters · 4 assumptions · 0 invented entities

This is an engineering demonstration, so the ledger lists the protocol and hardware premises the design depends on rather than fitted scientific constants. No parameter fitting of data occurs; the listed numbers are engineering choices that set the timing budget for the demonstrated benchmarks.

free parameters (3)
  • Readout hold latency = 600 ns
    Chosen wait time in the demo to cover demodulation of about 150 ns plus an assumed 450 ns data-communication latency; a design budget, not a fitted result.
  • Inter-frame delay = 32 ns
    Selected gap between transmitted readout frames; sets broadcast throughput and is customizable per the paper.
  • Aurora line rate and clock frequencies = 10.3125 Gbps; 156.25/161.1328125/125 MHz
    Standard transceiver settings that define the timing budget and are chosen for compatibility with general-purpose links.
assumptions (4)
  • standard math PTP offset equation assumes symmetric forward and reverse transit times between neighboring FPGAs.
    The minimal PTP offset correction ((t2-t1)-(t4-t3))/2 in Section III is valid only if copper link delays are symmetric; any asymmetry biases the counter alignment.
  • domain assumption Matched-length cables give equal reference-clock delay to each board.
    Section III states matched-length cables ensure aligned phase relationships; residual cable skew is not measured.
  • domain assumption ZCU216 MTS and SYSREF divider reset behave deterministically per AMD documentation.
    The design relies on documented multi-tile synchronization and zero-delay PLL behavior, Refs 38 and 39, for repeatable alignment.
  • domain assumption Aurora link delivers data reliably under operating conditions.
    CRC-32 detects user-data errors, but no BER, link-loss, or recovery data are reported; the feed-forward demo assumes reliable delivery, Section IV.

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Cite this review

Pith. "Pith review of Multi-FPGA Synchronization and Data Communication for Quantum Control and Measurement." pith.science (2026). https://pith.science/paper/G3P443JC

@misc{pith2026250609856,
  author       = {Pith},
  title        = {Pith review of: Multi-FPGA Synchronization and Data Communication for Quantum Control and Measurement},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/G3P443JC}},
  note         = {Machine review of arXiv:2506.09856}
}
read the original abstract

In the last decade, quantum computing has grown from novel physics experiments with a few qubits to commercial systems with hundreds of qubits. As quantum computers continue to grow in qubit count, the classical control systems must scale correspondingly. While a few expensive multi-board commercial solutions exist, most open-source solutions are limited to single-board radio frequency system-on-chip (RFSoC). The essential requirements for a multi-board solution are clock synchronization among multiple boards and the ability to transfer data with low latency for performing real-time feedback. In this work, we design a clock synchronization framework to distribute deterministic clock and synchronize the clock counters across multiple RFSoC boards to generate time-aligned radio frequency (RF) pulses used to control qubits. We also develop a data communication system over a fiber link to transfer quantum measurement data among multiple field-programmable gate arrays (FPGAs). This clock synchronization and data communication module has been integrated into the open-source quantum control system, QubiC, to enable the execution of quantum algorithms across multiple boards. We demonstrate the effectiveness of our design through bench tests with a room-temperature qubit readout emulator.

Figures

Figures reproduced from arXiv: 2506.09856 by the authors.

Figure 1
Figure 1. Clock synchronization among multiple FPGA boards in a ring [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 3
Figure 3. Oscilloscope output showing pulses generated by [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗

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Forward citations

Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Breaking Memory Bottlenecks in Quantum Control Systems for More Precise Experiments and Higher Throughput Computing

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    Ant-Q pipelines quantum circuit loading, execution, and readout uplink on FPGA control boards using a DRAM plus BRAM hierarchy, supporting deep randomized benchmarking circuits and reducing classical overhead to near zero.

  2. Manarat: A Scalable QICK-Based Control System for Superconducting Quantum Processors Supporting Synchronized Control of 10 Flux-Tunable Qubits

    quant-ph 2025-07 conditional novelty 5.0 of 10

    A multi-board extension of the QICK control platform synchronizes two RFSoC boards to sub-100 ps skew and runs synchronized control of 10 flux-tunable qubits.

Reference graph

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