Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links, observed 2026-08-06T17:48:53.908260Z
Paper Citation Record · LEDGER
As of 13 August 2026, this Paper Citation Record lists 29 of 29 outbound references and 0 inbound Pith citation observations for arXiv:2507.09965.
A citation records a reference. It does not transfer a finding from one paper to another.
Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links, observed 2026-08-06T17:48:53.908260Z
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-12T06:34:41.77262+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links
A source-named dated measurement, never combined with another source.
Source: cited_works
29 of 29 outbound references displayed
External citation measurements
No source-named external measurement is stored.
Observation c82d3a32-da43-41d5-9cee-3bd8dbc140aa · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design Stimulus generation for constrained random simulation,
Reference 1
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation 07de5ed3-63f1-4397-b8e6-e69b471f432b · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design Au- toBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design,
Reference 2
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation 43a9214b-6a07-4bca-8141-0df76dee088b · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design UVLLM: An Automated Universal RTL Verification Framework using LLMs,
Reference 3
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation 86d6f883-65d4-4c93-9717-9b846395f737 · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation | IEEE Conference Publication | IEEE Xplore
Reference 4
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation 96a00a75-f74f-4944-a9a2-49790a19f2da · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design ChipGPT: How far are we from natural language hardware design,
Reference 5
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation b0daac80-61cf-412d-872c-b252dba0209d · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design Chip-Chat: Chal- lenges and Opportunities in Conversational Hardware Design,
Reference 6
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation 6d8301cf-e6c0-450a-97bb-c76dbbc85171 · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design AutoChip: Automating HDL Generation Using LLM Feedback,
Reference 7
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation c71d55c1-d45d-4605-b72f-6413dbf21a9f · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design Using LLMs to Facilitate Formal Verification of RTL
Reference 8
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 532e0e8f-0575-4d12-aef8-10331e0c2d13 · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation
Reference 9
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 19bcaf43-835a-40d0-b195-8c3026a0ce1f · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design TED: A Python-Based Analog Design Environment for Agile Circuit Development,
Reference 10
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation 6acca702-290e-4b51-8d60-b99205b31e34 · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design Evaluating Large Language Models Trained on Code,
Reference 11
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation 78fcd3be-6cfd-42d0-975e-6d04ce7b2aeb · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design Artisan: Automated Operational Amplifier Design via Domain-specific Large Language Model,
Reference 12
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation 6669524d-36b0-4438-8716-0b934bcb95cf · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design LADAC: Large Language Model- driven Auto-Designer for Analog Circuits,
Reference 13
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation 962858f1-3bee-495f-b32e-6e44407abd24 · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design AmpAgent: An LLM-based Multi-Agent System for Multi-stage Amplifier Schematic Design from Literature for Process and Performance Porting,
Reference 14
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation a5f686bd-ae5e-4723-bef5-07a295b76be1 · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design A Survey on Hallucination in Large Language Models: Principles, Taxonomy, Challenges, and Open Questions | ACM Transactions on Information Systems
Reference 15
Source-reported events for the cited work
Unavailable: canonical work link unavailable.
Observation 30a71d48-f396-444a-8dde-739d29547074 · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design Analog design with verilog-a,
Reference 16
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation a17925a0-bae3-413e-a335-d855165c5319 · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design Automated Generation Procedure for Fully Differ- ential Op-Amp Using TED,
Reference 17
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation a04a440f-9248-4216-8749-dafa7c0bc04f · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits,
Reference 18
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation 487090d6-55c8-4c03-a594-9932530b0790 · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design ADO-LLM: Analog Design Bayesian Optimization with In-Context Learning of Large Language Models,
Reference 19
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation b7da624c-412d-45b1-9cfa-4dad8b5b0c7c · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design Masala- chai: A large-scale spice netlist dataset for analog circuits by harnessing ai,
Reference 20
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation 86080fe5-c6c2-4d10-aea6-b938076bfd50 · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design OpenAI Platform
Reference 21
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation 2b8b8492-b3df-4f6a-8205-b5d9f815c4a0 · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design An Ultra- Low-V oltage Ultra-Low-Power CMOS Miller OTA With Rail-to-Rail Input/Output Swing,
Reference 22
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation 13d9d694-6b02-40b3-a1fa-fb0aa95c9735 · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design 0.5-V operational transconductance amplifier for CMOS bandgap reference application,
Reference 23
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation cfab3fca-8594-4dad-b513-78495ea601c0 · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design A Miller-compensated amplifier with Gm-boosting,
Reference 24
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation 11c420d1-c6f3-4043-92a0-ce1e24f24166 · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design A CMOS 25.3 ppm ◦/C bandgap voltage reference using self-cascode composite transistor,
Reference 25
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation 2a9e60d0-aa91-4976-bc26-ebd662794a0e · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design A low-voltage low-power voltage reference based on subthreshold MOSFETs,
Reference 26
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation 19c0eb34-27c9-4839-9d77-73e69d5e8a15 · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design A 300 nW, 15 ppm/\circC, 20 ppm/V CMOS V oltage Reference Circuit Consisting of Subthreshold MOSFETs,
Reference 27
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation f44413f2-b659-448c-9600-06a949bc9e56 · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design A 65-nm CMOS Low Dropout Regulator Featuring >60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range,
Reference 28
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
Observation d3e7519b-195e-42d9-95f0-e9816e6b2134 · outbound
AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique,
Reference 29
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-12T06:34:41.77262+00:00.
No inbound Pith citation observations are available.