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REVIEW 5 major objections 6 minor 1 cited by

Rethinking LLM-Based RTL Code Optimization Via Timing Logic Metamorphosis

T0 review · 5 major / 6 minor · reviewed 2026-08-06 · deepseek-v4-flash

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Pith's one-line read The paper claims that LLM-based RTL optimization methods outperform compilers only on combinational logic and data paths, and lose to compilers on timing control flow and clock domain optimization because LLMs fail to grasp clock-cycle…

desk verdict A useful metamorphic benchmark for LLM-based RTL optimization, but the timing-logic conclusions rest on unproven cycle equivalence and an inconsistent normalization. read the letter →

arxiv 2507.16808 v1 pith:GQM4D3YW submitted 2025-07-22 cs.SE cs.AI

Zhihao Xu , Bixin Li , Lulu Wang This is my paper
classification cs.SEcs.AI
keywords empiricalstudylargelanguagemodelsRTLcodeoptimizationmetamorphictestingtiminglogicclockdomaincrossingfinitestatemachinesynthesis
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper asks whether large language models can genuinely optimize register-transfer-level (RTL) hardware code when the hard part is timing, not syntax. It introduces a metamorphosis evaluation: each RTL snippet is rewritten into a semantically equivalent but more complex mutant, and an optimizer is judged on whether its gains survive the rewrite. On logic operations and data paths, LLM-based optimizers, including RTLRewriter, GPT-4, and Claude-3.7-sonnet, match or beat the open-source synthesizer Yosys. On timing control flow and clock domain logic, they do not beat Yosys, and their results consistently degrade on the mutants. The paper attributes this to LLMs' weak grasp of clock-cycle semantics and offers the benchmark and metamorphosis protocol as a reusable way to test future optimizers.

What carries the argument

The central mechanism is the metamorphosis transformation set. For each optimization area, a rewrite rule produces a mutant intended to be functionally identical but harder to optimize: Boolean algebra rewrites and redundant terms for logic operations; always-true branches and cascaded multiplexers for data paths; inserted pass-through states and subdivided FSM states for timing control flow; and split synchronous clock domains with extra synchronizer registers for clock domains. The evaluation then normalizes every optimizer's synthesis result against Yosys's own synthesis of the same design and compares original versus mutant ratios. The load-bearing idea is symmetry: an optimizer that truly understands RTL should not lose effectiveness merely because the same function is expressed with more complex timing structure.

What would settle it

A direct test would be to verify each mutant with a sequential equivalence checker that compares cycle-by-cycle behavior over all reachable states, then re-run the benchmark only on mutants proven equivalent; if LLM optimizers still degrade on those mutants, the paper's attribution stands, and if they do not, the reported gap is an artifact of changed timing.

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Extended reading notes

Core claim

The paper's central claim is a split verdict on LLM-based RTL optimization. For combinational-style code, including logic operations, data paths, and multiplexer structures, LLM-based methods optimize as well as or better than the compiler-based baseline, and their performance on metamorphosed mutants is close to their performance on the original code. For timing-intensive code, including finite state machine control flow and multi-clock-domain logic, the same methods fail to beat Yosys and show consistently worse normalized synthesis metrics, such as wires, cells, area, delay, and power, on mutants than on originals. The paper interprets this as evidence that LLMs do not yet reason about clock cycles and temporal constraints, and it supports that reading with an embedding experiment in which one timing-preserving mutation is placed farther from the original than some semantics-breaking mutations.

Load-bearing premise

The evaluation stands on the claim that every mutant is semantically equivalent to its original, including cycle-by-cycle timing, because the inserted pass-through states and synchronizer registers may add latency and thereby change the behavior being optimized.

Editorial extensions

If this is right

  • If the claim holds, current LLM-guided RTL rewriting should not be trusted for timing control flow or clock domain optimization without independent verification.
  • The metamorphosis protocol gives future evaluations a standard test: run any new LLM optimizer on original and mutant RTL and require that optimization quality does not drop on mutants.
  • In practice, LLM-based rewriting is appropriate for logic-operation and data-path portions, while timing-critical sections should stay with compiler passes or receive explicit timing-aware guidance.
  • Prompt content matters: the paper shows that simply instructing the LLM to remove non-executing or redundant code eliminates much of the data-path mutant gap, so zero-shot prompting understates achievable results.
  • Closing the timing gap will require giving LLMs clock-cycle semantics, for example explicit timing information in the prompt or a temporally aware front end, rather than relying on their text-based training.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The state-machine and clock-domain metamorphoses insert pass-through states and synchronizer registers, which add clock cycles or latency; if those mutants are not cycle-by-cycle equivalent to the originals, the benchmark measures optimizer response to behaviorally different code rather than pure syntactic complexity.
  • A decisive follow-up would re-run the benchmark after sequential equivalence checking of each mutant, because the formal verification and simulation step the authors report does not by itself rule out cycle-count changes.
  • Because all ratios are normalized to Yosys's synthesis of the same design, the comparison conflates the optimizer's competence with Yosys's treatment of complex FSM and clock-domain constructs; a different synthesis ground truth could shift the relative rankings.
  • The embedding result suggests a predictive test: a temporal-reasoning probe on clock-edge expressions might identify which mutant constructs an LLM will misoptimize, giving a cheap way to extend the benchmark beyond the four current categories.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

5 major / 6 minor

Summary. The paper proposes a metamorphic evaluation methodology and a new benchmark for assessing LLM-based RTL code optimization across four areas: logic operations, data paths, timing control flow, and clock domains. The authors generate 'mutant' RTL designs that are claimed to be semantically equivalent to original designs but more complex, and they compare optimization effectiveness (wires, cells, area, delay, power) of LLM-based methods (RTLRewriter, GPT-4, Claude-3.7-sonnet) against Yosys on original vs. mutant code. The reported findings are that LLM-based methods outperform Yosys on logic and data-path optimization but do not outperform Yosys on timing control flow and clock-domain optimization.

Significance. The question is timely and practically important: if the finding holds, it would caution against using current LLM-based methods for timing-critical RTL optimization and motivate timing-aware model designs. The paper also contributes a benchmark and an evaluation idea that could be reused by the community. A particular strength is the inclusion of Yosys as an external baseline, which avoids the circularity of evaluating LLMs only against themselves. However, the empirical claims are currently undermined by load-bearing problems in the normalization scheme and, more fundamentally, in the semantic equivalence of the generated mutants.

major comments (5)
  1. [Section IV-E (Eq. 1) and Tables I-II] The normalization formula Ratio(d)_A = M_A(d)/M_Yosys(d) normalizes by Yosys on the same instance d, but Tables I and II are labeled 'normalized to Yosys org' and report mutant rows whose denominators cannot be Yosys(mutant): if they were, the Yosys mutant row would be identically 1.00, yet it is reported as 1.01/2.93/1.00 and 1.07/1.04/1.00. The mutant-vs-original comparisons (e.g., GPT org area 1.78 vs GPT mut 7.93 in Table I) therefore compare ratios with different denominators, and the conclusion that optimization effectiveness degrades on mutants is not supported. The analysis must be redone with one consistent normalization, preferably per-instance ratios relative to Yosys on the same instance, with the mutant/original comparison made on those ratios.
  2. [Section III-B3 and Fig. 5] The FSM metamorphosis replaces a direct transition S1→S2 with S1→S1A→S1B→S1C→S2. In a synchronous FSM each inserted state occupies at least one clock cycle, so the mutant cannot be cycle-equivalent to the original: either the intermediate states do not assert the same outputs as S1, changing the visible behavior, or they do, extending the time spent in the green/active state. The paper's assertion that 'the overall functionality and behavior are fully consistent with the original code' is therefore questionable. Because Section III-C reports no sequential equivalence checking procedure or results, RQ3's comparisons conflate added latency with added timing complexity.
  3. [Section III-B4 and Listing 3] The clock-domain metamorphosis splits a single always block into two clock domains and inserts synchronizer registers syncreg1 and syncreg2 plus an extra combinational stage between regA and regB. Even with identical-frequency clocks, data at regB is delayed by at least two additional clock cycles compared to the original, and the relationship is worse if clk2 is a multiple of clk1. Listing 3 is therefore not a semantics-preserving transformation under the paper's cycle-level notion of RTL semantics, and the RQ4 results may simply reflect the added synchronizer stages rather than any LLM-specific difficulty with clock-domain logic.
  4. [Section III-C] The paper claims that formal verification and simulation with ABC and Icarus guarantee semantic equivalence of originals and mutants, but no equivalence-checking command, netlist comparison, or quantitative results are described. ABC's commonly used `cec` checks combinational equivalence and cannot, without a documented sequential equivalence flow, certify equivalence of FSMs with extra states or synchronizer chains. Without such evidence, the key insight that optimization effectiveness should be invariant for semantically equivalent code is untested, and the metamorphic evaluation cannot support the paper's conclusions.
  5. [Section IV-B, IV-D, IV-F through IV-I] The experimental claims rest on single-run point estimates from stochastic LLMs with a single fixed prompt. No standard deviations, confidence intervals, or statistical tests are reported for any RQ, and the benchmark is limited to the authors' own 54/27/40/32 cases with no per-case distributions. The differences that drive the conclusions (e.g., Claude mut area 0.55 vs GPT mut area 7.93 in Table I) may not be reproducible or statistically significant. At minimum, repeated runs with variance reporting and, ideally, tests across the per-instance ratios are needed before the findings can be accepted.
minor comments (6)
  1. [Listings 1 and 3] The captions of Listing 1 and Listing 3 both say 'Example of Metamorphosis strategies in Logic Operation Optimization', but Listing 1 shows a counter and Listing 3 illustrates clock-domain metamorphosis; both captions should be corrected.
  2. [Abstract and Section II-B] There are several typos, including 'series issues' in the abstract (likely 'serious issues') and 'oftware programming languages' in Section II-B (missing 's' in 'software').
  3. [Section III-A] The description 'we invited a number of domain experts to classify' lacks detail: the number of experts, their qualification criteria, and inter-rater agreement are not reported, which weakens the benchmark-construction threat discussion.
  4. [Section IV-B] The benchmark is described only by counts (54, 27, 40, 32) and two source references; a table or appendix listing the module names, sources, licenses, and the classification result for each case would be needed for reproducibility.
  5. [Section II-B and Fig. 2] The t-SNE discussion says blue/green/red points show that MR-3 is farther from the original than some semantic-breaking variants, but no quantitative embedding distances are given; adding actual distance values would make the motivating observation more concrete.
  6. [Section IV-C] The definitions of wires, cells, area, delay, and power are prose-level; please specify the synthesis technology library and the exact Yosys pass script (e.g., synth, abc, opt flags), since these settings determine all reported metrics.

Circularity Check

1 steps flagged · score 4.0 of 10

The RQ3/RQ4 conclusion that LLMs fail on complex timing logic rests on an asserted, never-demonstrated cycle-level equivalence of the FSM and clock-domain mutants, whose constructions add pass-through states and synchronizer registers that change latency; the external Yosys baseline keeps the overall claim only partially independent.

  1. other [Sections III-B3, III-B4, and III-C (consumed by RQ3/RQ4; Tables I-II and Figs. 8-9)]
    "the direct transition is replaced by a longer path S1 → S1A → S1B → S1C → S2, where each intermediate state does not introduce additional logic but merely propagates the system forward ... To ensure the semantic equivalence of the original benchmark RTL code and mutant RTL code, we perform formal verification and simulation ... Theoretically, the original RTL code and mutant RTL code should exhibit the same optimization results, as the metamorphosis does not alter the program semantics of the RTL code."

    The paper's central RQ3/RQ4 finding (LLMs are not effective on complex timing logic because all methods degrade on the mutants, with the gap attributed to 'challenges LLMs face in understanding timing logic') is interpretable only if every mutant is cycle-level equivalent to its original. The paper's own constructions add timing stages: the state-machine strategy replaces a one-cycle S1→S2 transition with a four-state chain, adding clock cycles per pass-through state, and the clock-domain strategy in Listing 3 rewrites the single-cycle chain 'regB <= comb(regA)' into a two-register synchronizer pipeline (syncreg1, syncreg2) across split clocks, delaying regB by extra cycles.

full rationale

This paper is an empirical benchmark study, and its headline comparisons (LLM-based methods versus Yosys) are genuinely measured rather than derived from a fitted parameter, so there is no fit-renamed-as-prediction circularity. Citations [20] and [21] are the authors' own prior HDL-generator works, but they are used only to seed the motivating embedding study in Section II-B and are not load-bearing for the optimization-evaluation claim; the baselines RTLRewriter [5] and SymRTLO [6] are external. The load-bearing, partially circular step is the semantic-equivalence premise of the metamorphic method. Section III-C asserts formal verification with ABC and Icarus and states that original and mutant 'should exhibit the same optimization results,' yet no sequential-equivalence procedure or results are reported, and the Section III-B3 and III-B4 transformations (pass-through state chains; synchronizer registers inserted across split clock domains) visibly increase input-to-output latency. If the mutants are not cycle-exact, the RQ3/RQ4 degradation is explained by the added registers and states themselves, independent of any LLM deficiency, and the paper's conclusion 'This is primarily attributed to the challenges LLMs face in understanding timing logic in RTL code' follows from its own asserted premise rather than from the documented evidence. The threats-to-validity discussion (Section V-B) addresses benchmark representativeness and model generalizability but does not address this equivalence premise. The external Yosys baseline and the internal control (logic-operation mutants show invariance for RTLRewriter and Claude) provide independent content for part of the paper's claims, so the overall finding is only partially circular; no full derivation-reduces-to-input circularity is present and no load-bearing self-citation chain is used. Consequently, a moderate circularity score is appropriate.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

The central claim rests on the validity of the metamorphic mutants and the normalization scheme. The free parameters are methodological choices that affect mutant complexity, and the axioms include the untested semantic equivalence assumption and the normative invariance expectation, both of which are load-bearing.

free parameters (2)
  • number_of_intermediate_fsm_states = 3 in example, unspecified across benchmark
    The state machine metamorphosis inserts a chosen number of pass-through states (Section III-B3). This parameter controls mutant complexity and is not justified or swept.
  • number_of_split_clock_domains = 2 in example, unspecified across benchmark
    The clock domain metamorphosis splits logic across two clocks (Listing 3). The number of domains and the clock ratio are hand-picked and not varied.
assumptions (4)
  • domain assumption Metamorphosis mutants are semantically equivalent to the original RTL, including cycle-level timing.
    Stated in Section III-C, but the FSM and clock domain examples show added states and latencies that change timing. No sequential equivalence proof is provided.
  • ad hoc to paper Optimization effectiveness should remain consistent for semantically equivalent RTL code.
    This is the 'key insight' in the abstract and Section III, but it is a normative assumption about what effectiveness means, not a tested or proven property.
  • domain assumption Yosys is a valid reference for normalizing optimization quality.
    Section IV-E treats Yosys as the ground truth, but Yosys is only one synthesis tool and its optimization choices are not universally optimal.
  • domain assumption The four categories (logic, data path, timing control flow, clock domain) cover the relevant RTL optimization space.
    The categories are defined by the authors and based on vendor guidelines, but there is no evidence of completeness or inter-rater reliability in classification.

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Cite this review

Pith. "Pith review of Rethinking LLM-Based RTL Code Optimization Via Timing Logic Metamorphosis." pith.science (2026). https://pith.science/paper/GQM4D3YW

@misc{pith2026250716808,
  author       = {Pith},
  title        = {Pith review of: Rethinking LLM-Based RTL Code Optimization Via Timing Logic Metamorphosis},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/GQM4D3YW}},
  note         = {Machine review of arXiv:2507.16808}
}
read the original abstract

Register Transfer Level(RTL) code optimization is crucial for achieving high performance and low power consumption in digital circuit design. However, traditional optimization methods often rely on manual tuning and heuristics, which can be time-consuming and error-prone. Recent studies proposed to leverage Large Language Models(LLMs) to assist in RTL code optimization. LLMs can generate optimized code snippets based on natural language descriptions, potentially speeding up the optimization process. However, existing approaches have not thoroughly evaluated the effectiveness of LLM-Based code optimization methods for RTL code with complex timing logic. To address this gap, we conducted a comprehensive empirical investigation to assess the capability of LLM-Based RTL code optimization methods in handling RTL code with complex timing logic. In this study, we first propose a new benchmark for RTL optimization evaluation. It comprises four subsets, each corresponding to a specific area of RTL code optimization. Then we introduce a method based on metamorphosis to systematically evaluate the effectiveness of LLM-Based RTL code optimization methods.Our key insight is that the optimization effectiveness should remain consistent for semantically equivalent but more complex code. After intensive experiments, we revealed several key findings. (1) LLM-Based RTL optimization methods can effectively optimize logic operations and outperform existing compiler-based methods. (2) LLM-Based RTL optimization methods do not perform better than existing compiler-based methods on RTL code with complex timing logic, particularly in timing control flow optimization and clock domain optimization. This is primarily attributed to the challenges LLMs face in understanding timing logic in RTL code. Based on these findings, we provide insights for further research in leveraging LLMs for RTL code optimization.

Figures

Figures reproduced from arXiv: 2507.16808 by the authors.

Figure 2
Figure 2. Embedding results of original and mutated code on [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 4
Figure 4. Examples of Metamorphosis strategies in Data Path [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Example of Timing Control Flow Optimization Meta [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figures from the paper (3 more)
Figure 6
Figure 6. Figure 6: Logic Operation optimization Results with Wires and [PITH_FULL_IMAGE:figures/full_fig_p007_6.png]
Figure 8
Figure 8. Figure 8: Timing Control Flow Optimization Results with Wires [PITH_FULL_IMAGE:figures/full_fig_p008_8.png]
Figure 9
Figure 9. Figure 9: Clock Domain Optimization Results with Wires and [PITH_FULL_IMAGE:figures/full_fig_p009_9.png]

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Forward citations

Cited by 1 Pith paper

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement

    cs.AI 2026-04 unverdicted novelty 6.0 of 10

    Dr. RTL's multi-agent framework with group-relative skill learning achieves 21% WNS and 17% TNS timing improvements plus 6% area reduction on 20 real-world RTL designs over commercial synthesis tools.

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Pith tools

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