REVIEW 3 major objections 6 minor 29 references
Clock Pulling Enables Maximum-Efficiency Wireless Power Transfer
T0 review · 3 major / 6 minor · reviewed 2026-08-06 · deepseek-v4-flash
Pith's one-line read The paper claims a clock-pulling feedback loop can stabilize the maximum-efficiency state of nonlinear parity-time-symmetric wireless power transfer, and demonstrates it experimentally.
desk verdict Clever experiment stabilizes the max-efficiency mode in PT-symmetric WPT, but a sign error in Eq. (4) contradicts the paper's own stability argument and must be fixed before publication. read the letter →
The pith
A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.
The reading
What carries the argument
The mechanism is clock pulling: a phase-locked loop whose voltage-controlled oscillator provides a classical clock and forces continuous frequency variation, so feedback can act on the frequency-dependent phase of the steady-state required gain instead of being defeated by rapid transient frequency jumps. The load-bearing identity is the complex steady-state gain formula $g_{ss,c}$ (Eq. (4)); for the PT case its imaginary part changes sign across the mode $\tilde{\omega}_0 = 1$, giving the PLL a pulling polarity that increases frequency on one side and decreases it on the other. That polarity is what stabilizes the previously unstable maximum-efficiency state and destabilizes the symmetric modes.
What would settle it
Measure the phase-frequency response of the clock-pulling gain module around $\tilde{\omega}_0 = 1$ and check whether its slope matches the polarity assumed in Fig. 2(d); then flip the phase-detector operating point from $\pi$ to $0$ and see whether the stable mode switches from $\tilde{\omega}_0$ to $\tilde{\omega}_{1,2}$. If reversing the pulling polarity has no effect on which steady state is reached, the clock-pulling mechanism is not what stabilizes the maximum-efficiency mode.
Extended reading notes
Core claim
The central discovery is that the steady-state selection of a nonlinear PT-symmetric WPT dimer can be switched by a clock-pulling feedback loop. Examining the dispersion of the required gain, the authors find that the mode $\tilde{\omega}_0 = 1$, which conventionally is dismissed as unstable because it requires the highest gain, sits at an extremum of the complex required gain $g_{ss,c}$; its imaginary part has opposite polarity in the adjacent frequency bands. A phase-locked loop whose voltage-controlled oscillator provides a classical clock enforces continuous frequency variation, and near its $\phi_{\mathrm{PLL}} = \pi$ equilibrium the loop adjusts frequency with the correct polarity to pull the system to $\tilde{\omega}_0$ and hold it there, while making the symmetric modes $\tilde{\omega}_{1,2}$ unstable. The paper reports an 85 kHz two-coil prototype in which the system operates stably at $\tilde{\omega}_0$ with the theoretically maximum transfer efficiency in the strong-coupling region, consistent with coupled-mode calculations.
Load-bearing premise
The design rests on the sign of the frequency-dependent complex gain in Eq. (4), which sets the pulling polarity: if the imaginary part of the required gain does not change sign across $\tilde{\omega}_0 = 1$ in the way the paper's arrows show, the feedback would push the system away from the maximum-efficiency state instead of toward it.
Editorial extensions
If this is right
- If the paper is right, two-coil wireless power transfer can operate at the theoretical maximum transfer efficiency over a range of coupling coefficients without active tuning, outperforming conventional PT-symmetric designs in the strong-coupling region.
- The same clock-pulling principle should stabilize the corresponding zero-point mode in asymmetric non-Hermitian systems where $\chi_l \chi_c \neq 1$, since the phase-frequency response of the required gain remains similar.
- The stability assignment reverses in the PT-broken region: the clock-pulling configuration that stabilizes $\tilde{\omega}_0$ is unstable there, so the method is confined to the strong-coupling regime.
- Because the feedback reconfigures stability dynamically rather than changing the dispersion landscape, the mechanism should transfer to other nonlinear non-Hermitian platforms such as waveguide resonators, acoustic cavities, and optoelectronic oscillators.
Reading between the lines
- Beyond the paper, the same design logic should generalize to any nonlinear non-Hermitian oscillator whose required gain has an extremum at a target mode: clock pulling turns a frequency-domain extremum into a stable attractor, so other 'maximum-gain' modes could be stabilized without changing the physical nonlinearity.
- A testable extension is to sweep load resistance and coupling while recording efficiency: the clock-pulled state should track the theoretical maximum-efficiency curve up to the PT-broken boundary and then lose stability, giving a sharp quantitative prediction of the operating envelope.
- The engineering limit implied by the mechanism is feedback speed: if the loop bandwidth is too low to follow the rapid transient frequency shifts reported in earlier PT-circuit experiments, the stabilizing action will fail, so measuring loop bandwidth against frequency-switch transients would set the practical range.
Editorial analysis
A structured set of objections, weighed in public.
Referee Report
Summary. The manuscript proposes a 'clock-pulling' feedback mechanism, realized by a phase-locked loop, to stabilize the conventionally unstable symmetric mode ω̃₀ = 1 of a nonlinear parity-time-symmetric two-coil wireless power transfer system. The authors derive a coupled-mode-theory dispersion relation for the complex steady-state gain, argue that the frequency-dependent phase response of this gain permits a feedback polarity that makes the maximum-efficiency mode robustly stable, and support the idea with an FPGA-based PLL prototype operating at 85 kHz. Measured frequency and efficiency data are compared with the CMT predictions over a range of coupling coefficients. The central claim is that this clock-pulling scheme forcibly breaks the PT symmetry and enables operation at the theoretical maximum transfer efficiency without active tuning.
Significance. If correct, the paper would offer a control-theoretic route to operate a two-coil WPT system at the maximum-efficiency mode while retaining frequency robustness, and it would generalize the clock-pulling concept to other nonlinear non-Hermitian platforms. The experimental comparison is a genuine strength: Fig. 3 reports measured frequency and efficiency versus coupling coefficient for both the clock-pulling scheme and a conventional PT-symmetric system, with the model curves evidently not fitted to the data. The proposed mechanism is falsifiable and the central claim is clearly stated. However, the written algebraic derivation of the key dispersion relation contains a sign error that, as printed, reverses the feedback polarity and would destabilize the very state the design aims to stabilize. That issue must be resolved before the theoretical mechanism can be considered established.
major comments (3)
- [Eq. (4) and Fig. 2(b)-(d)] Equation (4) is algebraically inconsistent with Eq. (2) in the sign of the k² term in the imaginary part. Setting χ_c = χ_l = 1 and solving Eq. (2) for complex g_ss,c as a function of real ω̃ gives Im(g_ss,c) = 2(ω̃−1)[1 − k²/(γ² + 4(ω̃−1)²)], whereas Eq. (4) as printed has the same bracket with a plus sign. In the PT-symmetric phase k > γ, the correct sign is negative near ω̃ = 1, and the printed plus sign gives the opposite dispersion. Since the clock-pulling polarity argument in Fig. 2(d) relies on the sign of Im(g_ss,c) to determine whether a frequency error produces a stabilizing or destabilizing PLL response, the derivation as written does not support the claimed stabilization of ω̃₀. The authors should correct Eq. (4), re-plot the phase-dispersion curves in Fig. 2(b), and confirm that the polarity analysis still predicts stabilization of ω̃₀.
- [Fig. 2(b)-(d) and Sec. II] The narrative around Fig. 2(b) states that the left neighborhood of ω̃₀ exhibits negative phase angles and the right neighborhood positive angles. With the corrected sign derived from Eq. (2), the opposite holds for k > γ: left of ω̃₀ (δ < 0) gives positive Im(g_ss,c) and right (δ > 0) gives negative Im(g_ss,c). The text therefore describes the polarity that follows from the erroneous plus sign in Eq. (4), not from the stated model. The stabilization arrows in Fig. 2(d) must be re-derived from the corrected phase-frequency relation; as printed, they implement positive feedback and would destabilize the maximum-efficiency state.
- [Sec. II, Fig. 2(d)] The stability analysis is presented only as a heuristic red-arrow argument in Fig. 2(d) with no linearized small-signal stability calculation for the combined PLL/resonator dynamics. The claim that the clock-pulling scheme makes ω̃₀ 'uniquely robust stable' is load-bearing but is not supported by a Lyapunov or perturbation analysis. Given the sign error in Eq. (4), a proper linearized treatment is necessary to establish the claimed polarity and to define the conditions under which the continuous-time PLL loop actually converges to ω̃₀ rather than to ω̃₁ or ω̃₂.
minor comments (6)
- [Abstract and Introduction] The grammar 'nonlinear parity-time (PT) symmetry ... have posed' should be 'has posed', and the term 'parity-time symmetric WPT system' is used before the abbreviation PT is fully established in the same sentence; please polish the opening paragraph.
- [Fig. 1(d) caption] The caption contains a typo ('steady-state requried gain') and the axis label 'Log(gss)' should be 'Log(|g_ss,c|)' for clarity.
- [Eq. (4)] The bracket structure of Eq. (4) is ambiguous in the typeset equation; the imaginary part should be written with explicit parentheses so that the reader can immediately see the term 2χ_c²ω̃ − 2χ_c⁴χ_l² and the k² term are both inside the imaginary bracket.
- [Reference [19]] Reference [19] is given as 'See Supplement Material at url' with a placeholder 'url'; the actual supplementary link and document identifier should be provided before publication.
- [Fig. 3(c)-(d)] The measured data in Fig. 3(c) and (d) are presented without error bars or a statement of measurement uncertainty or number of repeated trials; adding this information would strengthen the claimed agreement with the CMT calculation.
- [Fig. 2(a) description] The description of the two PLL fixed-point types is confusing: for ϕ = (2n+1)π the text says the output is 'in phase' with the reference, which is unconventional for a sinusoidal phase detector; please clarify the sign convention and the relation to z_f.
Circularity Check
No significant circularity: clock-pulling stabilization is derived from the stated CMT equations and compared with measurements, not fitted or assumed.
full rationale
The paper's derivation chain is self-contained. The CMT Hamiltonian (Eq. 1) and characteristic equation (Eq. 2) yield the steady-state gain conditions (Eqs. 3a-3b); the complex gain gss,c in Eq. (4) is obtained directly from Eq. (2) under the same assumptions, and the clock-pulling polarity design in Fig. 2 is an application of that dispersion relation, not an input to it. The central claim—that PLL feedback stabilizes mode ω˜0 = 1—is supported by the phase-frequency response of the derived gain and by experiments in Fig. 3 that compare measured frequencies and efficiencies with calculated values; no parameter is fitted to the stabilization claim. The authors' prior works [15, 18] are cited as background on dispersive-gain and pseudo-Hermitian WPT, but the clock-pulling mechanism and its stability analysis are new to this paper, so the self-citations are not load-bearing. The possible sign discrepancy in Eq. (4) identified by the reader is an internal-consistency/correctness issue: if the printed sign is wrong, the polarity argument fails on mathematical grounds, but that failure would not mean the argument reduces to its own conclusion. Hence no circular step is present.
Assumptions & free parameters
assumptions (3)
- domain assumption The nonlinear gain gnl(a1) can be replaced by a constant steady-state gain gss when analyzing steady states.
- domain assumption The PLL feedback can enforce continuous frequency variation and pull the system to the desired steady state.
- ad hoc to paper The sign of the dispersion of the complex gain gss,c near e0 determines the required feedback polarity.
Cite this review
Pith. "Pith review of Clock Pulling Enables Maximum-Efficiency Wireless Power Transfer." pith.science (2026). https://pith.science/paper/VVAEBP6F
@misc{pith2026250722907,
author = {Pith},
title = {Pith review of: Clock Pulling Enables Maximum-Efficiency Wireless Power Transfer},
year = {2026},
howpublished = {\url{https://pith.science/paper/VVAEBP6F}},
note = {Machine review of arXiv:2507.22907}
}
read the original abstract
Nonlinear parity-time (PT) symmetry in non-Hermitian wireless power transfer (WPT) systems, while attracting significant attention from both physics and engineering communities, have posed formidable theoretical and practical challenges due to their complex dynamical mechanisms. Here, we revisit multistability in nonlinear non-Hermitian systems and find that the PT-symmetry state is not always stable even in PT-symmetry phase. We report a discovery on a nonlinear clock-pulling mechanism, which can forcibly break the PT symmetry. Proper implementation of this mechanism can switch the system stability, particularly in stabilizing the conventional unstable state which has the maximum transfer efficiency for WPT. Our work offers new tools for non-Hermitian physics and is expected to drive technological progress.
Figures
Reference graph
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