Pith. sign in

REVIEW 4 major objections 5 minor 3 cited by

LATTE, a two-tier FPGA-CPU decoding architecture for surface-code quantum error correction, reports over 90 percent syndrome-bandwidth reduction and constant-latency streaming decoding in arbitrarily long memory experiments.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

A hybrid FPGA-CPU streaming decoder cuts syndrome transmission by over 90% and keeps feedback latency roughly constant in long surface-code memory runs.

T0 review reviewed 2026-08-05 challenge →

load-bearing objection Solid architecture, but headline claims overreach: the 2-thread claim contradicts the paper's own Table V, and the cross-distance NLDU transfer lacks per-distance evidence. the 4 major comments →

arxiv 2509.03954 v1 pith:STWYEHOW submitted 2025-09-04 quant-ph

LATTE: A Decoding Architecture for Quantum Computing with Temporal and Spatial Scalability

Kai Zhang , Jubo Xu , Fang Zhang , Linghang Kong , Zhengfeng Ji , Jianxin Chen This is my paper
classification quant-ph PACS 03.67.Pp
keywords quantum error correctionsurface codedecoding architecturelattice surgeryneural local decoderFPGAstreaming decodingbandwidth reduction
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper sets out to show that the four practical bottlenecks of lattice-surgery quantum error correction — accuracy, throughput, transmission bandwidth, and latency — can be met simultaneously by a hybrid FPGA-CPU decoding architecture. The key claim is that a lightweight neural local decoder on the control FPGA can remove most syndrome before it is uploaded, while an asynchronous block-decoding system on the CPU decodes and merges blocks across time and space without a growing backlog. If it works, real-time decoding at physical error rates around 10^-3 becomes feasible with a few CPU threads and small FPGAs, removing a recognized obstacle to scaling superconducting fault-tolerant computers. The reported numbers are a greater than 90 percent reduction in syndrome transmission bandwidth and a 6.4x average single-block speedup at p=0.001, with constant streaming latency 16x-20x lower than a leading streaming decoder.

Core claim

The central claim is that decoding can be made scalable by splitting the decoding graph into two hierarchical stages instead of decoding the full space-time graph globally. At the FPGA tier, syndrome detectors are embedded as a tensor and a roughly 3000-parameter fully convolutional network with a (7,7,7) receptive field predicts six error classes (I, X, Y, Z, M, H) at every detector-error-model position; because errors are local and sparse, this removes more than 90 percent of the syndrome at p=0.001. At the CPU tier, the global decoding graph is partitioned into d x d x d blocks with buffer regions, decoded asynchronously in decode and merge thread pools coordinated by semaphores, with mer

What carries the argument

The load-bearing pieces are (1) the Neural Local Decoding Unit (NLDU), a streaming INT8-quantized fully convolutional network on the control FPGA whose (7,7,7) receptive field matches the typical error-chain length, and (2) the asynchronous block decoding system (BLDS) on CPU, which generalizes sliding-window decoding to full space-time blocks, decouples decode and merge via semaphores and shared memory, and is managed by a global dynamic scheduler that sends logical feedback at each tick. The syndrome tensor embedding maps arbitrary patches onto (alpha+1, beta+1, gamma, 2) tensors and errors onto six channels, turning local decoding from a subgraph matching problem into a per-vertex multi-c

Load-bearing premise

The neural local decoder is trained only on distance-13 data at three physical error rates and then applied without retraining to all code distances from 9 to 21 and error rates up to 0.005; if this transfer fails at unseen distances or boundary regions, the bandwidth-reduction and low-latency results rest on a model that has never been evaluated there.

What would settle it

Measure the remaining-syndrome ratio and logical error rate of LATTE at d=19 and d=21 at p=0.003 and p=0.005, using the shipped d=13-trained NLDU and identical simulated circuit-level noise, and compare against global minimum-weight perfect matching. If the remaining-syndrome ratio rises sharply above the roughly 22 percent seen at d=13, p=0.003, or the logical error rate deviates from MWPM beyond the buffer-convergence margin, the translation-invariance transfer claim is disproved.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

If this is right

  • Lattice-surgery circuits can stream syndromes continuously at the 1 microsecond round rate without memory overflow or exponentially growing backlog, even for arbitrarily long quantum memory experiments.
  • The CPU resource budget for decoding stays near-optimal (2 threads at distance 17), freeing cores for compilation, simulation, and control tasks.
  • Because the FPGA local unit is transparent to the block decoder, the same architecture can be paired with different base decoders such as minimum-weight perfect matching or union-find, and inherits the base decoder's accuracy.
  • The 90 percent bandwidth cut applies at p=0.001, the regime of current superconducting hardware, making the integration point practical rather than asymptotic.
  • Spatial scalability is modular: one NLDU covers patches up to distance 15, four cover distance 17 and 19, while each inference stage stays under 1 microsecond.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Editorial extension: the reported numbers assume the d=13-trained local model transfers to all distances by translation invariance; testing it directly at a held-out distance such as d=19 at p=0.005 with the same INT8 weights would separate architecture gains from model-generalization risk.
  • Editorial extension: because the NLDU output is a per-vertex six-class prediction, the same FPGA unit could be adapted to other local error models or to decoding with defects and holes during lattice surgery by retraining only the final layers; the paper demonstrates only rotated surface-code patches.
  • Editorial extension: in a full circuit with many overlapping logical patches and frequent feedback ticks, block scheduling contention and inter-FPGA communication could dominate the per-patch latency reported here; the multi-patch benchmark with 16 patches is a first step, not an upper bound on spatial scaling.
Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper presents LATTE, a hierarchical FPGA-CPU decoding architecture for surface-code lattice surgery. The CPU-side block decoding system (BLDS) partitions streaming syndromes into temporal/spatial blocks, decodes them asynchronously in a thread pool, and merges seam corrections; the FPGA-side neural local decoding unit (NLDU) is a ~3k-parameter INT8 convolutional network with a 7x7x7 receptive field that predicts local DEM errors and updates syndromes before transmission to the CPU. The authors claim circuit-level-noise accuracy close to MWPM, >90% transmission-bandwidth reduction at p=0.001, a 6.4x average single-block decoding speedup, constant streaming latency with a 16x-20x speedup over Google/Fusion Blossom, and that 2 threads are sufficient for distances up to 17. The paper includes memory/stability experiments for d=9..21, multi-block buffer convergence studies, comparisons with hardware decoders, and FPGA resource/latency tables.

Significance. If the quantitative claims hold, LATTE is a useful systems contribution: it cleanly decouples decoding and merging in a producer-consumer pipeline, integrates a very small neural pre-decoder on the control FPGA, and demonstrates low resource use. The paper's strengths include the explicit streaming architecture, modularity with respect to the base decoder, the lightweight quantized model, the resource-model equations, and the breadth of comparison against existing hardware-implemented decoders. However, the headline numbers rest on an unvalidated generalization of the NLDU across code distances and physical error rates, and most plotted results lack statistical uncertainty or controlled baselines. The significance is therefore conditional on additional validation rather than unconditional.

major comments (4)
  1. [§VI-B, Table II, Figs. 8a/9/10] The NLDU is trained only on d=13 circuit-level data at p=0.001, 0.003, 0.005, but it is deployed at d=9..21 and p up to at least 0.006 in Fig. 8a, with p=0.002 appearing in Fig. 9. The paper justifies this by 'translation invariance of convolutional networks', which holds only in the bulk: the constant-2 virtual-vertex encoding, missing-edge locations, hook-error orientations, and the boundary/bulk fraction all depend on d. No per-distance FP/FN rates or validation curves are reported, so the claim that the >90% bandwidth reduction and the latency speedups hold at untested distances is not directly supported. Please provide FP/FN as a function of d and p, and report error-barred remaining-syndrome and LER curves at each distance.
  2. [§VII-D2, Fig. 10(b)] The 16x-20x streaming-latency speedup is stated against Google/Fusion Blossom numbers taken from published work, not against a baseline run on the same hardware. Since CPU model, core count, memory system, compiler, and decoder configuration all differ, this is not a controlled comparison and the speedup factor is not a property of LATTE alone. Please provide a same-machine baseline run, or clearly label the comparison as cross-paper and weaken the abstract claim accordingly.
  3. [§VII-E1, Table V and abstract] The abstract's claim that 'merely 2 threads are sufficient' is incomplete. The system also uses a fixed pool of 2 merging threads (stated in §VII-E1), and Table V reports only the minimum number of decode threads. The criterion for 'sufficient' (latency threshold, measurement-round duration, or backlog-free operation) is not defined. Please report the full thread accounting and the criterion used to determine the minimum.
  4. [§VII-A/B, Figs. 8-9] No error bars, shot counts, or independent repetitions are reported for any LER, bandwidth, or latency curve. For logical error rates around 1e-5, Poisson sampling requires many shots to distinguish curves; for latency, run-to-run variance matters. Without uncertainty information or sample sizes, claims such as 'accuracy on par with MWPM' and 'over 90% reduction' cannot be quantitatively assessed. Please add error bars and declare the number of samples/repetitions for each reported point.
minor comments (5)
  1. [Eq. (1c) vs. Table VII] The latency model in Eq. (1c) includes a fixed 3us pipeline delay plus a term that with Table VII parameters yields roughly 4.2us, while the stage latencies in Table VII sum to about 1.2us. Please clarify what each quantity measures and reconcile the definitions.
  2. [§VI-B, FP/FN report] The false-positive/false-negative rates reported in §VI-B are given without a definition of the validation set. State whether these are on d=13 held-out data, and provide the per-distance breakdown requested above.
  3. [Table III & Table IV comparison] Table III uses qualitative entries ('High', 'Low', 'Medium') without quantitative thresholds. Table IV should state whether the comparison numbers for Lazy, CLIQUE, and Promatch were obtained with the same Stim circuits, noise model, and d/p grid, or are quoted from the respective papers.
  4. [Fig. 7 caption and Algorithm 1] Fig. 7 caption contains a typo ('visulization'). In Algorithm 1, 'f ront' appears twice in the DECODE/MERGE procedures; this should be 'front'.
  5. [§VII-C, Fig. 10(c)] The multi-patch measurement experiment lacks details on patch layout, communication/synchronization overhead, and the definition of Npatch=16. Please specify these parameters and include error bars or repeated-run statistics.

Circularity Check

0 steps flagged

No significant circularity: LATTE's headline claims are benchmarked results, not derivations from their own inputs.

full rationale

The paper's central quantitative claims—over 90% bandwidth reduction, 6.4x single-block speedup, 16-20x streaming latency improvement, and 2-thread scalability—are empirical results obtained by running the implemented system and comparing it against external baselines (Sparse Blossom/MWPM, Google/Fusion Blossom, CC). The NLDU is a supervised convolutional classifier trained on circuit-level DEM labels from Stim; its output is used to thin the syndrome before MWPM, and the resulting remaining syndrome, logical error rates, and latencies are measured outcomes. None of these metrics is an identity forced by the training objective or by a parameter fitted to the same target. The buffer size b = ceil(d/2) is not assumed as a circular input; it is validated in Fig. 8(b) against global MWPM and cross-referenced to prior work [8,48,51]. Self-citations ([51], [62]) appear as related work or as a noise-model reference and are not load-bearing: the accuracy and latency comparisons are performed in-paper. The main weakness is a generalization assumption—the NLDU is trained only at d=13 (p=0.001/0.003/0.005) and applied at d=9..21 and p=0.002—but this is standard supervised transfer, and Fig. 8(a) provides per-distance LER evidence. Missing per-distance FP/FN rates and error bars are a validation gap, not a demonstration that the claims reduce to their inputs by construction. No equation or fitted parameter in the paper is renamed as a prediction.

Axiom & Free-Parameter Ledger

3 free parameters · 4 axioms · 0 invented entities

The central claims rest on a small trained neural network, a hand-chosen classification threshold, and several domain assumptions about hardware timing and cross-distance generalization. No code, data, or bitstreams are provided, so these fitted components cannot be independently audited.

free parameters (3)
  • Neural network weights (~3000 parameters) = Trained on Stim circuit-level d=13 data at p=0.001, 0.003, 0.005; INT8 quantized
    The bandwidth-reduction and speedup claims depend on the trained classifier's false-positive and false-negative rates at p=0.001 and at code distances outside the training set.
  • Measurement/hook error threshold theta = 0.8 (pre-sigmoid threshold ln 4 in INT8)
    Chosen by hand in Section V-C; it determines the tradeoff between correcting errors locally and passing uncertain syndromes to the CPU decoder, and thus affects both bandwidth and accuracy.
  • Receptive field R=7 = 7x7x7
    Design choice in Section V-B justified by an unshown numerical experiment stating that over 90% of error chains have length at most 2; this fixes the locality and therefore the achievable bandwidth reduction of the NLDU.
axioms (4)
  • domain assumption The circuit-level noise model with I, X, Y, Z, M, D, H error types and Stim-generated DEM labels is faithful to real hardware.
    All training and benchmarking rely on Stim simulation under this model (Sections II-A, VII); no real-device data are used.
  • domain assumption A fixed 1 microsecond syndrome round emulates the readout timing of superconducting quantum hardware.
    Section IV-A sets the Streaming Syndrome Generator to 1 microsecond per round; real control hardware may have variable timing, feedback dependencies, and communication overheads.
  • ad hoc to paper Translation invariance lets a d=13-trained convolutional network generalize to d=9..21 and to physical error rates outside the training set.
    Invoked in Section VI-B.1; no per-distance validation of FP/FN rates or bandwidth reduction is reported for all claimed d and p settings.
  • domain assumption Seam merging by 2D decoding of the XOR of neighboring block seams is sufficient for circuit-level noise and arbitrary lattice surgery graphs.
    Assumed in Section IV-B and Algorithm 1; prior work (refs 8, 48, 51) supports the idea for standard memory experiments, but no proof or exhaustive validation is given for arbitrary temporal-spatial lattice surgery configurations.

reviewed 2026-08-05 · how reviews work

0 comments
Cite this review

Pith. "Pith review of LATTE: A Decoding Architecture for Quantum Computing with Temporal and Spatial Scalability." pith.science (2026). https://pith.science/paper/STWYEHOW

@misc{pith2026250903954,
  author       = {Pith},
  title        = {Pith review of: LATTE: A Decoding Architecture for Quantum Computing with Temporal and Spatial Scalability},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/STWYEHOW}},
  note         = {Machine review of arXiv:2509.03954}
}
Share X Bluesky LinkedIn Reddit HN
abstract

Quantum error correction allows inherently noisy quantum devices to emulate an ideal quantum computer with reasonable resource overhead. As a crucial component, decoding architectures have received significant attention recently. In this paper, we introduce LATTE, a FPGA-CPU hybrid decoding architecture aiming to address the key requirements of scaling up in lattice surgery quantum computation -- Latency, Accuracy, Throughput and Transmission Bandwidth, in an Eclectic manner. LATTE follows a hierarchical design: (1) A fully streaming and asynchronous block decoding system on CPU to enable parallelization both temporally and spatially. (2) A super-light yet accurate neural local decoding unit integrated with quantum control hardware on FPGA, which remains \emph{transparent} to the block decoding system, effectively reducing transmission bandwidth and accelerating the decoding process. LATTE delivers accuracy on par with the base decoder while achieving real-time decoding throughput and significantly reducing both bandwidth requirements and computational resources, enabling a level of scalability far beyond previous approaches. Under circuit-level noise $p=0.001$, LATTE achieves over $\mathbf{90\%}$ reduction in transmission bandwidth and a $\mathbf{6.4\times}$ speedup on average in single-block decoding. In the \emph{streaming decoding} scenario: (1) LATTE achieves constant and low latency ($\mathbf{16\times}$-$\mathbf{20\times}$ speedup over existing streaming decoding implementations) in arbitrarily long quantum memory experiments, with near-optimal resources -- merely $\mathbf{2}$ threads are sufficient for decoding the surface code with distance up to $17$. (2) LATTE minimizes latency in multi-patch measurement experiments through highly parallelized decoding operations. These combined efforts ensure sufficient scalability for large-scale fault-tolerant quantum computing.

Figures

Figures reproduced from arXiv: 2509.03954 by Fang Zhang, Jianxin Chen, Jubo Xu, Kai Zhang, Linghang Kong, Zhengfeng Ji.

Figure 1
Figure 1. Figure 1: (a) An illustration of the d = 3 rotated surface code with logical Z/X operators. (b) Separated decoding graph of Z and X stabilizers. The black, purple, blue and orange vertices represent (respectively) data qubits, Z stabilizers, X stabilizers, and virtual vertices assisting in decoding the errors of boundary data qubits. II. BACKGROUND AND MOTIVATION In this section, we will provide background on quantu… view at source ↗
Figure 2
Figure 2. Figure 2: (a) Temporal and spatial decoding graph example during lattice [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Decoding architecture. (a) Microarchitecture of LATTE. The readout syndromes processed by the NLDU will output in a streaming manner to the [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Block decoding and merging. (a) The decoding process decodes a [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Tensor representation for d = 5 surface code. (a) The syndrome information is embedded into the S Z , SX tensors. (b) The ground truth error labels before one-hot encoding are shown in E IXY Z , EM and EH. The output of the neural network represents the predicted probabilities of errors in the circuit, i.e. edges in the detector error model (DEM) [17, 25]. Representing errors becomes more complicated, espe… view at source ↗
Figure 6
Figure 6. Figure 6: Microarchitecture of the NLDU. The input of each layer at time step [PITH_FULL_IMAGE:figures/full_fig_p008_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Combinational logic for syndrome updating of the NLDU. For [PITH_FULL_IMAGE:figures/full_fig_p009_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: (a) Memory experiment and stability experiment. The memory [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Remaining syndrome ratio of LATTE after NLDU. [PITH_FULL_IMAGE:figures/full_fig_p011_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: (a) Single-block decoding latency. (b) Streaming decoding latency [PITH_FULL_IMAGE:figures/full_fig_p011_10.png] view at source ↗

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Forward citations

Cited by 3 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. Fast and accurate AI-based pre-decoders for surface codes

    quant-ph 2026-04 unverdicted novelty 7.0

    AI pre-decoders achieve O(1 μs) per round decoding runtimes on GPUs for surface codes while improving logical error rates over global decoding alone and enabling data-driven noise weight estimation.

  2. Rethink the Role of Neural Decoders in Quantum Error Correction

    quant-ph 2026-05 unverdicted novelty 6.0

    Neural decoders for surface-code QEC achieve practical microsecond FPGA latency when trained on large datasets with appropriate inductive biases and INT4 quantization, rather than relying on architectural complexity.

  3. Real-time Surface-Code Error Correction Using an FPGA-based Neural-Network Decoder

    quant-ph 2026-05 unverdicted novelty 6.0

    An FPGA-based neural-network decoder achieves 550 ns deterministic closed-loop latency for real-time distance-3 surface code error correction on a superconducting processor, matching offline decoding performance.

Reference graph

Works this paper leans on

63 extracted references · 51 canonical work pages · cited by 3 Pith papers · 1 internal anchor

  1. [1]

    Aleiner, Trond I

    Rajeev Acharya, Laleh Aghababaie-Beni, I. Aleiner, Trond I. Andersen, Markus Ansmann, Frank Arute, Ku- nal Arya, Abraham T. Asfaw, Nikita Astrakhantsev, Juan Atalaya, Ryan Babbush, Dave Bacon, Brian Ballard, Joseph C. Bardin, Johannes Bausch, Andreas Bengtsson, Alexander Bilmes, Sam Blackwell, Sergio Boixo, Gina Bortoli, Alexandre Bourassa, Jenna Bovaird,...

    work page 2024

  2. [2]

    Aleiner, Richard Allen, Trond I

    Rajeev Acharya, I. Aleiner, Richard Allen, Trond I. Andersen, Markus Ansmann, Frank Arute, Kunal Arya, Abraham T. Asfaw, Juan Atalaya, Ryan Babbush, Dave Bacon, Joseph C. Bardin, Jo ˜ao Marcos Vensi Basso, An- dreas Bengtsson, Sergio Boixo, Gina Bortoli, Alexandre Bourassa, Jenna Bovaird, Leon Brill, Mick Broughton, Bob B Buckley, David A. Buell, Tim Burg...

    work page 2022

  3. [3]

    Fault-tolerant quantum computation with constant error

    Dorit Aharonov and Michael Ben-Or. Fault-tolerant quantum computation with constant error. In Proceedings of the twenty-ninth annual ACM symposium on Theory of computing, pages 176–188, 1997

    work page 1997

  4. [4]

    Promatch: Ex- tending the reach of real-time quantum error correction with adaptive predecoding

    Narges Alavisamani, Suhas Vittal, Ramin Ayanzadeh, Poulami Das, and Moinuddin Qureshi. Promatch: Ex- tending the reach of real-time quantum error correction with adaptive predecoding. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3, pages 818–833. ACM, 2024

    work page 2024

  5. [5]

    U200 and u250 alveo data sheet

    AMD. U200 and u250 alveo data sheet. https://docs.amd. com/r/en-US/ds962-u200-u250/Summary, 2024. Ac- cessed: 2024-10-17

    work page 2024

  6. [6]

    Barnes, Tomasz Bialas, Okan Bugdayci, Earl T

    Ben Barber, Kenton M. Barnes, Tomasz Bialas, Okan Bugdayci, Earl T. Campbell, Neil I. Gillespie, Kauser Johar, Ram Rajan, Adam W. Richardson, Luka Skoric, Canberk Topal, Mark L. Turner, and Abbas B. Ziad. A real-time, scalable, fast and resource-efficient decoder for a quantum computer. Nature Electronics, 8:84–91, 2023

    work page 2023

  7. [7]

    Johannes Bausch, Andrew W Senior, Francisco J. H. Heras, Thomas Edlich, Alex Davies, Michael Newman, Cody Jones, Kevin Satzinger, Murphy Yuezhen Niu, Sam Blackwell, George Holland, Dvir Kafri, Juan Atalaya, Craig Gidney, Demis Hassabis, Sergio Boixo, Hartmut Neven, and Pushmeet Kohli. Learning high-accuracy error decoding for quantum processors. Nature, 6...

    work page 2024

  8. [8]

    Mod- ular decoding: parallelizable real-time decoding for quan- tum computers

    H ´ector Bomb ´ın, Chris Dawson, Ye-Hua Liu, Naomi Nickerson, Fernando Pastawski, and Sam Roberts. Mod- ular decoding: parallelizable real-time decoding for quan- tum computers. arXiv preprint arXiv:2303.04846 , 2023

    Pith/arXiv arXiv 2023

  9. [9]

    Scalable neural network decoders for higher dimensional quantum codes

    Nikolas P Breuckmann and Xiaotong Ni. Scalable neural network decoders for higher dimensional quantum codes. Quantum, 2:68, 2018

    work page 2018

  10. [10]

    Belief propagation as a partial decoder

    Laura Caune, Brendan Reid, Joan Camps, and Earl Campbell. Belief propagation as a partial decoder. arXiv preprint arXiv:2306.17142, 2023

    Pith/arXiv arXiv 2023

  11. [11]

    Tech- niques for combining fast local decoders with global decoders under circuit-level noise

    Christopher Chamberland, Luis Goncalves, Prasahnt Sivarajah, Eric Peterson, and Sebastian Grimberg. Tech- niques for combining fast local decoders with global decoders under circuit-level noise. Quantum Science and Technology, 8(4):045011, 2023

    work page 2023

  12. [12]

    Multi-path summation for decoding 2d topological codes

    Ben Criger and Imran Ashraf. Multi-path summation for decoding 2d topological codes. Quantum, 2:102, 2018

    work page 2018

  13. [13]

    Lilliput: a lightweight low-latency lookup-table decoder for near- term quantum error correction

    Poulami Das, Aditya Locharla, and Cody Jones. Lilliput: a lightweight low-latency lookup-table decoder for near- term quantum error correction. In Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems , pages 541–553. ACM, 2022

    work page 2022

  14. [14]

    Afs: Accurate, fast, and scalable error-decoding for fault-tolerant quantum computers

    Poulami Das, Christopher A Pattison, Srilatha Manne, Douglas M Carmean, Krysta M Svore, Moinuddin Qureshi, and Nicolas Delfosse. Afs: Accurate, fast, and scalable error-decoding for fault-tolerant quantum computers. In 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA) , pages 259–273. IEEE, 2022

    work page 2022

  15. [15]

    Hierarchical decoding to reduce hardware requirements for quantum computing

    Nicolas Delfosse. Hierarchical decoding to reduce hardware requirements for quantum computing. arXiv preprint arXiv:2001.11427, 2020

    Pith/arXiv arXiv 2001

  16. [16]

    Almost-linear time decoding algorithm for topological codes

    Nicolas Delfosse and Naomi H Nickerson. Almost-linear time decoding algorithm for topological codes. Quantum, 5:595, 2021

    2021

  17. [17]

    Topological quantum memory

    Eric Dennis, Alexei Kitaev, Andrew Landahl, and John Preskill. Topological quantum memory. Journal of Mathematical Physics, 43(9):4452–4505, 2002

    2002

  18. [18]

    Cooperating sequential processes

    Edsger W Dijkstra. Cooperating sequential processes. In The origin of concurrent programming: from semaphores to remote procedure calls , pages 65–138. Springer, Berlin, Heidelberg, 2002

    work page 2002

  19. [19]

    Matching, euler tours and the chinese postman

    Jack Edmonds and Ellis L Johnson. Matching, euler tours and the chinese postman. Mathematical programming, 5:88–124, 1973

    work page 1973

  20. [20]

    The end: An equivariant neural decoder for quantum error correction

    Evgenii Egorov, Roberto Bondesan, and Max Welling. The end: An equivariant neural decoder for quantum error correction. arXiv preprint arXiv:2304.07362, 2023

    Pith/arXiv arXiv 2023

  21. [21]

    Entangling logical qubits with lattice surgery

    Alexander Erhard, Hendrik Poulsen Nautrup, Michael Meth, Lukas Postler, Roman Stricker, Martin Stadler, Vlad Negnevitsky, Martin Ringbauer, Philipp Schindler, Hans J Briegel, et al. Entangling logical qubits with lattice surgery. Nature, 589(7841):220–224, 2021

    work page 2021

  22. [22]

    Optimal complexity correction of correlated errors in the surface code

    Austin G Fowler. Optimal complexity correction of correlated errors in the surface code. arXiv preprint arXiv:1310.0863, 2013

    Pith/arXiv arXiv 2013

  23. [23]

    Surface codes: Towards practical large-scale quantum computation

    Austin G Fowler, Matteo Mariantoni, John M Marti- nis, and Andrew N Cleland. Surface codes: Towards practical large-scale quantum computation. Physical Review A—Atomic, Molecular, and Optical Physics , 86(3):032324, 2012

    work page 2012

  24. [24]

    Establishing a new benchmark in quantum computational advantage with 105-qubit zuchongzhi 3.0 processor

    Dongxin Gao, Daojin Fan, Chen Zha, Jiahao Bei, Guo- qing Cai, Jianbin Cai, Sirui Cao, Fusheng Chen, Jiang 15 Chen, Kefu Chen, Xiawei Chen, Xiqing Chen, Zhe Chen, Zhiyuan Chen, Zi-Han Chen, Wenhao Chu, Hui Deng, Zhibin Deng, Pei Ding, Xun Ding, Zhuzhengqi Ding, Shuai Dong, Yupeng Dong, Bo Fan, Yu Fu, Song-Ming Gao, Lei Ge, Ming Gong, Jiacheng Gui, Cheng Gu...

    work page 2025

  25. [25]

    Stim: a fast stabilizer circuit simulator

    Craig Gidney. Stim: a fast stabilizer circuit simulator. Quantum, 5:497, 2021

    2021

  26. [26]

    Stability experiments: The overlooked dual of memory experiments

    Craig Gidney. Stability experiments: The overlooked dual of memory experiments. Quantum, 6:786, 2022

    work page 2022

  27. [27]

    A fast quantum mechanical algorithm for database search

    Lov K Grover. A fast quantum mechanical algorithm for database search. In Proceedings of the twenty-eighth annual ACM symposium on Theory of computing , pages 212–219, 1996

    1996

  28. [28]

    Pymatching: A python package for decoding quantum codes with minimum-weight perfect matching

    Oscar Higgott. Pymatching: A python package for decoding quantum codes with minimum-weight perfect matching. ACM Transactions on Quantum Computing , 3(3):1–16, 2022

    work page 2022

  29. [29]

    Sparse blossom: cor- recting a million errors per core second with minimum- weight matching

    Oscar Higgott and Craig Gidney. Sparse blossom: cor- recting a million errors per core second with minimum- weight matching. Quantum, 9:1600, 2025

    work page 2025

  30. [30]

    Nisq+: Boosting quantum computing power by approx- imating quantum error correction

    Adam Holmes, Mohammad Reza Jokar, Ghasem Pasandi, Yongshan Ding, Massoud Pedram, and Frederic T Chong. Nisq+: Boosting quantum computing power by approx- imating quantum error correction. In 2020 ACM/IEEE 47th annual international symposium on computer ar- chitecture (ISCA), pages 556–569. IEEE, 2020

    work page 2020

  31. [31]

    Quantization and training of neural networks for efficient integer-arithmetic-only inference

    Benoit Jacob, Skirmantas Kligys, Bo Chen, Menglong Zhu, Matthew Tang, Andrew Howard, Hartwig Adam, and Dmitry Kalenichenko. Quantization and training of neural networks for efficient integer-arithmetic-only inference. In Proceedings of the IEEE conference on computer vision and pattern recognition , pages 2704– 2713, 2018

    work page 2018

  32. [32]

    Quantum error correction with imperfect gates

    A Yu Kitaev. Quantum error correction with imperfect gates. In Quantum communication, computing, and measurement, pages 181–188. Springer, 1997

    work page 1997

  33. [33]

    Resilient quantum computation

    Emanuel Knill, Raymond Laflamme, and Wojciech H Zurek. Resilient quantum computation. Science, 279(5349):342–345, 1998

    work page 1998

  34. [34]

    Blossom v: a new implementation of a minimum cost perfect matching algorithm

    Vladimir Kolmogorov. Blossom v: a new implementation of a minimum cost perfect matching algorithm. Mathe- matical Programming Computation , 1:43–67, 2009

    work page 2009

  35. [35]

    Norris, Christian Kraglund Andersen, M

    Sebastian Krinner, Nathan Lacroix, Ants Remm, Agustin Di Paolo, ´Elie Genois, Catherine Leroux, Christoph Hellings, Stefania Laz ˘ar, Franc ¸ois Swiadek, Johannes Herrmann, Graham J. Norris, Christian Kraglund Andersen, M. Muller, Alexandre Blais, Christopher Eichler, and Andreas Wallraff. Realizing repeated quantum error correction in a distance-three su...

    work page 2022

  36. [36]

    Spatially parallel decoding for multi-qubit lattice surgery

    Sophia Fuhui Lin, Eric C Peterson, Krishanu Sankar, and Prasahnt Sivarajah. Spatially parallel decoding for multi- qubit lattice surgery. arXiv preprint arXiv:2403.01353 , 2024

    work page internal anchor Pith review Pith/arXiv arXiv 2024

  37. [37]

    A game of surface codes: Large-scale quantum computing with lattice surgery

    Daniel Litinski. A game of surface codes: Large-scale quantum computing with lattice surgery. Quantum, 3:128, 2019

    work page 2019

  38. [38]

    A substrate scheduler for compiling arbitrary fault-tolerant graph states

    Sitong Liu, Naphan Benchasattabuse, Darcy QC Mor- gan, Michal Hajdu ˇsek, Simon J Devitt, and Rodney Van Meter. A substrate scheduler for compiling arbitrary fault-tolerant graph states. In 2023 IEEE International Conference on Quantum Computing and Engineering (QCE), volume 1, pages 870–880. IEEE, 2023

    work page 2023

  39. [39]

    Fpga-based distributed union-find decoder for surface codes

    Namitha Liyanage, Yue Wu, Siona Tagare, and Lin Zhong. Fpga-based distributed union-find decoder for surface codes. IEEE Transactions on Quantum Engi- neering, 2024

    work page 2024

  40. [40]

    Universal quantum simulators

    Seth Lloyd. Universal quantum simulators. Science, 273(5278):1073–1078, 1996

    1996

  41. [41]

    Scal- able neural decoder for topological surface codes

    Kai Meinerz, Chae-Yeun Park, and Simon Trebst. Scal- able neural decoder for topological surface codes. Phys- ical Review Letters , 128(8):080505, 2022

    work page 2022

  42. [42]

    Pytorch: An imperative style, high-performance deep learning library

    Adam Paszke, Sam Gross, Francisco Massa, Adam Lerer, James Bradbury, Gregory Chanan, Trevor Killeen, Zem- ing Lin, Natalia Gimelshein, Luca Antiga, Alban Des- maison, Andreas Kopf, Edward Yang, Zachary DeVito, Martin Raison, Alykhan Tejani, Sasank Chilamkurthy, Benoit Steiner, Lu Fang, Junjie Bai, and Soumith Chin- 16 tala. Pytorch: An imperative style, h...

    work page 2019

  43. [43]

    A variational eigenvalue solver on a photonic quantum processor

    Alberto Peruzzo, Jarrod McClean, Peter Shadbolt, Man- Hong Yung, Xiao-Qi Zhou, Peter J Love, Al ´an Aspuru- Guzik, and Jeremy L O’brien. A variational eigenvalue solver on a photonic quantum processor. Nature commu- nications, 5(1):4213, 2014

    work page 2014

  44. [44]

    Better than worst-case decoding for quantum error correction

    Gokul Subramanian Ravi, Jonathan M Baker, Arash Fayyazi, Sophia Fuhui Lin, Ali Javadi-Abhari, Massoud Pedram, and Frederic T Chong. Better than worst-case decoding for quantum error correction. In Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2, pages 88–102, 2023

    work page 2023

  45. [45]

    Pauli frames for quantum computer architectures

    Leon Riesebos, Xiang Fu, Savvas Varsamopoulos, Car- men G Almudever, and Koen Bertels. Pauli frames for quantum computer architectures. In Proceedings of the 54th Annual Design Automation Conference 2017 , pages 1–6, 2017

    work page 2017

  46. [46]

    Gresh, Aaron M

    Ciar ´an Ryan-Anderson, Justin Gary Bohnet, K W Lee, Daniel N. Gresh, Aaron M. Hankin, John P. Gaebler, David Francois, Alexander Chernoguzov, Dario Luc- chetti, Natalie C. Brown, T. M. Gatterman, Si Khadir Halit, Kevin A. Gilmore, J. Gerber, Brian Neyenhuis, David Hayes, and Russell P. Stutz. Realization of real- time fault-tolerant quantum error correct...

    work page 2021

  47. [47]

    Polynomial-time algorithms for prime factorization and discrete logarithms on a quantum com- puter

    Peter W Shor. Polynomial-time algorithms for prime factorization and discrete logarithms on a quantum com- puter. SIAM review, 41(2):303–332, 1999

    work page 1999

  48. [48]

    Parallel window decod- ing enables scalable fault tolerant quantum computation

    Luka Skoric, Dan E Browne, Kenton M Barnes, Neil I Gillespie, and Earl T Campbell. Parallel window decod- ing enables scalable fault tolerant quantum computation. Nature Communications, 14(1):7040, 2023

    work page 2023

  49. [49]

    Local predecoder to reduce the bandwidth and latency of quantum error correction

    Samuel C Smith, Benjamin J Brown, and Stephen D Bartlett. Local predecoder to reduce the bandwidth and latency of quantum error correction. Physical Review Applied, 19(3):034050, 2023

    work page 2023

  50. [50]

    A sat scalpel for lattice surgery: Representa- tion and synthesis of subroutines for surface-code fault- tolerant quantum computing

    Daniel Bochen Tan, Murphy Yuezhen Niu, and Craig Gidney. A sat scalpel for lattice surgery: Representa- tion and synthesis of subroutines for surface-code fault- tolerant quantum computing. In 2024 ACM/IEEE 51st Annual International Symposium on Computer Architec- ture (ISCA), pages 325–339. IEEE, 2024

    work page 2024

  51. [51]

    Scalable surface-code decoders with par- allelization in time

    Xinyu Tan, Fang Zhang, Rui Chao, Yaoyun Shi, and Jianxin Chen. Scalable surface-code decoders with par- allelization in time. PRX Quantum, 4(4):040344, 2023

    work page 2023

  52. [52]

    Quantum error correction for quantum memories

    Barbara M Terhal. Quantum error correction for quantum memories. Reviews of Modern Physics , 87(2):307–346, 2015

    work page 2015

  53. [53]

    Neural network decoder for near-term surface-code experiments

    Boris M Varbanov, Marc Serra-Peralta, David Byfield, and Barbara M Terhal. Neural network decoder for near-term surface-code experiments. arXiv preprint arXiv:2307.03280, 2023

    Pith/arXiv arXiv 2023

  54. [54]

    Astrea: Accurate quantum error-decoding via practical minimum-weight perfect-matching

    Suhas Vittal, Poulami Das, and Moinuddin Qureshi. Astrea: Accurate quantum error-decoding via practical minimum-weight perfect-matching. In Proceedings of the 50th Annual International Symposium on Computer Architecture, pages 1–16, 2023

    work page 2023

  55. [55]

    Rapid high-fidelity single-shot dispersive readout of superconducting qubits

    Theo Walter, Philipp Kurpiers, Simone Gasparinetti, Paul Magnard, Anton Poto ˇcnik, Yves Salath ´e, Marek Pechal, Mintu Mondal, Markus Oppliger, Christopher Eichler, and Andreas Wallraff. Rapid high-fidelity single-shot dispersive readout of superconducting qubits. Physical Review Applied, 7(5):054020, 2017

    work page 2017

  56. [56]

    Transformer-qec: quantum error correction code decoding with transferable transformers

    Hanrui Wang, Pengyu Liu, Kevin Shao, Dantong Li, Jiaqi Gu, David Z Pan, Yongshan Ding, and Song Han. Transformer-qec: quantum error correction code decoding with transferable transformers. arXiv preprint arXiv:2311.16082, 2023

    Pith/arXiv arXiv 2023

  57. [57]

    A high performance compiler for very large scale surface code computations

    George Watkins, Hoang Minh Nguyen, Keelan Watkins, Steven Pearce, Hoi-Kwan Lau, and Alexandru Paler. A high performance compiler for very large scale surface code computations. Quantum, 8:1354, 2024

    work page 2024

  58. [58]

    Fusion blossom: Fast mwpm decoders for qec

    Yue Wu and Lin Zhong. Fusion blossom: Fast mwpm decoders for qec. In 2023 IEEE International Confer- ence on Quantum Computing and Engineering (QCE) , volume 1, pages 928–938. IEEE, 2023

    work page 2023

  59. [59]

    Hypergraph minimum-weight parity factor decoder for qec

    Yue Wu, Lin Zhong, and Shruti Puri. Hypergraph minimum-weight parity factor decoder for qec. Bulletin of the American Physical Society , 2024

    work page 2024

  60. [60]

    Qubic: An open-source fpga- based control and measurement system for superconduct- ing quantum information processors

    Yilun Xu, Gang Huang, Jan Balewski, Ravi Naik, Alexis Morvan, Bradley Mitchell, Kasra Nowrouzi, David I Santiago, and Irfan Siddiqi. Qubic: An open-source fpga- based control and measurement system for superconduct- ing quantum information processors. IEEE Transactions on Quantum Engineering , 2:1–11, 2021

    work page 2021

  61. [61]

    Fpga-based electronic system for the control and readout of superconducting quantum processors

    Yuchen Yang, Zhongtao Shen, Xing Zhu, Ziqi Wang, Gengyan Zhang, Jingwei Zhou, Xun Jiang, Chunqing Deng, and Shubin Liu. Fpga-based electronic system for the control and readout of superconducting quantum processors. Review of Scientific Instruments, 93(7), 2022

    work page 2022

  62. [62]

    A classical architecture for dig- ital quantum computers

    Fang Zhang, Xing Zhu, Rui Chao, Cupjin Huang, Ling- hang Kong, Guoyang Chen, Dawei Ding, Haishan Feng, Yihuai Gao, Xiaotong Ni, Liwei Qiu, Zhe Wei, Yueming Yang, Yang Zhao, Yaoyun Shi, Weifeng Zhang, Peng Zhou, and Jianxin Chen. A classical architecture for dig- ital quantum computers. ACM Transactions on Quantum Computing, 5(1):1–24, 2023

    work page 2023

  63. [63]

    Realization of an error-correcting surface code with superconducting qubits

    You-Wei Zhao, Yangsen Ye, Heliang Huang, Yiming Zhang, Dachao Wu, Hui-Rui Guan, Qingling Zhu, Zuolin Wei, Tan He, Sirui Cao, Fusheng Chen, Tung Hsun Chung, Hui Deng, Daojin Fan, Ming Gong, Cheng Guo, Shaojun Guo, Lianchen Han, Na Li, Shaowei Li, Yuan Li, Futian Liang, Jin Lin, Haoran Qian, Hao Rong, Hong Su, Lihua Sun, Shiyu Wang, Yulin Wu, Yu Xu, Chong Y...

    work page 2022

This paper was first reviewed by deepseek-v4-flash on August 5, 2026.