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Monolithic 3D integration lets tantalum pentoxide photonics be deposited directly onto arbitrary substrates, demonstrated here on lithium niobate, and enables combined second- and third-order nonlinear devices on a single chip.

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Monolithic 3D stacking of tantala photonics onto lithium niobate enables low-loss interlayer routing and combined second- and third-order nonlinear frequency conversion on a single wafer.

T0 review reviewed 2026-08-04 challenge →

load-bearing objection A credible and significant demonstration of monolithic tantala-on-LNOI 3D photonic integration, but the 'arbitrary substrates' claim overreaches given the 500 °C anneal and absence of a second substrate test. the 3 major comments →

arxiv 2509.08092 v1 pith:6B6IM5WP submitted 2025-09-09 physics.optics

Monolithic 3D integration of tantalum pentoxide photonics on arbitrary substrates

Grant M. Brodnik , Grisha Spektor , Lindell M. Williams , Jizhao Zang , Alexa R. Carollo , Atasi Dan , Jennifer A. Black , David R. Carlson
show 1 more author
Scott B. Papp
This is my paper
classification physics.optics
keywords monolithic 3D integrationtantala photonicslithium niobatenonlinear opticsoptical parametric oscillationsoliton microcombssecond-harmonic generationinterlayer routing
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Monolithic 3D integration usually requires bonding or substrate-specific processing. This paper claims that tantalum pentoxide (tantala) photonics can be deposited directly on top of arbitrary photonic substrates at room temperature, with only low-temperature anneals, and still deliver high-performance devices. On a lithium niobate platform, the authors show low-loss tantala waveguides with quality factors above five million, efficient routing between the tantala and LN layers, and simultaneous operation of third-order nonlinear tantala devices and second-order nonlinear poled-LN devices. If the approach generalizes to other substrates, it would let fab-scale foundries add nonlinear and visible-light photonics to existing chip platforms without changing the substrate. The paper only demonstrates the process on LN-on-silicon, so the 'arbitrary substrate' claim rests on compatibility assumptions that remain untested.

Core claim

The central discovery is a wafer-scale process flow in which tantala is sputtered and patterned directly on top of a prefabricated photonic substrate—demonstrated with thin-film lithium niobate on silicon—and then used to make high-Q microresonators, photonic-crystal resonators, and interlayer tapers. Because tantala is deposited at room temperature, annealed at only 500 °C, and has low residual stress, the upper layer can be built without removing or reflowing the lower substrate. The paper demonstrates the payoff: a single chip that does χ(3) optical parametric oscillation and soliton comb generation in tantala, χ(2) second-harmonic generation in poled LN, and cascaded χ(3)→χ(2) conversion

What carries the argument

The process is the mechanism: direct ion-beam sputtering of tantala onto an already-processed wafer, followed by an oxide filler layer, chemical-mechanical planarization, and lithographic patterning of the tantala. The load-bearing parts are the low-stress, low-temperature tantala film, which lets the upper layer be built without disturbing the substrate, and vertically coupled inverse tapers in both layers, which adiabatically transfer the optical mode between the tantala and LN waveguides with measured loss below 0.2 dB at 1550 nm.

Load-bearing premise

The process can be applied to 'arbitrary substrates' without degrading them—specifically, the 500 °C anneal and chemical-mechanical planarization step have only been tested on lithium niobate on silicon, and nothing in the paper shows they leave other optical materials or prefabricated devices unharmed.

What would settle it

Run the identical tantala deposition and 500 °C/12 h anneal on a different photonic platform, for example a silicon-nitride chip or a wafer with pre-patterned electro-optic devices, and compare the lower-layer device's optical loss and electrical performance before and after; any measurable degradation would falsify the 'arbitrary substrate' claim.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

If this is right

  • If the process transfers to other substrates, a single foundry line could add broadband visible and SWIR nonlinear photonics to silicon nitride, silicon, or lithium tantalate platforms without bonding steps.
  • The demonstrated cascaded χ(3)-χ(2) device shows that interlayer routing can combine nonlinear processes that no single material supports efficiently.
  • Low-loss interlayer tapers make 3D routing a practical tool for dense photonic circuits, not just a research demo.
  • Quality factors above 5 million in the upper tantala layer indicate that the integration process does not catastrophically degrade the deposited tantala's loss, preserving low parametric-oscillation thresholds.
  • Room-temperature deposition and low annealing temperatures keep the process compatible in principle with backend-of-line CMOS-style integration, opening a path to photonics directly on electronics wafers if thermal-budget constraints are met.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The 'arbitrary substrate' claim is broader than what is demonstrated; a natural next test would run the same flow on silicon nitride or on a wafer containing pre-patterned electro-optic devices, measuring lower-layer performance before and after.
  • The measured SHG phase-matching offset between chips hints at wafer-level thickness variations; adapting the poling pitch to measured thickness maps could close that gap and is a cheap, testable improvement.
  • If tantala can be doped (e.g., with titanium) to relax the anneal, the thermal budget drops further, making the process plausible on temperature-sensitive substrates such as polymer or III-V wafers.
  • Interlayer taper loss at 780 nm is higher than at 1550 nm; extending the taper length or optimizing modal overlap specifically in the visible could yield visible-band 3D routing that is loss-competitive with single-layer guides.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 7 minor

Summary. The paper introduces a monolithic 3D integration process in which tantala photonics are deposited by room-temperature ion-beam sputtering onto a patterned thin-film lithium niobate (LN) substrate, with oxide planarization and a 500 °C / 12 h anneal. The authors demonstrate low-loss tantala waveguides with intrinsic quality factors on the order of 5 million, interlayer taper losses below 0.2 dB at 1550 nm and 0.5 dB at 780 nm, quasi-phase-matched SHG in poled LN with geometry-normalized efficiencies up to 13000 %W−1cm−2, octave-spanning χ(3) OPO, dark-pulse soliton microcombs, and a cascaded χ(3)–χ(2) device. The central claim is that this constitutes full-wafer, monolithic 3D integration of tantala photonics onto arbitrary substrates, with thin-film LN on silicon as the demonstration platform.

Significance. If the central claim is accepted, this is a significant advance: it provides a wafer-level route to combine a low-loss χ(3) tantala platform with a χ(2) LN platform, including efficient vertical interlayer tapers and a broad nonlinear device palette. The paper is strong on experimental breadth and on transparent use of prior Sellmeier data and FEM simulation for dispersion and quasi-phase-matching design, with the acknowledged phase-matching offset a sign of honest reporting. The main weakness is that the 'arbitrary substrates' claim is supported by only one substrate and by a process that includes a 500 °C anneal and CMP, which are not substrate-agnostic. The quantitative headliner metrics also lack uncertainty analysis.

major comments (3)
  1. [Sec. 3 / Fig. 2a; title/abstract/conclusion] The central, load-bearing claim is monolithic 3D integration of tantala photonics onto 'arbitrary substrates'. The only demonstration is thin-film LN on silicon. The process flow includes ALD SiO2 deposition, CMP planarization, and a 500 °C / 12 h anneal after room-temperature IBS. A 500 °C step exceeds the thermal budget of many platforms (polymers, III–V with backend metals, CMOS BEOL Cu/low-k), and CMP imposes mechanical/chemical constraints that are not substrate-agnostic. The anneal-free titanium-doped variant [39] is mentioned but not used. The conclusion's 'low-temperature processing' is therefore an overstatement for the demonstrated process. Either demonstrate a second substrate or lower-layer device before/after processing, or revise the title/abstract/conclusion to the demonstrated LNOI-compatible process.
  2. [Sec. 3 (fabrication) and Sec. 4 (SHG)] The phrase 'without compromising substrate performance or compatibility' is not directly evidenced. No identical lower-layer device (e.g., a PPLN waveguide or high-Q LN resonator) is characterized before and after tantala deposition, CMP, and the 500 °C anneal. The reported SHG after integration is impressive, but it does not show that the lower layer is unaffected. Provide comparative Q and SHG efficiency measurements with and without the upper tantala stack, or state that this compatibility has not yet been tested. This is load-bearing for the integration claim.
  3. [Secs. 3–4; Figs. 2b, 2e, 3f] Quantitative headline metrics are given without error bars or uncertainty analysis: Q_i 'on the order of 5 million' and ~7×10^5–1×10^6 in Fig. 2b; loss per taper transition '<0.2 dB' (1550 nm) and '<0.5 dB' (780 nm) in Fig. 2e; SHG conversion efficiencies 13000/2200/4500 %W−1cm−2 in Fig. 3f. The number of devices, fit residuals, and calibration uncertainties are not reported. Since these values are the evidence for 'low-loss' and 'efficient' performance, the paper should provide uncertainty and sample-size information or clearly state that the values are representative single-device measurements.
minor comments (7)
  1. [Sec. 3] 'fluorene-based plasma' is likely a typo for 'fluorine-based plasma'; please correct.
  2. [Introduction vs Sec. 3] The introduction says Q_i 'exceeding 5 million' while Sec. 3 says 'on the order of 5 Million'. Make these consistent and report the maximum measured value.
  3. [Fig. 2e] Please describe how the loss-per-transition is extracted from the serially cascaded taper test structures (fit model, calibration procedure, number of transitions per device).
  4. [Fig. 3f / Methods] State explicitly the quadratic fit form, whether pump depletion is negligible at the highest powers, and how the on-chip pump power calibration accounts for coupling uncertainty.
  5. [Eq. (1)] Define k_ω and k_2ω explicitly and specify the mode order used in the QPM calculation.
  6. [References] Reference [39] is cited as an arXiv preprint; update if it has been accepted in a peer-reviewed venue.
  7. [Data availability] The statement 'All data necessary to evaluate the conclusions' would be more useful with a supplementary table listing the individual Q_i, taper-loss, and SHG-efficiency values.

Circularity Check

0 steps flagged

No circularity: empirical demonstrations are self-contained; self-citations are background and not load-bearing.

full rationale

The paper's central claims are direct measurements and device demonstrations, not derivations that reduce to their inputs. Intrinsic quality factors are measured (Fig. 2b), interlayer taper loss is measured (Fig. 2e), SHG efficiency and spectra are measured (Fig. 3), and OPO/comb/SHG spectra are measured (Fig. 4c). None of these outputs is defined by a fitted parameter that was extracted from the same data. The quasi-phase-matching model in Methods uses standard Sellmeier data for MgO-doped LN and SiO2, an FEM mode solver, and the textbook QPM relation (Eq. 1); the paper explicitly notes a slight offset between the modeled curve and measured gain centers, showing the model is not force-fitted to the data. Dispersion engineering uses a prior tantala Sellmeier fit [37] as an external refractive-index input; that Sellmeier curve is not derived from the present resonator comb measurements, and the paper reports measured D2/Dint results (Fig. 4a,b) rather than presenting those measurements as a prediction of the model. The numerous self-citations ([6], [33]–[36], [37], [39], [45]) are background, design, or material-characterization references from the authors' prior work; they are not invoked as uniqueness theorems and do not define the demonstrated nonlinear or routing results. The broad claim of 'arbitrary substrates' is supported only by a single LN-on-Si demonstration, and the 500 °C/12 h anneal and CMP step in Sec. 3 may not be portable to all substrates; however, that is a generalizability/correctness limitation, not a circular-derivation issue. No step in the paper's claimed derivation chain is equivalent to its inputs by construction.

Axiom & Free-Parameter Ledger

0 free parameters · 4 axioms · 0 invented entities

The central demonstration is experimental; no free parameters are fitted to data in this paper. It relies on published refractive-index data and standard numerical solvers. The 'arbitrary substrate' claim is an assumption not established by the experiments.

axioms (4)
  • domain assumption Sellmeier refractive index data for MgO-doped LN and SiO2 from refs [38,53] are accurate for the fabricated films.
    Used in the QPM phase-matching model (Methods, 'Second-harmonic quasi-phase-matching').
  • standard math FEM mode solver accurately computes effective indices for the fabricated waveguide geometry.
    Used for both QPM curve and dispersion modeling (Methods).
  • domain assumption Tantala material dispersion from ref [37] applies to the deposited film.
    Used in GVD simulations (Methods, 'Tantala dispersion design').
  • domain assumption The linearly tapered inverse tapers are adiabatic as simulated by FDTD, so measured loss-per-transition reflects the taper design.
    Assumed in interlayer routing loss characterization (Section 3).

reviewed 2026-08-04 · how reviews work

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Cite this review

Pith. "Pith review of Monolithic 3D integration of tantalum pentoxide photonics on arbitrary substrates." pith.science (2026). https://pith.science/paper/6B6IM5WP

@misc{pith2026250908092,
  author       = {Pith},
  title        = {Pith review of: Monolithic 3D integration of tantalum pentoxide photonics on arbitrary substrates},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/6B6IM5WP}},
  note         = {Machine review of arXiv:2509.08092}
}
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abstract

The photonics landscape encompasses a wide scope of material platforms, each optimized for specific functionalities, yet no platform meets the demands of all current and evolving photonic applications. While combining integrated photonics materials enhances overall capability - such as unifying nonlinear optics, low-loss passive devices, and electro-optics - material and process compatibility remains a major challenge. We introduce full-wafer, monolithic 3D integration of tantalum pentoxide (Ta$_2$O$_5$, hereafter tantala) photonics onto arbitrary substrates, which we explore here with thin-film lithium niobate (LN) on silicon. Tantala's unique properties, importantly room-temperature deposition, low-temperature annealing, and low stress in thick films optimized for phase matching, make it well suited for monolithic 3D integration without compromising substrate performance or compatibility. We demonstrate low-loss, high-quality-factor microresonators and nanophotonics in tantala, robust quasi-phase-matching in poled LN waveguides, and efficient 3D interlayer routing. This enables us to demonstrate a rich palette of nonlinear frequency conversion processes, including $\chi^{(3)}$ optical parametric oscillation (OPO) and soliton microcomb generation in tantala microresonators and photonic-crystal resonators, $\chi^{(2)}$ second-harmonic generation (SHG) in periodically poled LN, and combinations thereof. Monolithic 3D integration with tantala opens a new paradigm for scalable, multifunctional photonic systems, enabling visible, near-IR, and nonlinear operation into existing photonic infrastructure.

Figures

Figures reproduced from arXiv: 2509.08092 by Alexa R. Carollo, Atasi Dan, David R. Carlson, Grant M. Brodnik, Grisha Spektor, Jennifer A. Black, Jizhao Zang, Lindell M. Williams, Scott B. Papp.

Figure 1
Figure 1. Figure 1: (a) Direct deposition of tantala onto arbitrary substrates, functionalizing photonic platforms using [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: (a) Process flow for monolithic 3D integrated tantala photonics realized directly on LNOI substrates. [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: (a) Second harmonic test devices in LNOI and tantala-LN wafers. (b) Schematic of LN poling [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: (a) Geometric dispersion engineering and control of [PITH_FULL_IMAGE:figures/full_fig_p007_4.png] view at source ↗

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This paper was first reviewed by deepseek-v4-flash on August 4, 2026.