Paper Citation Record · LEDGER

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN

As of 21 August 2026, this Paper Citation Record lists 16 of 16 outbound references and 0 inbound Pith citation observations for arXiv:2509.08608.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2509.08608 v1

Coverage vector

measured 16 of 16 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-15T16:10:34.696444Z

measured 16 of 16 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-21T06:32:19.484+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

16 of 16 outbound references displayed

verified exact0
verified fuzzy16
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 1e6a11ba-4ed6-4402-894b-288faf02365f · outbound

This paper cites From Cloud RAN to Open RAN,.

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN From Cloud RAN to Open RAN,

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:10:34.911912Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation c12ebaeb-d41d-4fc9-9269-bd99c24225a9 · outbound

This paper cites Intelligent O-RAN Beyond 5G: Architecture, Use Cases, Challenges, and Opportunities,.

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN Intelligent O-RAN Beyond 5G: Architecture, Use Cases, Challenges, and Opportunities,

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:10:34.901095Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 872160b0-c740-4709-b6be-69744c87a48e · outbound

This paper cites QoS aware resource allocation for coexistence mechanisms between eMBB and URLLC: Issues, challenges, and future directions in 5G,.

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN QoS aware resource allocation for coexistence mechanisms between eMBB and URLLC: Issues, challenges, and future directions in 5G,

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:10:34.888496Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 43f3a1af-9056-4ece-8a0a-2a8e88a0da9e · outbound

This paper cites Recommendation ITU-R M.2160-0: Framework and overall objectives of the future development of IMT for 2030 and beyond,.

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN Recommendation ITU-R M.2160-0: Framework and overall objectives of the future development of IMT for 2030 and beyond,

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:10:34.876948Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 3bbb49d8-32cf-4fef-96ce-6b8756eba22c · outbound

This paper cites End-to-end learning for OFDM: From neural receivers to pilotless communication,.

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN End-to-end learning for OFDM: From neural receivers to pilotless communication,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:10:34.864918Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 8b5232a6-fa62-4f80-92ad-222cf23d5739 · outbound

This paper cites Energy-efficient 5G for a Greener Future,.

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN Energy-efficient 5G for a Greener Future,

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:10:34.853338Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 3fdf8240-cc21-4f13-a7ce-8d382335b922 · outbound

This paper cites Ericsson Mobility Report,.

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN Ericsson Mobility Report,

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:10:34.842810Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 4cefe530-7d0a-4826-b41d-d84dbc4b27a8 · outbound

This paper cites MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory,.

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory,

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:10:34.832866Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation b665deb7-5289-4f9d-8644-6c529b3c2ce2 · outbound

This paper cites MiniFloats on RISC-V Cores: ISA Extensions With Mixed-Precision Short Dot Products,.

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN MiniFloats on RISC-V Cores: ISA Extensions With Mixed-Precision Short Dot Products,

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:10:34.821916Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 2f0abfe4-dc44-4085-a3cb-1e61b06efa69 · outbound

This paper cites Enabling Efficient Hybrid Systolic Computation in Shared-L1-Memory Manycore Clusters,.

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN Enabling Efficient Hybrid Systolic Computation in Shared-L1-Memory Manycore Clusters,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:10:34.810917Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 27119cc2-20f8-4ce4-bb35-9977ff325ece · outbound

This paper cites A 1095 pJ/b 219 Mb/s Application-specific Instruction-set Processor for Distributed Massive MIMO in 22FDX,.

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN A 1095 pJ/b 219 Mb/s Application-specific Instruction-set Processor for Distributed Massive MIMO in 22FDX,

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:10:34.798137Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 4370c3c7-23ec-4ca1-baf6-6e5cea7e5d01 · outbound

This paper cites DXT501:An SDR-Based Baseband MP-SoC for Multi-Protocol Industrial Wireless Communication,.

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN DXT501:An SDR-Based Baseband MP-SoC for Multi-Protocol Industrial Wireless Communication,

Reference 12

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:10:34.785182Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 0c6e357a-7042-4983-baf4-ab01dd592509 · outbound

This paper cites A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS,.

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS,

Reference 13

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:10:34.770878Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 6b5b634c-2330-490e-8bf5-a1cdd60b8bda · outbound

This paper cites A 283 pJ/b 240 Mb/s Floating- Point Baseband Accelerator for Massive MU-MIMO in 22FDX,.

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN A 283 pJ/b 240 Mb/s Floating- Point Baseband Accelerator for Massive MU-MIMO in 22FDX,

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:10:34.756622Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation 8715b6b9-b5c6-4bd7-83af-7d0a04a88978 · outbound

This paper cites BayesBB: A 9.6Gbps 1.61ms Configurable All-Message Passing Baseband-Accelerator for B5G/6G Cell-Free Massive-MIMO in 40nm CMOS,.

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN BayesBB: A 9.6Gbps 1.61ms Configurable All-Message Passing Baseband-Accelerator for B5G/6G Cell-Free Massive-MIMO in 40nm CMOS,

Reference 15

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:10:34.742646Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Observation fa20409d-4c64-4e46-aab5-88f40c81bc5b · outbound

This paper cites A 1.96 Gb/s Massive MU-MIMO Detector for Next- Generation Cellular Systems,.

A 410GFLOP/s, 64 RISC-V Cores, 204.8GBps Shared-Memory Cluster in 12nm FinFET with Systolic Execution Support for Efficient B5G/6G AI-Enhanced O-RAN A 1.96 Gb/s Massive MU-MIMO Detector for Next- Generation Cellular Systems,

Reference 16

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T16:10:34.730002Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-21T06:32:19.484+00:00.

Pith citing papers

No inbound Pith citation observations are available.