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REVIEW 3 major objections 6 minor 65 references

Circuit realization and hardware linearization of monotone operator equilibrium networks

T0 review · 3 major / 6 minor · reviewed 2026-08-04 · deepseek-v4-flash

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Pith's one-line read RTGD circuits - resistors, transformers, gyrators, diodes - are exactly ReLU monotone operator equilibrium networks, and their training gradients can be measured in hardware by one unit excitation per resistive device.

desk verdict Solid core, overclaimed converse: the RTGD-to-MonDEQ one-way theorem and hardware linearization are real, but the 'always exists' direction is not proven and the saturation resolvent in VII-B is wrong. read the letter →

arxiv 2509.13793 v2 pith:R3OJHN5T submitted 2025-09-17 eess.SY cs.LGcs.NEcs.SYmath.OC

Thomas Chaffey This is my paper
classification eess.SYcs.LGcs.NEcs.SYmath.OC MSC 68T0794C0547H05
keywords analogneuralnetworksmonotoneoperatorequilibriumresistor-diodecircuitshardwarelinearizationcrossbararraysactivationfunctionsreciprocityimplicitdifferentiation
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that the port behavior of a passive DC circuit built from resistors, transformers, gyrators, and diodes is exactly the fixed-point equation solved by a ReLU monotone operator equilibrium network (MonDEQ), a neural-network architecture that is the infinite-depth limit of weight-tied networks. If this is right, then building such circuits is a direct way to instantiate MonDEQs in analog hardware, and a forward pass happens in a single excitation-and-measurement step. The paper also shows that the gradient of the circuit output with respect to every resistance and conductance can be obtained in hardware by replacing each diode with an open or short circuit and applying one unit excitation per device. That makes in-hardware training possible, and the paper demonstrates it in a device-level circuit simulation. A cascade construction extends the result to non-symmetric weight matrices and to feedforward ReLU networks, and different diode models yield different activation functions, including a smoothed ReLU called the diode ReLU.

What carries the argument

The kernel equation 0 ∈ H z + ψ(z) + B u, y = -C z - D u is the central object: it encodes both the circuit's port behavior and the MonDEQ's fixed-point condition, with H positive semidefinite and ψ the diagonal monotone operator formed by ideal diodes. The forward/backward iteration (I + αψ)^{-1}(I - αH)(z - Bu) turns this inclusion into a ReLU layer, because the resolvent of an ideal diode is the ReLU. Hardware linearization replaces each diode with its derivative at the operating point - open circuit if forward-biased, short circuit if reverse-biased - turning the implicit gradient equation into the kernel equation of a linearized circuit. Reciprocity, the signature symmetry of the hybrid

What would settle it

Synthesize a specific positive semidefinite matrix H that is not signature-symmetric and try to realize it with the RTG construction; failure would break the converse of Corollary 1. Alternatively, measure on a physical reciprocal resistor-diode circuit the gradient by applying unit excitations per device and compare with finite-difference gradients, looking for a systematic mismatch that would invalidate the hardware-linearization formula.

Watch

Extended reading notes

Core claim

The central discovery is a two-way correspondence: the kernel equation of an RTGD network is the set of fixed points of a ReLU MonDEQ, and every ReLU MonDEQ can be realized by such a circuit. The proof maps the circuit's hybrid matrix H, which is positive semidefinite, into the MonDEQ's weight matrix, and the ideal diode's multivalued relation into the ReLU. On the gradient side, hardware linearization replaces each diode at its operating point by either a short or an open circuit; the resulting linear reciprocal network has the property that the derivative of its hybrid matrix with respect to one resistance or conductance is a rank-one outer product of measured responses, so one unit excita

Load-bearing premise

The two-way correspondence rests on the imported classical theorem that every positive semidefinite matrix is realizable as the hybrid matrix of a passive network of ideal resistors, transformers, and gyrators; the hardware-gradient theorem adds the assumption that the circuit is reciprocal, i.e. contains no gyrators.

Editorial extensions

If this is right

  • Every resistor-transformer-gyrator-diode network realizes a ReLU MonDEQ, and every ReLU MonDEQ can be built as such a circuit; a forward pass is a single set of applied excitations.
  • For reciprocal circuits (no gyrators), the gradient of the output with respect to each resistance and conductance is obtained exactly by one unit voltage or current excitation per device and reading the responses.
  • Cascading crossbar arrays with adjustable gains produces non-symmetric weight matrices and recovers feedforward ReLU networks, while a single array gives only symmetric positive-definite weights with nonpositive off-diagonal entries.
  • Replacing ideal diodes with a non-ideal diode model yields a smooth 'diode ReLU' activation, and pairs of voltage-limiting and current-limiting diodes yield saturation activations, so the correspondence extends beyond ReLU.
  • Device-level simulation shows hardware linearization trains almost identically to equilibrium backpropagation on ideal models and is more robust to resistance errors and update noise.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the classical synthesis result invoked in the converse direction holds for every positive semidefinite matrix, then MonDEQs in general - including non-symmetric or non-reciprocal ones - are not just mathematically equivalent to circuits but physically embeddable; testing this on random positive semidefinite matrices would be a cheap falsification.
  • Hardware linearization could make training on memristive crossbars self-calibrating: because the gradient is measured from the actual device states, resistance drift and fabrication tolerances are automatically absorbed, a property that model-based equilibrium backpropagation lacks.
  • The diode ReLU suggests a natural smooth counterpart of ReLU for digital networks, defined through a special function that inverts x e^x; the paper does not test this as a digital activation, but the expression is explicit enough to try.
  • The cascade construction gives a modular recipe for convolutional or other structured MonDEQs in analog hardware; a next step would be to check how non-ideal amplifiers with finite gain affect gradient propagation through deep cascades.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. The paper develops a formal correspondence between circuits made of resistors, transformers, gyrators, and ideal diodes (RTGD networks) and ReLU monotone operator equilibrium networks (MonDEQs). Theorem 1 derives the kernel behavior of an RTGD network as a monotone inclusion with a positive semidefinite matrix and diagonal diode operators. The paper then identifies the fixed points of a forward/backward iteration with this kernel, defines ReLU MonDEQs, and states in Corollary 1 a two-way correspondence. A second thread introduces hardware linearization: replacing diodes by their linearized equivalents lets the derivative of a circuit output with respect to parameters be computed in hardware (Theorems 2 and 3, Corollary 2). Cascades of crossbar arrays are shown to realize feedforward ReLU layers and more general asymmetric networks (Proposition 2, Section VI). Section VII treats non-ideal diodes and Zener-diode saturations, and Section VIII reports ngSPICE simulations of hardware-linearization training.

Significance. If the claims hold, the paper gives a clean bridge between classical circuit synthesis and modern equilibrium deep learning, and hardware linearization is a potentially valuable in-situ training method. The one-way direction (every RTGD network realizes a ReLU MonDEQ) is supported by a self-contained derivation from loop/cutset analysis, and the diode-ReLU and saturation resolvents are explicit and checkable. The device-level ngSPICE simulation is a concrete, falsifiable demonstration that the gradient procedure works with realistic diode models and resistance error. No circularity issue is apparent: the arguments rely on published element-extraction results and a classical synthesis theorem, not on fitted parameters relabeled as predictions. However, the advertised two-way correspondence and the scope of the hardware-training claim are not fully established by the proof as written, as detailed in the major comments.

major comments (3)
  1. [Section IV, Eq. (7)] As printed, the forward/backward update is z_{k+1} = (I+αψ)^{-1}((I-αH)(z_k - Bu)). Substituting a fixed point z_{k+1}=z_k=z gives Hz + ψ(z) + α^{-1}(I-αH)Bu ∋ 0, not Hz + ψ(z) + Bu = 0 as claimed. Thus the statement 'Substitution of a fixed point ... immediately yields (4)' is false for the displayed update. The standard iteration would be z_{k+1} = (I+αψ)^{-1}((I-αH)z_k - αBu), whose fixed points do satisfy (4). Please correct Eq. (7) and adjust the surrounding text accordingly; as written this is a load-bearing inconsistency for Definition 1 and Corollary 1.
  2. [Section IV, Corollary 1] The converse direction is not established. The proof asserts that every positive semidefinite H is the impedance matrix of an RTG network, citing [43, §9.2, p. 373], and concludes that every ReLU MonDEQ has an RTGD realization. But the full MonDEQ kernel (4)-(5) involves B, C, D as well as H, and the extracted hybrid matrix is ~H = -[[D,C],[B,H]] in (6). The cited result is never stated, and no construction is given for the B,C,D blocks or for the sign/passivity constraints of Lemma 1. A realizability theorem for H alone is insufficient. The authors should either state and prove a synthesis result for the whole augmented hybrid matrix, or explicitly weaken the correspondence to the one-way direction RTGD ⇒ MonDEQ throughout the abstract, introduction, and Corollary 1.
  3. [Section VI and Theorem 3] The hardware-gradient result and the realizability claim are not over the same class of circuits. Theorem 3 assumes a reciprocal RTD network (no gyrators) and the experiment in Section VIII uses only resistor-diode crossbar cascades. The converse of Corollary 1, if valid, may require ideal gyrators to realize non-reciprocal MonDEQs, and Section VI itself notes that ideal passive gyrators have not been realized without external fields. Thus the central statements 'every ReLU MonDEQ is realizable as an RTGD circuit' and 'the gradient can be obtained exactly in hardware by one unit excitation per device' are not shown to apply simultaneously. Please clarify the precise scope of each claim, either by proving the full synthesis with gyrators and showing how Theorem 3 extends, or by limiting the claims to reciprocal RTD networks.
minor comments (6)
  1. [Section II] In the definition of the ideal transformer, 'T ∈ R^{n+m}' should be a matrix dimension such as R^{n×m} (or R^{m×n}); the current notation is nonsensical as written.
  2. [Section II, Lemma 1 proof] The sentence 'i is the number of currents in x and i is the number of voltages' should read '... and j is the number of voltages'.
  3. [Section IV, Definition 1] Definition 1 is underspecified: it refers to a fixed point of iteration (7) but omits the input matrix B and the output maps C,D. For a formal correspondence with (4)-(5), the definition should include the full data (H,B,C,D) or explicitly normalize the input.
  4. [Section IV-A] Typo: 'Successsive Over-Relaxation' should be 'Successive Over-Relaxation'.
  5. [Section VII-A] The resolvent of the Shockley model is written 'take the resolvent, (RS + I)^{-1}' where R appears to stand for the Shockley operator. This is likely a typo for (Z_S + I)^{-1}; please make the notation consistent.
  6. [Section VIII] Typo: 'It it also interesting' should be 'It is also interesting'.

Circularity Check

0 steps flagged · score 0.0 of 10

No circular derivation found; the core reductions are self-contained, and the only load-bearing external import (classical RTG synthesis for Corollary 1's converse) is a support gap, not a circular step.

full rationale

The paper's central derivations are self-contained. Theorem 1 obtains the kernel representation (4)-(5) by element extraction and Lemma 1, with a proof given in the paper rather than assumed. The forward direction of Corollary 1 is an algebraic substitution: a fixed point of iteration (7) satisfies (4), so the correspondence between RTGD circuits and ReLU MonDEQs is not definitionally manufactured. The converse direction of Corollary 1 is the one genuinely load-bearing external import: the proof cites [43, Sec. 9.2, p. 373] for the statement that every positive semidefinite H is realizable as the impedance matrix of an RTG network. This is a classical external theorem, not a self-citation, and it is not equivalent to the paper's conclusion. Whether that cited theorem also supplies the full block structure (B, C, D) of the MonDEQ kernel is a completeness/evidence concern, not a circularity: the cited result does not assume the target claim. The hardware linearization results (Theorem 2, Corollary 2, Theorem 3) are derived by implicit differentiation of the kernel equations and by standard sensitivity analysis of reciprocal resistor networks; they do not fit a parameter and then relabel it as a prediction. The ngSPICE experiment is an external simulation check against the ideal model, not circular evidence. The author's prior works [23]-[25] are cited for context and for proof templates, but the proofs in this paper are given substantially in-line, so those citations are not load-bearing. The diode ReLU is derived by taking the resolvent of the Shockley equation, which is a concrete calculation rather than a renaming of a known activation. Overall, no step reduces by construction to its own input.

Assumptions & free parameters 0 free parameters · 6 assumptions · 0 invented entities

No parameters are fitted to data anywhere in the derivations. The theoretical results (kernel representation, resolvent identities, gradient formulas, cascade composition, diode ReLU) are derived from the stated element models. The experiment's settings (100 ohm initial resistances, 5% and 10% noise levels, SPICE diode parameters) are choices, not fitted values used to produce a claimed result. No new physical entities are postulated: the diode ReLU is a derived function (resolvent of the Shockley model), the ideal Zener and CRD devices are textbook circuit models, and the synaptic weights are ideal amplifier gains.

assumptions (6)
  • domain assumption Ideal diode, ideal transformer, ideal gyrator, and LTI resistor are represented as maximal monotone operators with the stated graphs (Section II).
    The entire correspondence depends on these ideal element models. Real diodes deviate; Section VII-A partially addresses this and Section VIII shows empirical robustness.
  • standard math Lemma 1: every RTG network has a hybrid matrix H tilde with H tilde plus H tilde transpose negative semidefinite and the expression H tilde = P - M^T (diag(r,g) - Q)^{-1} M (Section II, eq. 1).
    Proven in-text via fundamental loop and cutset analysis, following [42] and [43]; relies on standard passivity sign conventions.
  • domain assumption Every positive semidefinite H is realizable as the hybrid matrix of an RTG network ([43, Sec. 9.2, p. 373]).
    Imported classical synthesis theorem, not stated or proven in the paper. It carries the converse direction of Corollary 1.
  • standard math The forward/backward iteration converges to a solution of the inclusion when one exists, for a suitably chosen step alpha.
    Standard monotone splitting theory, cited to [20] and [46]. The printed formula (7) has a misplaced input term, but the intended algorithm is standard.
  • domain assumption The Shockley diode equation v = n v_T log(i/i_s + 1) models the non-ideal diode (Section VII-A).
    Imported device model; its resolvent (diode ReLU) is derived, not fitted.
  • domain assumption Ideal amplifiers with gains sigma can connect subcircuits in cascades (Section VI).
    Active elements are assumed ideal; the paper notes that gyrators require active realization.

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Pith. "Pith review of Circuit realization and hardware linearization of monotone operator equilibrium networks." pith.science (2026). https://pith.science/paper/R3OJHN5T

@misc{pith2026250913793,
  author       = {Pith},
  title        = {Pith review of: Circuit realization and hardware linearization of monotone operator equilibrium networks},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/R3OJHN5T}},
  note         = {Machine review of arXiv:2509.13793}
}
read the original abstract

It is shown that the port behavior of a resistor-diode network corresponds to the solution of a ReLU monotone operator equilibrium network (a neural network in the limit of infinite depth), giving a parsimonious construction of a neural network in analog hardware. We furthermore show that the gradient of such a circuit can be computed directly in hardware, using a procedure we call hardware linearization. This allows the network to be trained in hardware, which we demonstrate with a device-level circuit simulation. We extend the results to cascades of resistor-diode networks, which can be used to implement feedforward and other asymmetric networks. We finally show that different nonlinear elements give rise to different activation functions, and introduce the novel diode ReLU which is induced by a non-ideal diode model.

Figures

Figures reproduced from arXiv: 2509.13793 by the authors.

Figure 1
Figure 1. RTGD network with diodes extracted. Precisely, we have the following. Theorem 1. Let C be an m-port RTGD circuit, with n diodes. Then there exist: 1) a partition of the driving point voltages {vk}k=1...m and driving point currents {ik}k=1...m into vectors u, y ∈ R m, 2) vectors i ∈ R p , v ∈ R q , p + q = n, such that, for each diode, either the current through it is in i or the voltage across it is in v, 1These sig… view at source ↗
Figure 2
Figure 2. A crossbar array. Grey edges are resistors. At input ports (left), [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 2
Figure 2. [PITH_FULL_IMAGE:figures/full_fig_p005_2.png] view at source ↗
Figures from the paper (5 more)
Figure 3
Figure 3. Figure 3: The circuit graph of the circuit in Figure 2, with a spanning tree in [PITH_FULL_IMAGE:figures/full_fig_p005_3.png]
Figure 4
Figure 4. Figure 4: Cascade of two crossbar arrays, each configured according to Figure 2. [PITH_FULL_IMAGE:figures/full_fig_p007_4.png]
Figure 5
Figure 5. Figure 5: A crossbar array configured with a common earth terminal for all [PITH_FULL_IMAGE:figures/full_fig_p008_5.png]
Figure 6
Figure 6. Figure 6: , which we call the diode ReLU. As in the case of the ideal diode, a dual diode ReLU mapping current to voltage can be implemented using the admittance of a reverse biased diode. Replacing the ideal diode model with the Shockley equation then gives a realization theore…
Figure 7
Figure 7. Figure 7: Training curves for the experiment of Section VIII. Top: Training [PITH_FULL_IMAGE:figures/full_fig_p011_7.png]

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Pith tools

Reviewed August 4, 2026 · model on record in the stance chip above.