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arxiv: 2509.17617 · v2 · submitted 2025-09-22 · ❄️ cond-mat.mes-hall

Device-scaling constraints imposed by the van der Waals gap formed in two-dimensional materials

Mahdi Pourfath , Tibor Grasser This is my paper

Pith reviewed 2026-05-18 14:51 UTC · model grok-4.3

classification ❄️ cond-mat.mes-hall
keywords two-dimensional materialsvan der Waals gaptransistor scalinggate leakagecontact resistance2D semiconductorsdevice miniaturizationelectrostatic control
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The pith

The van der Waals gap in 2D material devices creates a scaling trade-off that causes many insulators to miss targets and leaves contact resistances too high.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper examines how a van der Waals gap naturally forms at the interfaces between two-dimensional semiconductors and both gate dielectrics and contact metals. This gap acts as a low-dielectric-constant tunneling barrier that cuts down gate leakage but also adds a parasitic series capacitance and raises source and drain contact resistance. The authors calculate the resulting limits on how far transistors can be scaled down while keeping leakage and resistance acceptable. They conclude that many standard insulators do not meet the necessary criteria and that metal contacts to the channel cannot reach the required low resistances. Interfaces without the gap, such as zipper-like bonds, are suggested as a way forward for continued miniaturization.

Core claim

In two-dimensional semiconductors the van der Waals gap that forms at gate-dielectric and metal-contact interfaces functions as a low-dielectric-constant tunneling barrier. This barrier reduces gate leakage yet simultaneously increases contact resistance and introduces parasitic capacitance in series with the gate dielectric, thereby imposing fundamental constraints on electrostatic scaling and contact performance in miniaturized transistors.

What carries the argument

The van der Waals gap modeled as a uniform low-dielectric-constant layer that serves as both a tunneling barrier for leakage and a parasitic capacitance element.

If this is right

  • Many common gate insulators fail to satisfy the combined leakage and capacitance requirements for further scaling.
  • Source and drain contacts to the 2D channel cannot achieve the low resistances needed for high-performance devices.
  • Zipper-like interfaces that eliminate the van der Waals gap through quasi-covalent bonding without dangling bonds enable better scaling.
  • The quantified trade-off shows that leakage suppression comes at the cost of electrostatic and contact limits.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Interface engineering to remove or modify the van der Waals gap could unlock continued scaling in 2D electronics.
  • Similar gap effects may appear in other 2D-material-based devices such as sensors or memory elements.
  • Experimental validation could involve fabricating devices with and without engineered interfaces and measuring actual contact resistances and capacitances against the model predictions.

Load-bearing premise

The van der Waals gap is assumed to form reliably at every relevant interface and to behave as a simple low-dielectric-constant tunneling barrier whose properties can be calculated without extra chemistry or defects.

What would settle it

Fabrication and electrical testing of scaled 2D transistors using different insulators and contact metals to measure whether gate leakage, parasitic capacitance, and contact resistance match the predicted values that cause scaling failure.

read the original abstract

Transistor miniaturization requires controlling gate leakage through ultrathin dielectrics and minimizing source/drain contact resistance. Although two-dimensional (2D) semiconductors offer excellent electrostatic control, their interfaces with gate dielectrics and contact metals often form a van der Waals (vdW) gap that impacts device performance and acts as a tunneling barrier with a low-dielectric constant. While this reduces dielectric leakage, it increases metal-channel contact resistance and introduces a parasitic series capacitance to the gate. We quantified the trade-off between leakage suppression and electrostatic and contact-resistance scaling limits. As a result, many insulators fail to meet scaling targets, and metal-channel contacts fall short of required resistances. Zipper-like interfaces, where quasi-covalent bonding removes the vdW gap without creating dangling bonds, offer a path toward ultrascaled transistor designs.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 2 minor

Summary. The manuscript analyzes how the van der Waals (vdW) gap that forms at interfaces between 2D semiconductors and gate dielectrics or contact metals constrains transistor scaling. It treats the gap as a low-dielectric-constant tunneling barrier that suppresses gate leakage while adding parasitic series capacitance and raising source/drain contact resistance. Quantitative trade-off curves are presented showing that many common insulators fail to meet projected leakage and electrostatic targets and that metal-channel contacts cannot reach the required resistance values. Zipper-like interfaces that eliminate the vdW gap via quasi-covalent bonding are proposed as a route to overcome these limits.

Significance. If the modeling assumptions hold, the work supplies a concrete framework for evaluating dielectric and contact choices in 2D FETs and identifies a clear performance bottleneck that experimental groups would need to address. The suggestion of zipper-like interfaces is constructive and could stimulate targeted interface-engineering studies. The analysis is timely for the 2D-materials device community.

major comments (3)
  1. [§3.1] §3.1 and the leakage model: the vdW gap is treated throughout as a uniform low-k (k≈1.5) tunneling barrier of fixed thickness (≈0.3–0.4 nm) whose properties are independent of the adjacent dielectric or metal. This assumption is load-bearing for the claim that “many insulators fail to meet scaling targets,” yet no material-specific ab initio results or experimental interface data are shown to justify the fixed parameters across the dielectrics examined.
  2. [§4.2] §4.2, contact-resistance scaling: the conclusion that metal-channel contacts fall short of required resistances rests on the same fixed-gap tunneling model. If real interfaces exhibit partial gap closure or chemistry-induced barrier-height changes (as the skeptic note flags), the resistance curves would shift and the quantitative shortfall would need re-evaluation.
  3. [§5] §5, zipper-interface proposal: while conceptually attractive, the manuscript provides no quantitative estimate of the residual barrier height or contact resistance once the vdW gap is removed, leaving the claim that such interfaces “offer a path toward ultrascaled transistor designs” unsupported by numbers.
minor comments (2)
  1. [Figure 2] Figure 2: axis labels and units for the parasitic capacitance contribution are missing; the reader cannot directly compare the plotted values to the ITRS targets cited in the text.
  2. [Notation] Notation: the symbol E_g is used both for the semiconductor band gap and for an effective gap height in the tunneling model; a distinct symbol would improve clarity.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for the constructive and detailed comments, which have helped us clarify the modeling assumptions and improve the presentation of our results. We address each major comment point by point below.

read point-by-point responses

  1. Referee: [§3.1] §3.1 and the leakage model: the vdW gap is treated throughout as a uniform low-k (k≈1.5) tunneling barrier of fixed thickness (≈0.3–0.4 nm) whose properties are independent of the adjacent dielectric or metal. This assumption is load-bearing for the claim that “many insulators fail to meet scaling targets,” yet no material-specific ab initio results or experimental interface data are shown to justify the fixed parameters across the dielectrics examined.

    Authors: The vdW gap parameters are representative averages drawn from multiple experimental reports (AFM, TEM, and capacitance measurements) on 2D interfaces, as cited in Section 2. While we recognize that interface-specific chemistry can introduce variations, the fixed values enable identification of general scaling trends that apply across a range of common dielectrics. In the revised manuscript we have added a dedicated sensitivity paragraph in §3.1 that quantifies how ±0.1 nm or ±0.5 changes in gap thickness and dielectric constant shift the leakage curves, together with additional citations to ab initio interface studies that support the chosen averages. revision: partial

  2. Referee: [§4.2] §4.2, contact-resistance scaling: the conclusion that metal-channel contacts fall short of required resistances rests on the same fixed-gap tunneling model. If real interfaces exhibit partial gap closure or chemistry-induced barrier-height changes (as the skeptic note flags), the resistance curves would shift and the quantitative shortfall would need re-evaluation.

    Authors: We agree that partial gap closure or chemistry-driven barrier modifications can occur in practice. Our analysis deliberately retains the conservative fixed-gap assumption to highlight the intrinsic limit imposed by a persistent vdW gap. The revised §4.2 now includes a short discussion of how such deviations would move the resistance curves and cites recent experimental demonstrations of interface-engineered contacts that achieve lower resistances, thereby framing the quantitative shortfall as a benchmark rather than an absolute prediction. revision: partial

  3. Referee: [§5] §5, zipper-interface proposal: while conceptually attractive, the manuscript provides no quantitative estimate of the residual barrier height or contact resistance once the vdW gap is removed, leaving the claim that such interfaces “offer a path toward ultrascaled transistor designs” unsupported by numbers.

    Authors: The zipper-like interface is offered as a conceptual route whose primary benefit is the elimination of the tunneling barrier and parasitic capacitance. Specific residual barrier heights and contact resistances would require material-pair-specific first-principles calculations that lie outside the scope of the present work, which focuses on quantifying the constraints created by the vdW gap itself. In the revised §5 we have added references to recent experimental reports of quasi-covalent 2D interfaces that show reduced effective barriers and clarified that the proposal is intended to motivate targeted follow-on modeling and device studies rather than to supply ready-to-use numerical targets. revision: partial

Circularity Check

0 steps flagged

No significant circularity in derivation chain

full rationale

The paper models the van der Waals gap as a low-k tunneling barrier at 2D material interfaces and quantifies trade-offs between leakage suppression, electrostatic scaling, and contact resistance under that model. The abstract and described approach state the gap-formation assumption explicitly as an input rather than deriving it from the scaling conclusions. No equations, predictions, or steps reduce the quantified limits to fitted parameters by construction, nor do they rely on self-citation chains or imported uniqueness theorems for the central claims. The results about insulator failures and contact shortfalls follow from applying the stated barrier model to scaling targets, remaining self-contained against external physical benchmarks and without circular equivalence to the inputs.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

Based on abstract only; the central claim rests on the domain assumption that vdW gaps form at typical interfaces and dominate tunneling and capacitance behavior.

axioms (1)
  • domain assumption A van der Waals gap forms at interfaces between 2D semiconductors and gate dielectrics or contact metals and functions as a low-dielectric-constant tunneling barrier.
    Stated directly in the abstract as the starting point for the trade-off analysis.

pith-pipeline@v0.9.0 · 5670 in / 1243 out tokens · 41298 ms · 2026-05-18T14:51:37.448172+00:00 · methodology

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