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REVIEW 4 major objections 5 minor 1 cited by

A compiled Mølmer-Sørensen gate reaches 92.47% process fidelity on a superconducting processor, landing within 0.55 percentage points of the device's native CNOT gate, evidence that non-native entangling gates can be made hardware-competiti

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An MS gate compiled to one CNOT plus single-qubit rotations achieves 92.47% process fidelity on an IBM superconducting processor, roughly matching the native CX's 93.02%.

T0 review reviewed 2026-08-04 challenge →

load-bearing objection Standard KAK compilation plus a single QPT benchmark; the QPT is unvalidated and the CX baseline is uncontrolled, so the parity claim doesn't hold. the 4 major comments →

arxiv 2510.07352 v1 pith:I3QS3OE5 submitted 2025-10-08 quant-ph

A Hardware-Efficient M{\o}lmer-S{\o}rensen Gate for Superconducting Quantum Computers

M. AbuGhanem This is my paper
classification quant-ph PACS 03.67.Lx03.67.-a03.65.Ca
keywords Mølmer-Sørensen gatesuperconducting quantum processorquantum process tomographygate compilationentangling gateCNOTNISQprocess fidelity
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to establish that a non-native entangling gate, the Mølmer-Sørensen (MS) gate from trapped-ion quantum computing, can be compiled onto a fixed-architecture superconducting processor without paying the usual fidelity penalty. The authors decompose the MS unitary into a circuit using only one CNOT plus single-qubit rotations, and benchmark it with quantum process tomography. They report a hardware process fidelity of 92.47%, compared with 93.02% for the device's native CX gate, and a 94.2% success probability for preparing the Bell state from |00> on real hardware. If correct, this shows that hardware-aware compilation can expand the effective gate set on NISQ devices, giving algorithm designers more entangling primitives that perform on par with native operations.

Core claim

The central claim is that the Mølmer-Sørensen gate, a maximally entangling operation locally equivalent to CNOT, can be implemented on a superconducting processor by compiling it into the native gate set {RZ, √X, CNOT} using exactly one CNOT gate, and that this implementation is high-fidelity. Quantum process tomography on real hardware gives 92.47% process fidelity for the MS gate versus 93.02% for the native CX gate; the noiseless simulator gives 96.86% versus 97.89%. For the input |00>, the gate produces the Bell state (|00>+i|11>)/√2 with 94.2% subspace success probability. The paper interprets the small fidelity gap as evidence that non-native gates can be optimized to rival hardware-na

What carries the argument

The key machinery is the hardware-efficient compilation of the MS unitary into a single-CNOT circuit, with specific rotation angles chosen to enact the MS transformation while respecting qubit connectivity. This minimal-depth decomposition is what keeps error accumulation low enough for the compiled gate to approach native-gate fidelity. The paper also uses quantum process tomography to reconstruct the process matrix and compute process fidelity as the benchmark, comparing the compiled MS gate against the device's native CX gate.

Load-bearing premise

The central claim collapses if the MS gate and the native CX gate were not benchmarked on the same physical qubit pair, because the small fidelity gap could then be caused by different qubit noise rather than comparable gate quality.

What would settle it

Re-benchmark the compiled MS gate and the native CX gate on the same identified qubit pair under the same calibration, and also verify that a noiseless statevector simulation reconstructs the MS process with fidelity 1.0 when sufficient measurement shots are used; if either test fails, the claimed parity is not established.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

If this is right

  • Non-native entangling gates compiled with minimal circuit depth can match hardware-native gate fidelity on current NISQ processors.
  • Quantum compiler designs can treat any efficiently compilable unitary as a potential primitive rather than restricting algorithms to the native gate set.
  • The single-CNOT decomposition provides a template for porting other trapped-ion-style entangling operations to superconducting architectures.
  • Quantum process tomography can serve as a cross-platform benchmarking protocol for comparing gates from different hardware modalities.
  • The 5.8% state-preparation infidelity quantifies the error budget that algorithm designers must account for when scaling circuits that use the compiled MS gate.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The paper does not identify which physical qubit pair was used for either QPT benchmark, so the 0.55-point gap may reflect qubit quality or readout errors rather than a genuine parity between the compiled MS gate and the native CX gate; a same-pair, same-calibration re-measurement would settle this.
  • A noiseless statevector simulator producing 96.86% process fidelity is unexpectedly far from 100%; if this deviation is not fully explained by finite-shot tomographic sampling, it would indicate the compiled circuit is not exactly equivalent to the ideal MS unitary, which would alter the interpretation of the hardware result.
  • Because process tomography includes state-preparation and measurement errors, an interleaved randomized-benchmarking measurement of the compiled MS gate would give a cleaner estimate of its true gate fidelity and would be a natural next test.
  • The same compilation strategy could be applied to other unitaries locally equivalent to CNOT, such as the iSWAP gate, to check whether parity with native gates is a general feature of single-CNOT decompositions or specific to the MS gate.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper reports a compilation of the two-qubit Mølmer-Sørensen (MS) gate into the native gate set {RZ, √X, CNOT} using only a single CNOT, and claims a hardware process fidelity of 92.47% on IBM's ibm_nairobi processor, which is presented as competitive with the 93.02% fidelity of the native CX gate. The authors perform direct population measurements on the |00⟩ input (94.2% success probability into the {|00⟩,|11⟩} subspace) and full quantum process tomography on both a noiseless simulator and the real device. They also provide device-parameter tables and a stability analysis across two experimental campaigns. The central claim is that a non-native, hardware-compiled entangling gate can perform on par with a native gate in the NISQ regime.

Significance. If the claimed result were fully substantiated, it would be a useful data point for quantum compiler design, showing that a two-qubit gate locally equivalent to CNOT can be executed with a single-CNOT decomposition and with fidelity close to that of the native CNOT. The paper's approach—direct QPT on compiled circuits and on a simulator—is methodologically appropriate in spirit, and the inclusion of device characterization data is a strength. However, the significance is substantially tempered by the fact that U_MS is locally equivalent to CNOT and the compiled circuit contains exactly one CNOT; the observed near-parity with native CX is therefore partially expected. Moreover, as detailed below, the experimental evidence as presented is not yet sufficient to establish even this modest claim reliably.

major comments (4)
  1. [Section III.B / Fig. 3(b)] The noiseless-simulator QPT result F_sim = 96.86% is presented as validating the compilation, with the 3.14% gap attributed to finite sampling. With 4,000 shots per measurement setting and 16 input states (or even the 9 nontrivial Pauli settings), the finite-sample standard deviation of the estimated process fidelity is well under 1%; a 3.14% shortfall is far outside normal sampling fluctuations. This indicates a systematic bias in the tomographic reconstruction pipeline (e.g., in state preparation, readout calibration, or the CPTP projection step). Since the same pipeline is used for the hardware data, the 92.47% hardware fidelity cannot be treated as an unbiased estimate of the implemented process. The authors should validate the QPT protocol on a known ideal process, report statistical error bars (e.g., via bootstrapping or repeated runs), and reconcile the simulator discrepancy befor
  2. [Section III.B / Table II / ref. [46]] The native CX hardware fidelity of 93.02% is not measured in this work but is cited from reference [46], an unpublished self-cited manuscript. The paper does not state which physical qubit pair was used for the MS-gate QPT, nor the pair or calibration conditions underlying the CX benchmark. Tables I and III list parameters for all seven qubits, but no pair is identified. Since CX fidelity varies significantly across qubit pairs and over time, the 0.55-percentage-point gap between the MS and CX values may reflect qubit quality or calibration drift rather than the compilation strategy. The central comparison must be made by measuring the native CX gate on the same qubit pair, in the same calibration window, with the same QPT protocol.
  3. [Section III.A / Fig. 2] The Bell-state validation only reports populations in the computational basis, P00 + P11 = 94.2%. This metric is insensitive to coherence: a fully dephased mixture 0.5|00⟩⟨00| + 0.5|11⟩⟨11| would also yield the same population-based 'success probability' if the populations are 0.494 and 0.448. The claim that this result 'confirms the correct logical operation' is therefore unsupported. The authors should report the full two-qubit density matrix from state tomography, or at least a parity scan/entanglement witness, to confirm the coherences required for Bell-state generation.
  4. [Section II.A / Fig. 1] The paper does not provide the explicit decomposition: no rotation angles for the RZ(θ) gates or the √X gates are given, and the circuit diagram in Fig. 1 is only a placeholder (the actual figure is not embedded in the text). This makes it impossible for a reader to verify the claimed single-CNOT decomposition, to reproduce the experiment, or to assess whether the implemented unitary actually matches U_MS in Eq. (1). The full transpiled circuit and all rotation angles should be provided in the text or an appendix.
minor comments (5)
  1. [Section III.A] The ideal Bell state for the |00⟩ input is written as (|00⟩+|11⟩)/√2, but Eq. (1) and Section II.B give (|00⟩+i|11⟩)/√2. The phase is relevant for the process fidelity; this inconsistency should be corrected.
  2. [Section II.C] The text refers to 'statevector simulator (qasm simulator)' inconsistently; a qasm_simulator is a sampling simulator, not a statevector simulator. The exact simulator type and any noise model used should be clarified.
  3. [General] The manuscript contains multiple duplicated passages, repeated figure and table captions, and typos (e.g., 'charechtersistics', 'gate gate', 'hardware performnace'). A thorough editorial pass is needed, and all figures should be properly embedded.
  4. [Table II] The column headers 'F QPT Process (Simulator)' and 'F QPT Process (Hardware)' are awkwardly formatted; the fidelity metric should be defined explicitly (e.g., process fidelity relative to U_MS) and the number of significant figures should be consistent.
  5. [Reference [46]] Reference [46] is cited as the source of the native CX fidelity but is an unpublished manuscript with no journal, arXiv identifier, or year. If this work is publicly available, a complete citation should be provided; otherwise the baseline is unverifiable.

Circularity Check

1 steps flagged

The MS-gate fidelity is an independent measurement, but the headline 'competitive with native CX' borrows its 93.02% CX baseline from a self-cited reference [46] rather than from a same-run comparison, making part of the central claim load-bearing on self-citation.

specific steps
  1. self citation load bearing [Section III.B, Table II, Refs [46]]
    "As summarized in Table II, this performance is directly comparable to the 93.02% fidelity of the device’s native CX gate [46]."

    The paper's comparative conclusion ('performance competitive with the native CX gate') depends on a native-CX process fidelity of 93.02% that is not measured in this study; it is imported from reference [46], a 2025 work by the same author. The paper gives no same-qubit-pair, same-calibration CX measurement, so the parity claim rests on a self-cited external number rather than on the present experimental data. The MS fidelity itself is independently measured, so the circularity is partial rather than total.

full rationale

The core compilation step — decomposing U_MS into RZ, sqrt(X), and one CNOT — is not fitted to the QPT data, and no parameter is extracted from the fidelity results to predict another closely related quantity. The simulator fidelities are presented as validation, but they are not part of a circular derivation; their unexplained deficit (96.86% in a noiseless simulation) is a correctness/validation concern, not a circularity one. The main circularity-adjacent issue is that the abstract and conclusion claim parity with the native CX gate using a 93.02% fidelity taken from reference [46], a self-cited prior work, without an in-house controlled CX benchmark. Because the MS-gate measurement itself is new and independent, the overall score is moderate.

Axiom & Free-Parameter Ledger

1 free parameters · 4 axioms · 0 invented entities

No new entities or fitted parameters are introduced; the main unstated inputs are the decomposition angles and the self-cited CX fidelity.

free parameters (1)
  • Single-qubit rotation angles {θ_i} = not reported
    The circuit decomposition depends on specific RZ(θ) and sqrt(X) angles to implement U_MS; the paper states these were 'calculated' but never lists them, so exact replication is impossible.
axioms (4)
  • standard math Any two-qubit gate locally equivalent to CNOT can be synthesized with one CNOT plus single-qubit rotations (Cartan/KAK decomposition).
    Invoked implicitly in Section II A to justify the one-CNOT circuit; not proven or cited.
  • domain assumption The unitary U_MS in Eq. (1) is the standard Mølmer-Sørensen gate.
    The paper defines it without derivation; this matrix is the standard MS unitary up to local phases.
  • standard math QPT with CPTP projection gives an unbiased estimator of process fidelity.
    Relied on in Section II C; no discussion of estimator bias or uncertainty.
  • ad hoc to paper The native CX process fidelity of 93.02% cited from [46] is accurate and measured under comparable conditions.
    The benchmark comparator comes from the author's own self-cited reference; no independent measurement is shown in this paper.

reviewed 2026-08-04 · how reviews work

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Cite this review

Pith. "Pith review of A Hardware-Efficient M{\o}lmer-S{\o}rensen Gate for Superconducting Quantum Computers." pith.science (2026). https://pith.science/paper/I3QS3OE5

@misc{pith2026251007352,
  author       = {Pith},
  title        = {Pith review of: A Hardware-Efficient M\olmer-S\orensen Gate for Superconducting Quantum Computers},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/I3QS3OE5}},
  note         = {Machine review of arXiv:2510.07352}
}
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abstract

The M{\o}lmer-S{\o}rensen gate, a cornerstone entangling operation in trapped-ion systems, represents a promising alternative to standard entangling gates in superconducting quantum architectures. However, its performance on superconducting hardware has remained unverified. In this work, we present a hardware-efficient implementation of the M{\o}lmer-S{\o}rensen gate and characterize its performance using quantum process tomography (QPT) on IBM Quantum's superconducting processors. Our implementation achieves a process fidelity of 92.47\% on the real quantum hardware, a performance competitive with the 93.02\% fidelity of the device's native controlled-NOT (CX) gate. Furthermore, for the $|00\rangle$ input state, the gate prepares the target Bell state with $94.2\%$ success probability, confirming its correct logical operation. These results demonstrate that non-native entangling gates can be optimized to perform on par with hardware-native operations. This work expands the effective gate set for algorithm design on fixed-architecture processors and provides a critical benchmark for cross-platform gate evaluation, underscoring the role of hardware-aware compilation in advancing noisy intermediate-scale quantum (NISQ) computing.

Figures

Figures reproduced from arXiv: 2510.07352 by M. AbuGhanem.

Figure 2
Figure 2. Figure 2: FIG. 2. Measurement-based validation of the Mølmer-Sørensen gate on a superconducting quantum process tfthit tt|00⟩iltfiltilt(bl) d hd ities, and state preparation and measurement (SPAM) errors. The variation in T2 times (22–143 TABLE II. Performance comparison of nati twoqubit gatesProcess fidelities for the [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. Quantum process tomography of the Mølmer-Sørensen gate. Reconstructed process matrices (Choi matrices) from (a) Idl thtil ti(F CZ 10)(b) ililti(fidlit0969)d () hdti FIG. 3. Quantum process tomography of the Mølmer-Sørensen gate. Reconstructed process matrices (Choi matrices) from (a) [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. Comprehensive stability analysis of superconducting quantum processor performance across experimental campaigns. FIG. 4. Comprehensive stability analysis of superconducting quantum processor performance across experimental campaigns. [PITH_FULL_IMAGE:figures/full_fig_p006_4.png] view at source ↗

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This paper was first reviewed by deepseek-v4-flash on August 4, 2026.