pith. sign in

arxiv: 2510.10521 · v3 · submitted 2025-10-12 · ❄️ cond-mat.mtrl-sci

A ferroelectric junction transistor memory made from switchable van der Waals p-n heterojunctions

Baoyu Wang , Lingrui Zou , Tao Wang , Lijun Xu , Zexin Dong , Chuan Qin , Xin He , Shangui Lan
show 13 more authors
Yinchang Ma Meng Tang Maolin Chen Chen Liu Zheng-Dong Luo Lijie Zhang Zhenhua Wu Yan Liu Genquan Han Bin Yu Xixiang Zhang Kai Chang Fei Xue
This is my paper

Pith reviewed 2026-05-18 07:57 UTC · model grok-4.3

classification ❄️ cond-mat.mtrl-sci
keywords van der Waals heterojunctionferroelectric memoryp-n junctionjunction field-effect transistorneuromorphic computingband alignment2D materialsSnSe In2Se3
0
0 comments X

The pith

Switchable van der Waals p-n heterojunctions from SnSe and ferroelectric In2Se3 create a new junction transistor memory with 1.8 V windows and 100 ns speed.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper shows that pairing p-type SnSe with n-type ferroelectric alpha-In2Se3 produces high-quality van der Waals p-n heterojunctions that exhibit very low reverse leakage of 0.1 pA and a diode ideality factor near 1.95. Ferroelectric polarization switching tunes the band alignment and changes the junction barrier height by as much as 900 meV. These tunable junctions are then used to construct a ferroelectric junction field-effect transistor memory that delivers a 1.8 V memory window, 100 ns write speed, stable operation up to 393 K, and only 2 percent cycle-to-cycle variation. The same devices also display synaptic weight updates, pointing toward low-power neuromorphic applications.

Core claim

Using band-aligned p-type SnSe and n-type ferroelectric α-In2Se3, the authors realize near-ideal vdW p-n heterojunctions with 0.1 pA reverse leakage and an ideality factor of 1.95. Ferroelectric switching produces a 900 meV barrier modulation. From these switchable junctions they build and characterize a ferroelectric junction field-effect transistor memory that exhibits 1.8 V memory windows, 100 ns operation, reliable performance at 393 K, 2 percent cycle-to-cycle variation, and synaptic characteristics suitable for neuromorphic computing.

What carries the argument

Ferroelectric-tuned band alignment at the SnSe/α-In2Se3 vdW p-n interface, which modulates the junction barrier height by up to 900 meV to control current flow for memory states.

If this is right

  • The 1.8 V memory windows enable reliable binary or multi-level storage.
  • 100 ns switching supports high-speed read and write operations.
  • Stable function at 393 K extends usability to elevated-temperature environments.
  • 2 percent cycle-to-cycle variation allows consistent performance across many cycles.
  • Synaptic characteristics support direct implementation in low-power neuromorphic circuits.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The low leakage current could enable dense arrays with reduced static power in future integrated circuits.
  • Combining this junction approach with other 2D semiconductors might yield hybrid logic-memory elements on a single platform.
  • Longer-term endurance tests beyond the reported cycles would be needed to assess suitability for non-volatile storage.
  • The giant barrier modulation may be useful for reconfigurable optoelectronic devices that change response with ferroelectric state.

Load-bearing premise

The heterojunctions keep near-ideal diode behavior and ferroelectric switching intact without major interface traps or degradation over the reported cycles and temperatures.

What would settle it

An observed rise in reverse leakage above 0.1 pA or a clear increase in ideality factor after repeated cycling at 393 K would show the device stability claim does not hold.

read the original abstract

Van der Waals (vdW) p-n heterojunctions are important building blocks for advanced electronics and optoelectronics, in which high-quality heterojunctions essentially determine device performances or functionalities. Creating tunable depletion regions with substantially suppressed leakage currents presents huge challenges, but is crucial for heterojunction applications. Here, by using band-aligned p-type SnSe and n-type ferroelectric {\alpha}-In2Se3 as a model, we report near-ideal multifunctional vdW p-n heterojunctions with small reverse leakage currents (0.1 pA) and a desired diode ideality factor (1.95). We realize ferroelectric-tuned band alignment with a giant barrier modulation of 900 meV. Based on such tunable heterojunctions, we propose and demonstrate a fundamental different memory device termed ferroelectric junction field-effect transistor memory, which shows large memory windows (1.8 V), ultrafast speed (100 ns), high operation temperature (393 K), and low cycle-to-cycle variation (2%). Additionally, the reliable synaptic characteristics of these memory devices promise low-power neuromorphic computing. Our work provides a new device platform with switchable memory heterojunctions, applicable to high performance brain-inspired electronics and optoelectronics.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper reports fabrication of van der Waals p-n heterojunctions from p-type SnSe and n-type ferroelectric α-In2Se3 that exhibit low reverse leakage (0.1 pA) and a diode ideality factor of 1.95. Ferroelectric polarization is used to tune the band alignment, producing a 900 meV barrier modulation. The authors introduce and demonstrate a ferroelectric junction field-effect transistor memory device that achieves a 1.8 V memory window, 100 ns switching, operation up to 393 K, and 2% cycle-to-cycle variation, together with synaptic characteristics for neuromorphic computing.

Significance. If the central claims are substantiated, the work establishes a new device platform that integrates ferroelectric switching directly into a vdW heterojunction for memory and synaptic functions. The combination of large barrier modulation, high-temperature operation, and low variation would be a meaningful advance for 2D-material-based neuromorphic electronics, provided the memory effect is shown to originate from polarization rather than interface traps.

major comments (2)
  1. [p-n heterojunction electrical characterization] The reported ideality factor of 1.95 (close to 2) is consistent with Shockley-Read-Hall recombination through interface states. In the electrical characterization of the SnSe/α-In2Se3 junction, this raises the possibility that hysteresis used to extract the 1.8 V memory window and 900 meV barrier shift could arise from charge trapping rather than pure ferroelectric polarization modulation. Temperature-dependent I-V or admittance spectroscopy data are needed to distinguish these mechanisms.
  2. [ferroelectric junction field-effect transistor memory demonstration] The memory metrics (1.8 V window, 100 ns speed, 393 K operation, 2% variation) are presented without accompanying statistical distributions, error bars, or device-to-device yield data. In the ferroelectric junction transistor memory section, it is therefore unclear whether the quoted performance reflects typical behavior or post-selection of best devices.
minor comments (2)
  1. [Abstract] The abstract contains the phrase 'fundamental different'; this should read 'fundamentally different'.
  2. [Figures and captions] Figure captions should explicitly label the measurement geometry, contact configuration, and any post-fabrication annealing steps to allow direct comparison with the reported leakage and ideality values.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the thorough and constructive review of our manuscript. We have carefully addressed the concerns regarding the possible role of interface traps versus ferroelectric polarization and the need for statistical presentation of device metrics. Our point-by-point responses and planned revisions are detailed below.

read point-by-point responses

  1. Referee: The reported ideality factor of 1.95 (close to 2) is consistent with Shockley-Read-Hall recombination through interface states. In the electrical characterization of the SnSe/α-In2Se3 junction, this raises the possibility that hysteresis used to extract the 1.8 V memory window and 900 meV barrier shift could arise from charge trapping rather than pure ferroelectric polarization modulation. Temperature-dependent I-V or admittance spectroscopy data are needed to distinguish these mechanisms.

    Authors: We appreciate the referee highlighting the ambiguity that can arise from an ideality factor near 2. While we acknowledge that interface states can contribute to recombination, the 900 meV barrier modulation we report is substantially larger than shifts typically attributable to charge trapping in vdW heterojunctions. The hysteresis direction and magnitude are directly tied to the ferroelectric polarization reversal in α-In2Se3, consistent with the PFM characterization included in the manuscript. To rigorously address this point, we will incorporate temperature-dependent I-V measurements in the revised manuscript. These data will enable extraction of activation energies and temperature dependence of the memory window, allowing clearer differentiation between ferroelectric switching and thermally activated trap processes. revision: yes

  2. Referee: The memory metrics (1.8 V window, 100 ns speed, 393 K operation, 2% variation) are presented without accompanying statistical distributions, error bars, or device-to-device yield data. In the ferroelectric junction transistor memory section, it is therefore unclear whether the quoted performance reflects typical behavior or post-selection of best devices.

    Authors: We agree that robust statistical reporting is necessary to establish the reproducibility of the device performance. In the revised manuscript, we will add error bars (standard deviation from repeated measurements), histograms or distributions of key metrics across multiple devices, and device-to-device yield information from a larger fabrication batch. This will demonstrate that the reported values (1.8 V window, 100 ns switching, etc.) represent typical rather than best-case performance. revision: yes

Circularity Check

0 steps flagged

No circularity: experimental device metrics are measured, not derived

full rationale

This is an experimental materials and device paper reporting fabricated SnSe/α-In2Se3 vdW heterojunctions and measured transistor-memory characteristics. The central claims (1.8 V memory window, 100 ns speed, 393 K operation, 2% variation, 900 meV barrier modulation) are presented as direct electrical and structural characterization results rather than outputs of any internal equations, fitted models, or self-referential derivations. No load-bearing steps reduce to self-definition, fitted inputs renamed as predictions, or uniqueness theorems imported via self-citation. The derivation chain is therefore self-contained against external benchmarks of device fabrication and I-V testing.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

The central claims rest on the experimental realization of high-quality vdW interfaces and reversible ferroelectric polarization switching; no explicit free parameters or invented entities are stated in the abstract.

pith-pipeline@v0.9.0 · 5820 in / 988 out tokens · 23480 ms · 2026-05-18T07:57:55.564268+00:00 · methodology

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

21 extracted references · 21 canonical work pages

  1. [1]

    & Peng, L

    Jiang, J., Xu, L., Qiu, C. & Peng, L. M. Ballistic two - dimensional InSe transistors. Nature 616 , 470 - 475 (2023). 2

    work page 2023

  2. [2]

    Zhang, E. et al. ReS 2 ‐ b ased f ield‐ e ffect t ransistors and p hotodetectors. Adv . Funct . Mater . 25 , 4076 - 4082 (2015). 3 . Zh ao, S. et al. Fractional quantum Hall phases in high - mobility n - type molybdenum disulfide transistors. Nat. Electron. 7 , 1117 - 1125 (2024). 4

    work page 2015

  3. [3]

    Wang, X. et al. Van der Waals negative capacitance transistors. Nat . Commun . 10 , 3037 (2019). 5

    work page 2019

  4. [4]

    Si, M. et al. Steep - slope hysteresis - free negative capacitance MoS 2 transistors. Nat . Nanotechnol . 13 , 24 - 28 (2018). 6

    work page 2018

  5. [5]

    Wu, G. et al. Ferroelectric - defined reconfigurable homojunctions for in - memory sensing and computing. Nat . Mater . 22 , 1499 - 1506 (2023). 7 . Kim , K. H. et al. Scalable CMOS back - end - of - line - compatible AlScN/two - dimensional channel ferroelectric field - effect transistors. Nat . Nanotechnol . 18 , 1044 - 1050 (2023). 8

    work page 2023

  6. [6]

    Xian, Z. et al. 2D f erroelectric m etal – o rganic f rameworks for u ltralow p ower f ield e ffect t ransistors. Adv . Funct . Mater . 35 , 2409388 (2024). 9

    work page 2024

  7. [7]

    & Park, J

    Park, S., Lee, D., Kang, J., Choi, H. & Park, J. H. Laterally gated ferroelectric field effect transistor (LG - FeFET) using α - In 2 Se 3 for stacked in - memory computing array. Nat . Commun . 14 , 6 778 (2023). 10

    work page 2023

  8. [8]

    Wang, X. et al. Van der Waals engineering of ferroelectric heterostructures for long - retention memory. Nat . Commun . 12 , 1109 (2021). 11

    work page 2021

  9. [9]

    Wang, S. et al. Two - dimensional ferroelectric channel transistors integrating ultra - fast memory and neural computing. Nat . Commun . 12 , 53 (2021). 12

    work page 2021

  10. [10]

    Chen, Y . et al. Highly l inear and s ymmetric s ynaptic m emtransistors b ased on p olarization s witching in t wo - d imensional f e rroelectric s emiconductors. Small 18 , e2203611 (2022). 13

    work page 2022

  11. [11]

    Han, W. et al. Phase - controllable large - area two - dimensional In 2 Se 3 and ferroelectric heterophase junction. Nat . Nanotechnol . 18 , 55 - 63 (2023). 14

    work page 2023

  12. [12]

    Lim, T. et al. Large - a rea g rowth of f erroelectric 2D γ - In 2 Se 3 s emiconductor by s pray p yrolysis for n ext - g eneration m emory. Adv . Mater . 36 , e2308301 (2024). 15

    work page 2024

  13. [13]

    Lee, S. et al. Low - temperature processed beta - phase In 2 Se 3 ferroelectric semiconductor thin film transistors. 2D Materials 9 , 025023 (2022). 16

    work page 2022

  14. [14]

    Yang, T. H. et al. Ferroelectric transistors based on shear - transformation - mediated rhombohedral - stacked molybdenum disulfide. Nat . Electron . 7 , 29 - 38 (2023). 1 7

    work page 2023

  15. [15]

    Wang, H. et al. Junction f ield‐ e ffect t ransistors b ased on PdSe 2 / MoS 2 h eterostructures for p hotodetectors s howing h igh r esponsivity and d etectivity. Adv . Funct . Mater . 31 , 2106105 (2021). 1 8

    work page 2021

  16. [16]

    Guo, J. et al. SnSe/MoS 2 van der Waals h eterostructure j unction f ield - e ffect t ransistors with n early i deal s ubthreshold s lope. Adv . Mater . 31 , e1902962 (2019). 1 9

    work page 2019

  17. [17]

    Lim, J. Y . et al. Van der Waals junction field effect transistors with both n - and p - channel transition metal dichalcogenides. npj 2D Mater. Appl. 2 , 37 (2018). 20

    work page 2018

  18. [18]

    Kim, Y . H. et al. Boltzmann s witching MoS 2 m etal - s emiconductor f ield - e ffect t ransistors e nabled by m onolithic - o xide - g apped m etal g ates at the Schottky - Mott l imit. Adv . Mater . 36 , e2314274 (2024). 47 / 47 2 1

    work page 2024

  19. [19]

    Jeon, P. J. et al. Black p hosphorus - z inc o xide n anomaterial h eterojunction for p - n d iode and j unction f ield - e ffect t ransistor. Nano Lett . 16 , 1293 - 1298 (2016). 2 2

    work page 2016

  20. [20]

    Shin, H. G. et al. Vertical and i n - p lane c urrent d evices u sing NbS 2 /n - MoS 2 van der Waals Schottky j unction and g raphene c ontact. Nano Lett . 18 , 1937 - 1945 (2018). 2 3

    work page 1937

  21. [21]

    Seo, S. et al. Artificial van der Waals hybrid synapse and its application to acoustic pattern recognition. Nat . Commun . 11 , 3936 (2020)

    work page 2020