Pith. sign in

REVIEW 3 major objections 5 minor 91 references

BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement

T0 review · 3 major / 5 minor · reviewed 2026-08-04 · deepseek-v4-flash

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

Pith's one-line read This paper introduces the first benchmark built specifically for black-box optimization in chip placement and provides evidence that BBO configurations can match or beat analytical and reinforcement-learning placers on wirelength.

desk verdict Useful benchmark, but the 'BBO beats analytical' headline rests on HPO tuning DREAMPlace itself. read the letter →

arxiv 2510.23472 v2 pith:RATSBHTN submitted 2025-10-27 cs.LG cs.AIcs.ARcs.NE

Ke Xue , Ruo-Tong Chen , Rong-Xi Tan , Xi Lin , Yunqi Shi , Siyuan Xu , Mingxuan Yuan , Chao Qian This is my paper · ORCID
classification cs.LGcs.AIcs.ARcs.NE
keywords black-boxoptimizationchipplacementmacroglobalwirelengthbenchmarkevolutionaryalgorithmshyperparameter
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Black-box optimization (BBO) has been applied to chip placement for decades, but early formulations were too weak to compete with analytical placers. This paper argues that recent BBO formulations change that, and it introduces a benchmark to make the case testable: BBOPlace-Bench, which unifies three problem formulations—sequence pair, mask-guided optimization, and hyperparameter optimization—under one evaluation protocol on industrial chip cases. Under that protocol, the mask-guided and hyperparameter formulations outperform the permutation-based sequence pair, and evolutionary algorithms (Vanilla-EA, PSO) outperform simulated annealing and Bayesian optimization, especially in high-dimensional spaces. The central empirical claim is that the best configurations—notably hyperparameter-optimized runs of the analytical placer DREAMPlace—achieve better wirelength on the ISPD 2005 and ICCAD 2015 suites than representative analytical and reinforcement-learning baselines. A sympathetic reader would take away that BBO is a viable tool for macro and global placement, and that the benchmark provides a shared testbed for further algorithm development.

What carries the argument

The load-bearing machinery is a decoupled framework that splits chip placement into problem formulation (how a genotype becomes physical coordinates), optimization algorithm, and evaluation. The three formulations are the core objects: sequence pair (two permutations decoded by longest common subsequence into macro coordinates), mask-guided optimization (grid coordinates refined by a wire-mask greedy decoder that places macros on the lowest incremental-wirelength grid), and hyperparameter optimization (a solution is a full configuration of the analytical placer DREAMPlace, and running that placer is the decoding step). The framework standardizes two industrial chip suites and three metric ti

What would settle it

Run the same five algorithms under the same protocol but replace DREAMPlace with a different analytical placer as both the GP-HPWL evaluator and the HPO decoder; if HPO loses its ranking advantage over MGO and the RL/analytical baselines, the paper's central comparative result is an artifact of DREAMPlace's hyperparameter sensitivity rather than a general BBO advantage.

Watch

Extended reading notes

Core claim

The paper's central discovery is a layered comparative result. On six ISPD 2005 and eight ICCAD 2015 cases, with five seeds and fixed evaluation budgets (10,000 evaluations for macro-placement HPWL, 200 for global-placement HPWL), the sequence-pair formulation consistently ranks last, while mask-guided optimization (MGO) and hyperparameter optimization (HPO) dominate it. Across algorithms, Vanilla-EA and PSO are the strongest optimizers, particularly as the number of macros grows; Bayesian optimization struggles in high-dimensional MGO spaces but is competitive in the low-budget HPO setting. The headline numbers: HPO-Vanilla-EA and HPO-PSO reach average ranks of 2 and 2.67 on ISPD GP-HPWL, b

Load-bearing premise

The comparisons assume DREAMPlace is an impartial downstream evaluator for every formulation, even though the HPO formulation's entire search space is DREAMPlace's own configuration space; if DREAMPlace favors its own tuned configurations, the headline rankings would shift.

Editorial extensions

If this is right

  • If the results hold, BBO can field competitive solutions for both macro placement and global placement on industrial-scale chips, not just toy circuits.
  • BBOPlace-Bench gives the BBO community a real-world, high-dimensional, and expensive-evaluation testbed where new algorithms can be compared under identical budgets and metrics.
  • The HPO formulation's success indicates that tuning a strong analytical placer's hyperparameters is itself a powerful placement strategy, worth pursuing alongside direct macro-placement search.
  • The weak correlation between GP-HPWL and timing metrics (WNS) warns that wirelength gains do not automatically translate into PPA gains; multi-objective BBO is the next target.
  • At 200 evaluations, the GP-HPWL setting is an expensive-optimization testbed, and the fact that BO did not dominate there suggests a gap between BO's theoretical sample efficiency and practical performance on placement objectives.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • Because the HPO search space is exactly DREAMPlace's hyperparameter space, an independent reading is that the 'BBO beats analytical placer' result is partly 'tuned DREAMPlace beats default DREAMPlace'; a starker test would use a different analytical placer as the HPO decoder and as the GP-HPWL evaluator for all formulations.
  • The benchmark's decoupling makes it straightforward to reuse as a testbed for meta-BBO, algorithm configuration, or surrogate modeling on a hard real-world objective—none of which the paper itself explores.
  • A testable extension: freeze the hyperparameters found by HPO and run each macro placement through DREAMPlace with those settings; if the wirelength gap over MGO-EA persists, the gain is genuinely in macro placement, not just in hyperparameter tuning.
  • Another extension: vary the standard-cell placer in the GP-HPWL evaluation while keeping macro placement fixed, to measure how much of the reported advantage is downstream-engine-specific.
Share X Bluesky LinkedIn Reddit HN

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper introduces BBOPlace-Bench, proposed as the first benchmark tailored to black-box optimization (BBO) for chip placement. It integrates three problem formulations — Sequence Pair (SP), Mask-Guided Optimization (MGO), and Hyperparameter Optimization (HPO) over DREAMPlace — and five BBO algorithm families (SA, Vanilla-EA, CMA-ES, PSO, BO), with standardized preprocessing for ISPD 2005 and ICCAD 2015, and three evaluation levels: MP-HPWL, GP-HPWL, and PPA. The experiments compare formulations and algorithms under a shared protocol and also compare against analytical (DREAMPlace) and RL (AlphaChip, MaskPlace, EfficientPlace) baselines. The headline findings are that MGO and HPO dominate SP, EAs tend to outperform SA and BO, and, under GP-HPWL, HPO-based BBO methods achieve better average ranks than the analytical and RL baselines. The authors are careful to frame the experiments as illustrative case studies and to acknowledge limitations, including the reliance on commercial PPA tools.

Significance. The benchmark is potentially useful to the BBO community: it provides a modular, decoupled interface, unified preprocessing of two industrial benchmark suites, three search-space paradigms, a wide selection of out-of-the-box BBO algorithms, and both cheap (MP-HPWL) and expensive (GP-HPWL/PPA) evaluation settings. If the comparison protocol were unbiased, the result that some BBO configurations can compete with analytical and RL placers would be notable and would support the paper's central claim. The paper also contains genuinely valuable internal comparisons — e.g., the scalability failure of SP, the relative performance of BO in high dimensions, and the trade-off between MGO and HPO — that do not depend on the cross-paradigm baseline comparison. The paper ships code, reports standard deviations over five seeds, and uses Wilcoxon rank-sum tests for within-benchmark comparisons, which are good practices that strengthen the empirical claims.

major comments (3)
  1. [§III-B3, §III-D, Tables IV and VI] The central claim that BBO configurations are competitive with representative analytical and RL baselines in GP-HPWL is undermined by an asymmetric evaluation protocol. For SP and MGO, macro placement is performed by the BBO method and then DREAMPlace completes standard-cell placement with (presumably default) hyperparameters. For HPO, the search space is exactly DREAMPlace’s hyperparameter space (Algorithm 3, Table I) and each solution decoding is a full DREAMPlace run with tuned hyperparameters. The paper itself acknowledges this in §IV-B(b): the HPO advantage is ‘attributable to its capability of tuning the hyperparameters of the analytical placer DREAMPlace.’ Thus the high average ranks of HPO-Vanilla-EA (2.0) and HPO-PSO (2.67) in Table IV, and 1.88/1.38 in Table VI, may reflect hyperparameter tuning of the baseline engine rather than an independent black-box placement capability. T
  2. [§IV-C-b, Table VII] The PPA evaluation selects for each algorithm the single best placement across runs by GP-HPWL, reports no variance, and provides no external baselines. Metrics such as routed wirelength differ by well under 1% in several cases (e.g., superblue1: 75.06 vs 74.90 vs 75.23 m for SA/Vanilla-EA/PSO), yet the text states that PSO ‘performs the best in five cases’ and Vanilla-EA in three. These rankings are not accompanied by any significance test or repeatability measure, and best-of-N selection can introduce bias when runs are few. The claims in this subsection should be softened to descriptive observations or supplemented with variance/statistics over runs.
  3. [§IV-A, §IV-B, §IV-C] The comparison against external baselines is not controlled for hyperparameter tuning. The BBO algorithms are given a defined search budget and, for HPO, the ability to tune DREAMPlace, while the analytical and RL baselines (DREAMPlace, MaskPlace, EfficientPlace, AlphaChip) are taken from the literature or from default configurations. This is acknowledged only implicitly. A fairer statement would be that BBO with access to the downstream placer’s configuration space is competitive with untuned analytical baselines, or the authors should tune the baselines with a comparable budget. This does not invalidate the within-benchmark comparisons, but it is load-bearing for the abstract’s wording that ‘some BBO configurations ... are competitive with representative analytical and reinforcement learning baselines.’
minor comments (5)
  1. [§IV-A] For ICCAD 2015, macros are defined as the 512 largest modules by area. This is an important design choice, but no sensitivity analysis is given for this threshold; Table VIII varies macro count only for MGO, not for the SP and HPO formulations. The arbitrariness of this choice should be at least flagged in the main text.
  2. [§II-A] Typo: ‘cooling schedule (refereed to as temperature)’ should be ‘referred to as temperature.’
  3. [§IV-A] Footnote 4 contains a doubled URL prefix: ‘https://https://github.com/...’.
  4. [Table IX] The formatting of the SP rows in Table IX is unclear: the optimization/evaluation times for SP SA and Vanilla-EA are merged in a way that makes the per-iteration time hard to read. Please reformat the table for readability.
  5. [Abstract / §V] The abstract is appropriately hedged (‘some BBO configurations ... are competitive’), but the Conclusion states more strongly that ‘EAs demonstrate better overall performance than SA and BO ... and also achieve state-of-the-art performance compared to the mainstream chip placement methods.’ Given the asymmetric protocol, the conclusion overstates the evidence. Please align the strength of the claims with the controlled part of the experiments.

Circularity Check

0 steps flagged · score 2.0 of 10

No significant circularity; the benchmark is empirical and self-contained, with only minor non-load-bearing self-citation.

full rationale

BBOPlace-Bench is an empirical benchmark, not a derivation. Its main claims are comparisons of algorithms and formulations under a shared protocol, and these are supported by fresh experiments on ISPD 2005 and ICCAD 2015. The closest thing to a circular step is the GP-HPWL advantage of the HPO formulation, which arises because HPO optimizes DREAMPlace's own hyperparameters while SP/MGO are evaluated with a fixed DREAMPlace completion. However, the paper explicitly discloses and attributes this: 'the HPO problem formulation leads to the best performance, which is attributable to its capability of tuning the hyperparameters of the analytical placer DREAMPlace.' This is a stated property of the formulation, not a hidden prediction that reduces to a fitted input. The MGO formulation comes from the authors' prior work [68], but it is re-implemented and re-evaluated here with multiple algorithms and new benchmarks; the citation is background, not load-bearing. No uniqueness theorem or ansatz is smuggled in via self-citation, and no known result is merely renamed. The comparison against analytical and RL baselines may have an experimental-design weakness (default hyperparameters for the baseline DREAMPlace), but that is a correctness/robustness concern, not circularity by construction.

Assumptions & free parameters 5 free parameters · 5 assumptions · 0 invented entities

No new physical or mathematical entities are introduced. The ledger instead captures hand-chosen experimental settings and domain assumptions: macro count on ICCAD, evaluation budgets, algorithm hyperparameters, HPO bounds, and the dual role of DREAMPlace as both baseline and evaluation engine. These choices are not fitted to produce a derivation, but they materially shape the rankings the benchmark reports.

free parameters (5)
  • ICCAD 2015 macro count = 512 largest modules by area
    No macros are defined in ICCAD 2015; the paper defaults to the 512 largest modules, which sets the SP/MGO search-space dimension and shapes all ICCAD comparisons.
  • Evaluation budgets = 10,000 MP-HPWL; 200 GP-HPWL
    Chosen by hand; budget differences heavily affect BO vs EA comparisons (BO does better at 200 evaluations).
  • Population size and SA schedule = pop_size=50; T0=100, decay=0.99, update=100
    Common defaults chosen for comparability; not optimized per instance.
  • HPO search space ranges = Table I (15 hyperparameters, e.g., targetdensity [0.8,1.2])
    Adopted from AutoDMP/DREAMPlace practice; these bounds define the HPO formulation and partially determine results.
  • MGO grid resolution n×n = not reported in text
    The MGO decoding assumes an n×n canvas grid; n is not specified, so its effect on decode quality is uncontrolled.
assumptions (5)
  • domain assumption HPWL is a valid proxy for final chip PPA
    Section II-B/D says HPWL is widely used; the paper's own PPA table shows weak correlation between routed wirelength and WNS (-0.10), partially undermining this assumption.
  • domain assumption DREAMPlace is an appropriate universal downstream placer and analytical baseline
    Section III-D; using DREAMPlace to place standard cells after macro placement and to produce HPO decoding means evaluation and baseline share implementation.
  • ad hoc to paper The 512 largest modules represent macro sets on ICCAD 2015
    Section IV-A: 'we default to defining the 512 largest modules (by area) as macros.'
  • domain assumption Three problem formulations (SP, MGO, HPO) are representative of BBO for chip placement
    Section III-B; the benchmark excludes many possible encodings and treats these three as the design space.
  • domain assumption Wire-mask-guided decoding [68] correctly converts any solution to legal placement with low HPWL
    Algorithm 2; the benchmark relies on this external method's correctness without re-validating it.

how reviews work

0 comments
Cite this review

Pith. "Pith review of BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement." pith.science (2026). https://pith.science/paper/RATSBHTN

@misc{pith2026251023472,
  author       = {Pith},
  title        = {Pith review of: BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/RATSBHTN}},
  note         = {Machine review of arXiv:2510.23472}
}
read the original abstract

Chip placement is a vital stage in modern chip design, and black-box optimization (BBO) has been applied to it for decades. Early BBO efforts, however, were limited by immature problem formulations and inefficient algorithm designs, leading to worse efficiency, quality, and scalability than mainstream analytical methods. Recent advances in BBO have shown strong potential, but a unified, BBO-specific benchmark for thoroughly assessing various problem formulations and BBO algorithms is lacking. To fill this gap, we propose BBOPlace-Bench, the first benchmark tailored for evaluating and developing BBO algorithms for chip placement. It integrates three BBO problem formulations and offers a modular, flexible framework that enables users to seamlessly implement, test, and compare their own algorithms. It aggregates representative modern chip cases and standardizes their formats, providing uniform and comprehensive information to support BBO optimization. Moreover, it integrates representative BBO algorithm families, including simulated annealing, population-based search (including GA, CMA-ES, and PSO), and Bayesian optimization, and systematically evaluates their performance across different problem formulations using key chip-placement metrics. We position these experiments primarily as illustrative case studies under a shared evaluation protocol, including common benchmark instances, metric definitions, evaluation pipeline, and search budgets. Under this protocol, some BBO configurations (e.g., GA under the mask-guided optimization formulation) are competitive with representative analytical and reinforcement learning baselines. BBOPlace-Bench not only facilitates the development of efficient BBO-driven solutions for chip placement but also broadens the practical application scenarios urgently needed by the BBO community.

Figures

Figures reproduced from arXiv: 2510.23472 by the authors.

Figure 1
Figure 1. Illustration of BBOPlace-Bench. It decouples three core components, i.e., problem formulation, optimization algorithm, [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Example illustration of calculating HPWL. There [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. GP-HPWL vs. number of evaluations of different methods on ICCAD 2015. [PITH_FULL_IMAGE:figures/full_fig_p011_3.png] view at source ↗
Figures from the paper (1 more)
Figure 4
Figure 4. Figure 4: Placement layouts and congestions of different methods on the chip case superblue7 of ICCAD 2015. The congestion [PITH_FULL_IMAGE:figures/full_fig_p014_4.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

91 extracted references · 9 linked inside Pith

  1. [1]

    AutoDMP: Automated DREAMPlace-based macro placement,

    A. Agnesina, P. Rajvanshi, T. Yang, G. Pradipta, A. Jiao, B. Keller, B. Khailany, and H. Ren, “AutoDMP: Automated DREAMPlace-based macro placement,” inProceedings of the 27th International Symposium on Physical Design, Virtual, 2023, pp. 149–157

    2023

  2. [2]

    Toward an open-source digital flow: First learnings from the OpenROAD project,

    T. Ajayi, V . A. Chhabria, M. Fogac ¸a, S. Hashemi, A. Hosny, A. B. Kahng, M. Kim, J. Lee, U. Mallappa, M. Neseem, G. Pradipta, S. Reda, M. Saligane, S. S. Sapatnekar, C. Sechen, M. Shalan, W. Swartz, L. Wang, Z. Wang, M. Woo, and B. Xu, “Toward an open-source digital flow: First learnings from the OpenROAD project,” inProceedings of the 56th Annual Desig...

    2019

  3. [3]

    Net-based force-directed macrocell place- ment for wirelength optimization,

    S. Alupoaei and S. Katkoori, “Net-based force-directed macrocell place- ment for wirelength optimization,”IEEE Transactions on Very Large Scale Integration Systems, vol. 10, no. 6, pp. 824–835, 2002

    2002

  4. [4]

    HPO-B: A large-scale reproducible benchmark for black-box HPO based on OpenML,

    S. P. Arango, H. S. Jomaa, M. Wistuba, and J. Grabocka, “HPO-B: A large-scale reproducible benchmark for black-box HPO based on OpenML,”arXiv:2106.06257, 2021

    arXiv 2021

  5. [5]

    Audet and W

    C. Audet and W. Hare,Derivative-Free and Blackbox Optimization. Springer, 2017

    2017

  6. [6]

    B ¨ack,Evolutionary Algorithms in Theory and Practice: Evolution Strategies, Evolutionary Programming, Genetic Algorithms

    T. B ¨ack,Evolutionary Algorithms in Theory and Practice: Evolution Strategies, Evolutionary Programming, Genetic Algorithms. Oxford University Press, 1996

    1996

  7. [7]

    BoTorch: A framework for efficient Monte-Carlo Bayesian optimization,

    M. Balandat, B. Karrer, D. R. Jiang, S. Daulton, B. Letham, A. G. Wil- son, and E. Bakshy, “BoTorch: A framework for efficient Monte-Carlo Bayesian optimization,” inAdvances in Neural Information Processing Systems 33, Virtual, 2020, pp. 21 524–21 538

    2020

  8. [8]

    A survey on high-dimensional Gaussian process modeling with application to Bayesian optimization,

    M. Binois and N. Wycoff, “A survey on high-dimensional Gaussian process modeling with application to Bayesian optimization,”ACM Transactions on Evolutionary Learning and Optimization, vol. 2, no. 2, pp. 1–26, 2022

    2022

Show all 91 references
  1. [9]

    On wirelength estimations for row-based placement,

    A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov, and A. Ze- likovsky, “On wirelength estimations for row-based placement,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 9, pp. 1265–1278, 1999

    1999

  2. [10]

    CircuitNet: An open-source dataset for machine learning in VLSI CAD applica- tions with improved domain-specific evaluation metric and learning strategies,

    Z. Chai, Y . Zhao, W. Liu, Y . Lin, R. Wang, and R. Huang, “CircuitNet: An open-source dataset for machine learning in VLSI CAD applica- tions with improved domain-specific evaluation metric and learning strategies,”IEEE Transactions on Computer-Aided Design of Integrated Circ...

    2023

  3. [11]

    Flexible multiple- objective reinforcement learning for chip placement,

    F.-C. Chang, Y .-W. Tseng, Y .-W. Yu, S.-R. Lee, A. Cioba, I.-L. Tseng, D.-s. Shiu, J.-W. Hsu, C.-Y . Wang, C.-Y . Yanget al., “Flexible multiple- objective reinforcement learning for chip placement,”arXiv:2204.06407, 2022

    2022 arXiv

  4. [12]

    Essential issues in analytical place- ment algorithms,

    Y . Chang, Z. Jiang, and T. Chen, “Essential issues in analytical place- ment algorithms,”IPSJ Transactions on System LSI Design Methodol- ogy, vol. 2, pp. 145–166, 2009

    2009

  5. [13]

    B*-trees: A new representation for non-slicing floorplans,

    Y .-C. Chang, Y .-W. Chang, G.-M. Wu, and S.-W. Wu, “B*-trees: A new representation for non-slicing floorplans,” inProceedings of the 37th Annual Design Automation Conference, Los Angeles, CA, 2000, pp. 458–463

    2000

  6. [14]

    NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints,

    T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y .-W. Chang, “NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 7, p...

    2008

  7. [15]

    RePlAce: Advancing solution quality and routability validation in global placement,

    C.-K. Cheng, A. B. Kahng, I. Kang, and L. Wang, “RePlAce: Advancing solution quality and routability validation in global placement,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 9, pp. 1717–1730, 2018

    2018

  8. [16]

    The policy-gradient placement and generative routing neural networks for chip design,

    R. Cheng, X. Lyu, Y . Li, J. Ye, J. Hao, and J. Yan, “The policy-gradient placement and generative routing neural networks for chip design,” in Advances in Neural Information Processing Systems 35, New Orleans, LA, 2022, pp. 26 350–26 362

    2022

  9. [17]

    On joint learning for solving placement and routing in chip design,

    R. Cheng and J. Yan, “On joint learning for solving placement and routing in chip design,” inAdvances in Neural Information Processing Systems 34, Virtual, 2021, pp. 16 508–16 519

    2021

  10. [18]

    Deb,Multi-Objective Optimization Using Evolutionary Algorithms

    K. Deb,Multi-Objective Optimization Using Evolutionary Algorithms. Wiley, 2001

    2001

  11. [19]

    PyPop7: A pure-Python li- brary for population-based black-box optimization,

    Q. Duan, G. Zhou, C. Shao, and Others, “PyPop7: A pure-Python li- brary for population-based black-box optimization,”Journal of Machine Learning Research, vol. 25, no. 296, pp. 1–28, 2024

    2024

  12. [20]

    High-dimensional bayesian optimiza- tion with sparse axis-aligned subspaces,

    D. Eriksson and M. Jankowiak, “High-dimensional bayesian optimiza- tion with sparse axis-aligned subspaces,” inProceedings of the 37th Conference on Uncertainty in Artificial Intelligence, Virtual Event, 2021, pp. 493–503

    2021

  13. [21]

    Scalable global optimization via local Bayesian optimization,

    D. Eriksson, M. Pearce, J. R. Gardner, R. Turner, and M. Poloczek, “Scalable global optimization via local Bayesian optimization,” in Advances in Neural Information Processing Systems 32, Vancouver, Canada, 2019, pp. 5497–5508

    2019

  14. [22]

    A tutorial on Bayesian optimization,

    P. I. Frazier, “A tutorial on Bayesian optimization,”arXiv:1807.02811, 2018

    2018 arXiv

  15. [23]

    Garnett,Bayesian Optimization

    R. Garnett,Bayesian Optimization. Cambridge University Press, 2023

    2023

  16. [24]

    LaMPlace: Learning to optimize cross-stage metrics in macro placement,

    Z. Geng, J. Wang, Z. Liu, S. Xu, Z. Tang, S. Kai, M. Yuan, J. Hao, and F. Wu, “LaMPlace: Learning to optimize cross-stage metrics in macro placement,” inProceedings of the 13th International Conference on Learning Representations, Singapore, 2025

    2025

  17. [25]

    Reinforcement learning within tree search for fast macro placement,

    Z. Geng, J. Wang, Z. Liu, S. Xu, Z. Tang, M. Yuan, J. Hao, Y . Zhang, and F. Wu, “Reinforcement learning within tree search for fast macro placement,” inProceedings of the 41st International Conference on Machine Learning, Vienna, Austria, 2024, pp. 15 402–15 417

    2024

  18. [26]

    That chip has sailed: A critique of unfounded skepticism around AI for chip design,

    A. Goldie, A. Mirhoseini, and J. Dean, “That chip has sailed: A critique of unfounded skepticism around AI for chip design,”arxiv:2411.10053, 2024

    2024 arXiv

  19. [27]

    Addendum: A graph placement methodology for fast chip design,

    A. Goldie, A. Mirhoseini, M. Yazgan, J. W. Jiang, E. Songhori, S. Wang, Y .-J. Lee, E. Johnson, O. Pathak, A. Novaet al., “Addendum: A graph placement methodology for fast chip design,”Nature, vol. 634, no. 8034, pp. E10–E11, 2024

    2024

  20. [28]

    Genetic learning particle swarm optimization,

    Y .-J. Gong, J.-J. Li, Y . Zhou, Y . Li, H. S.-H. Chung, Y .-H. Shi, and J. Zhang, “Genetic learning particle swarm optimization,”IEEE Transactions on Cybernetics, vol. 46, no. 10, pp. 2277–2290, 2015

    2015

  21. [29]

    DREAMPlace 3.0: Multi- electrostatics based robust VLSI placement with region constraints,

    J. Gu, Z. Jiang, Y . Lin, and D. Z. Pan, “DREAMPlace 3.0: Multi- electrostatics based robust VLSI placement with region constraints,” inProceedings of the 33rd IEEE/ACM International Conference on Computer-Aided Design, San Diego, CA, 2020, pp. 1–9

    2020

  22. [30]

    Con- figX: Modular configuration for evolutionary algorithms via multitask IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, VOL. XX, NO. X, 2025 16 reinforcement learning,

    H. Guo, Z. Ma, J. Chen, Y . Ma, Z. Cao, X. Zhang, and Y .-J. Gong, “Con- figX: Modular configuration for evolutionary algorithms via multitask IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, VOL. XX, NO. X, 2025 16 reinforcement learning,” inProceedings of the 39th AAAI Confere...

    2025

  23. [31]

    The CMA evolution strategy: A tutorial,

    N. Hansen, “The CMA evolution strategy: A tutorial,” arXiv:1604.00772, 2016

    2016 arXiv

  24. [32]

    Evolution strategies,

    N. Hansen, D. V . Arnold, and A. Auger, “Evolution strategies,” in Springer Handbook of Computational Intelligence. Springer, 2015, pp. 871–898

    2015

  25. [33]

    Ripple: A robust and effective routability-driven placer,

    X. He, T. Huang, L. Xiao, H. Tian, and E. F. Y . Young, “Ripple: A robust and effective routability-driven placer,”IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol. 32, no. 10, pp. 1546–1556, 2013

    2013

  26. [34]

    Corner block list: An effective and efficient topological representation of non-slicing floorplan,

    X. Hong, G. Huang, Y . Cai, J. Gu, S. Dong, C.-K. Cheng, and J. Gu, “Corner block list: An effective and efficient topological representation of non-slicing floorplan,” inProceedings of the 13th IEEE/ACM Inter- national Conference on Computer Aided Design, San Jose, CA, 2000, pp. 8–12

    2000

  27. [35]

    Data-driven evolutionary optimization: An overview and case studies,

    Y . Jin, H. Wang, T. Chugh, D. Guo, and K. Miettinen, “Data-driven evolutionary optimization: An overview and case studies,”IEEE Trans- actions on Evolutionary Computation, vol. 23, no. 3, pp. 442–458, 2019

    2019

  28. [36]

    Efficient global optimiza- tion of expensive black-box functions,

    D. R. Jones, M. Schonlau, and W. J. Welch, “Efficient global optimiza- tion of expensive black-box functions,”Journal of Global Optimization, vol. 13, no. 4, pp. 455–492, 1998

    1998

  29. [37]

    A tale of two nets: Studies of wirelength progression in physical design,

    A. B. Kahng and S. Reda, “A tale of two nets: Studies of wirelength progression in physical design,” inProceedings of the 7th International Workshop on System-level Interconnect Prediction, Munich, Germany, 2006, pp. 17–24

    2006

  30. [38]

    Particle swarm optimization,

    J. Kennedy and R. Eberhart, “Particle swarm optimization,” inPro- ceedings of 3rd International Conference on Neural Networks, Perth, Australia, 1995, pp. 1942–1948

    1995

  31. [39]

    ICCAD-2015 CAD contest in incremental timing-driven placement and benchmark suite,

    M. Kim, J. Hu, J. Li, and N. Viswanathan, “ICCAD-2015 CAD contest in incremental timing-driven placement and benchmark suite,” inProceedings of the 28th IEEE/ACM International Conference on Computer-Aided Design, Austin, TX, 2015, pp. 921–926

    2015

  32. [40]

    A new method of locating the maximum point of an arbitrary multipeak curve in the presence of noise,

    H. J. Kushner, “A new method of locating the maximum point of an arbitrary multipeak curve in the presence of noise,”Journal of Basic Engineering, vol. 86, no. 1, pp. 97–106, 1964

    1964

  33. [41]

    ChiPFormer: Transferable chip placement via offline decision transformer,

    Y . Lai, J. Liu, Z. Tang, B. Wang, J. Hao, and P. Luo, “ChiPFormer: Transferable chip placement via offline decision transformer,” inPro- ceedings of the 40th International Conference on Machine Learning, Honolulu, HI, 2023, pp. 18 346–18 364

    2023

  34. [42]

    MaskPlace: Fast chip placement via reinforced visual representation learning,

    Y . Lai, Y . Mu, and P. Luo, “MaskPlace: Fast chip placement via reinforced visual representation learning,” inAdvances in Neural In- formation Processing Systems 35, New Orleans, LA, 2022, pp. 24 019– 24 030

    2022

  35. [43]

    iEDA: An open-source infrastructure of EDA,

    X. Li, Z. Huang, S. Tao, Z. Huang, C. Zhuang, H. Wang, Y . Li, Y . Qiu, G. Luo, H. Li, H. Shen, M. Chen, D. Bu, W. Zhu, Y . Cai, X. Xiong, Y . Jiang, Y . Heng, P. Zhang, B. Yu, B. Xie, and Y . Bao, “iEDA: An open-source infrastructure of EDA,” inProceedings of the 29th Asia an...

    2024

  36. [44]

    DREAMPlace 4.0: Timing-driven placement with momentum-based net weighting and Lagrangian-based refinement,

    P. Liao, D. Guo, Z. Guo, S. Liu, Y . Lin, and B. Yu, “DREAMPlace 4.0: Timing-driven placement with momentum-based net weighting and Lagrangian-based refinement,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 10, pp. 3374– 3387, 2023

    2023

  37. [45]

    POLAR 3.0: An ultrafast global placement engine,

    T. Lin, C. C. N. Chu, and G. Wu, “POLAR 3.0: An ultrafast global placement engine,” inProceedings of the 28th IEEE/ACM International Conference on Computer-Aided Design, Austin, TX, 2015, pp. 520–527

    2015

  38. [46]

    DREAMPlace: Deep learning toolkit-enabled GPU acceleration for modern VLSI placement,

    Y . Lin, Z. Jiang, J. Gu, W. Li, S. Dhar, H. Ren, B. Khailany, and D. Z. Pan, “DREAMPlace: Deep learning toolkit-enabled GPU acceleration for modern VLSI placement,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 4, pp. 748–761, 2020

    2020

  39. [47]

    Evolution of heuristics: Towards efficient automatic algorithm design using large language model,

    F. Liu, T. Xialiang, M. Yuan, X. Lin, F. Luo, Z. Wang, Z. Lu, and Q. Zhang, “Evolution of heuristics: Towards efficient automatic algorithm design using large language model,” inProceedings of the 41st International Conference on Machine Learning, Vienna, Austria, 2024, pp. 32...

    2024

  40. [48]

    A systematic survey on large language models for algorithm design,

    F. Liu, Y . Yao, P. Guo, Z. Yang, Z. Zhao, X. Lin, X. Tong, M. Yuan, Z. Lu, Z. Wanget al., “A systematic survey on large language models for algorithm design,”arXiv:2410.14716, 2024

    2024

  41. [49]

    Xplace: An extremely fast and extensible placement framework,

    L. Liu, B. Fu, S. Lin, J. Liu, E. F. Y . Young, and M. D. F. Wong, “Xplace: An extremely fast and extensible placement framework,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, no. 6, pp. 1872–1885, 2024

    2024

  42. [50]

    ePlace: Electrostatics-based placement using fast Fourier transform and Nesterov’s method,

    J. Lu, P. Chen, C.-C. Chang, L. Sha, D. J.-H. Huang, C.-C. Teng, and C.-K. Cheng, “ePlace: Electrostatics-based placement using fast Fourier transform and Nesterov’s method,”ACM Transactions on Design Automation of Electronic Systems, vol. 20, no. 2, pp. 1–34, 2015

    2015

  43. [51]

    Neural exploratory landscape analysis for meta-black-box-optimization,

    Z. Ma, J. Chen, H. Guo, and Y .-J. Gong, “Neural exploratory landscape analysis for meta-black-box-optimization,” inProceedings of the 13th International Conference on Learning Representations, Singapore, 2025

    2025

  44. [52]

    MetaBox: A benchmark platform for meta-black-box optimization with reinforcement learning,

    Z. Ma, H. Guo, J. Chen, Z. Li, G. Peng, Y .-J. Gong, Y . Ma, and Z. Cao, “MetaBox: A benchmark platform for meta-black-box optimization with reinforcement learning,” inAdvances in Neural Information Processing Systems 36, New Orleans, LA, 2023, pp. 10 775–10 795

    2023

  45. [53]

    Toward automated algorithm design: A survey and practical guide to meta-black-box- optimization,

    Z. Ma, H. Guo, Y .-J. Gong, J. Zhang, and K. C. Tan, “Toward automated algorithm design: A survey and practical guide to meta-black-box- optimization,”IEEE Transactions on Evolutionary Computation, 2025

    2025

  46. [54]

    An industrial view of electronic design automation,

    D. MacMillen, R. Camposano, D. Hill, and T. W. Williams, “An industrial view of electronic design automation,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 12, pp. 1428–1448, 2000

    2000

  47. [55]

    Progress and challenges in VLSI placement research,

    I. L. Markov, J. Hu, and M.-C. Kim, “Progress and challenges in VLSI placement research,” inProceedings of the 25th IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2012, pp. 275–282

    2012

  48. [56]

    Exploratory landscape analysis,

    O. Mersmann, B. Bischl, H. Trautmann, M. Preuss, C. Weihs, and G. Rudolph, “Exploratory landscape analysis,” inProceedings of the 13th Genetic and Evolutionary Computation Conference, Dublin, Ire- land, 2011, pp. 829–836

    2011

  49. [57]

    A graph placement methodology for fast chip design,

    A. Mirhoseini, A. Goldie, M. Yazgan, J. W. Jiang, E. Songhori, S. Wang, Y .-J. Lee, E. Johnson, O. Pathak, A. Naziet al., “A graph placement methodology for fast chip design,”Nature, vol. 594, no. 7862, pp. 207– 212, 2021

    2021

  50. [58]

    VLSI module placement based on rectangle-packing by the sequence-pair,

    H. Murata, K. Fujiyoshi, S. Nakatake, and Y . Kajitani, “VLSI module placement based on rectangle-packing by the sequence-pair,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 12, pp. 1518–1524, 1996

    1996

  51. [59]

    The ISPD 2005 placement contest and benchmark suite,

    G.-J. Nam, C. J. Alpert, P. Villarrubia, B. Winter, and M. Yildiz, “The ISPD 2005 placement contest and benchmark suite,” inProceedings of the 9th International Symposium on Physical Design, San Francisco, CA, 2005, pp. 216–220

    2005

  52. [60]

    Bayesian optimization for macro placement,

    C. Oh, R. Bondesan, D. Kianfar, R. Ahmed, R. Khurana, P. Agarwal, R. Lepert, M. Sriram, and M. Welling, “Bayesian optimization for macro placement,”arXiv:2207.08398, 2022

    2022 arXiv

  53. [61]

    A review of population-based metaheuristics for large-scale black-box global optimization—Part I,

    M. N. Omidvar, X. Li, and X. Yao, “A review of population-based metaheuristics for large-scale black-box global optimization—Part I,” IEEE Transactions on Evolutionary Computation, vol. 26, no. 5, pp. 802–822, 2022

    2022

  54. [62]

    IncreMacro: Incremental macro placement refinement,

    Y . Pu, T. Chen, Z. He, J. Qin, C. Bai, H. Zheng, Y . Lin, and B. Yu, “IncreMacro: Incremental macro placement refinement,”IEEE Trans- actions on Computer-Aided Design of Integrated Circuits and Systems, vol. 44, no. 8, pp. 3222–3235, 2025

    2025

  55. [63]

    SOO-Bench: Benchmarks for evaluating the stability of offline black-box optimization,

    H. Qian, Y . Zhu, X. Shu, X. An, Y . Wen, S. Liu, H. Lu, A. Zhou, K. Tang, and Y . Yu, “SOO-Bench: Benchmarks for evaluating the stability of offline black-box optimization,” inProceedings of the 13th International Conference on Learning Representations, Singapore, 2025

    2025

  56. [64]

    C. E. Rasmussen and C. K. I. Williams,Gaussian Processes for Machine Learning. The MIT Press, 2006

    2006

  57. [65]

    Finite Markov chain results in evolutionary computation: A tour d’horizon,

    G. Rudolph, “Finite Markov chain results in evolutionary computation: A tour d’horizon,”Fundamenta Informaticae, vol. 35, no. 1-4, pp. 67– 89, 1998

    1998

  58. [66]

    VLSI cell placement techniques,

    K. Shahookar and P. Mazumder, “VLSI cell placement techniques,”ACM Computing Surveys, vol. 23, no. 2, pp. 143–220, 1991

    1991

  59. [67]

    Taking the human out of the loop: A review of Bayesian optimization,

    B. Shahriari, K. Swersky, Z. Wang, R. P. Adams, and N. de Freitas, “Taking the human out of the loop: A review of Bayesian optimization,” Proceedings of the IEEE, vol. 104, no. 1, pp. 148–175, 2016

    2016

  60. [68]

    Macro placement by wire-mask- guided black-box optimization,

    Y . Shi, K. Xue, L. Song, and C. Qian, “Macro placement by wire-mask- guided black-box optimization,” inAdvances in Neural Information Processing Systems 36, New Orleans, LA, 2023, pp. 6825–6843

    2023

  61. [69]

    Monte Carlo tree search based variable selection for high dimensional Bayesian optimization,

    L. Song, K. Xue, X. Huang, and C. Qian, “Monte Carlo tree search based variable selection for high dimensional Bayesian optimization,” in Advances in Neural Information Processing Systems 35, New Orleans, LA, 2022

    2022

  62. [70]

    Fast and accurate routing demand estimation for efficient routability-driven placement,

    P. Spindler and F. M. Johannes, “Fast and accurate routing demand estimation for efficient routability-driven placement,” inProceedings of the 14th Conference on Design, Automation & Test in Europe, Nice, France, 2007, pp. 1–6

    2007

  63. [71]

    Information- theoretic regret bounds for Gaussian process optimization in the bandit setting,

    N. Srinivas, A. Krause, S. M. Kakade, and M. W. Seeger, “Information- theoretic regret bounds for Gaussian process optimization in the bandit setting,”IEEE Transactions on Information Theory, vol. 58, no. 5, pp. 3250–3265, 2012. IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, V...

    2012

  64. [72]

    LLaMEA: A large language model evolu- tionary algorithm for automatically generating metaheuristics,

    N. v. Stein and T. B ¨ack, “LLaMEA: A large language model evolu- tionary algorithm for automatically generating metaheuristics,”IEEE Transactions on Evolutionary Computation, vol. 29, no. 2, pp. 331–345, 2025

    2025

  65. [73]

    Nonconvex optimization by fast simulated annealing,

    H. H. Szu and R. L. Hartley, “Nonconvex optimization by fast simulated annealing,”Proceedings of IEEE, vol. 75, no. 11, pp. 1538–1540, 1987

    1987

  66. [74]

    A memetic algorithm for VLSI floorplanning,

    M. Tang and X. Yao, “A memetic algorithm for VLSI floorplanning,” IEEE Transactions on Systems, Man, and Cybernetics, vol. 37, no. 1, pp. 62–69, 2007

    2007

  67. [75]

    MuJoCo: A physics engine for model-based control,

    E. Todorov, T. Erez, and Y . Tassa, “MuJoCo: A physics engine for model-based control,” inProceedings of the 35th IEEE/RSJ International Conference on Intelligent Robots and Systems, Vilamoura, Portugal, 2012, pp. 5026–5033

    2012

  68. [76]

    How do dynamic events change the fitness landscape of traveling salesman problems?

    H. Tong, M. Li, J. Liu, and X. Yao, “How do dynamic events change the fitness landscape of traveling salesman problems?”IEEE Transactions on Evolutionary Computation, vol. 29, no. 5, pp. 1463–1474, 2025

    2025

  69. [77]

    Design-Bench: Bench- marks for data-driven offline model-based optimization,

    B. Trabucco, X. Geng, A. Kumar, and S. Levine, “Design-Bench: Bench- marks for data-driven offline model-based optimization,” inProceedings of the 39th International Conference on Machine Learning, Baltimore, MD, 2022, pp. 21 658–21 676

    2022

  70. [78]

    Placement in integrated circuits using cyclic reinforcement learning and simulated annealing,

    D. Vashisht, H. Rampal, H. Liao, Y . Lu, D. Shanbhag, E. Fallon, and L. B. Kara, “Placement in integrated circuits using cyclic reinforcement learning and simulated annealing,”arXiv:2011.07577, 2020

    2011 arXiv

  71. [79]

    Two Arch2: An improved two-archive algorithm for many-objective optimization,

    H. Wang, L. Jiao, and X. Yao, “Two Arch2: An improved two-archive algorithm for many-objective optimization,”IEEE Transactions on Evo- lutionary Computation, vol. 19, no. 4, pp. 524–541, 2015

    2015

  72. [80]

    Learning search space partition for black-box optimization using Monte Carlo tree search,

    L. Wang, R. Fonseca, and Y . Tian, “Learning search space partition for black-box optimization using Monte Carlo tree search,” inAdvances in Neural Information Processing Systems 33, Virtual, 2020, pp. 19 511– 19 522

    2020

  73. [81]

    Benchmarking end-to-end performance of AI- based chip placement algorithms,

    Z. Wang, Z. Geng, Z. Tu, J. Wang, Y . Qian, Z. Xu, Z. Liu, S. Xu, Z. Tang, S. Kaiet al., “Benchmarking end-to-end performance of AI- based chip placement algorithms,” inAdvances in Neural Information Processing Systems 38, San Diego, CA, 2025

    2025

  74. [82]

    Reinforcement learning policy as macro regulator rather than macro placer,

    K. Xue, R.-T. Chen, X. Lin, Y . Shi, S. Kai, S. Xu, and C. Qian, “Reinforcement learning policy as macro regulator rather than macro placer,” inAdvances in Neural Information Processing Systems 38, Vancouver, Canada, 2024, pp. 140 565–140 588

    2024

  75. [83]

    Escaping local optima in global placement,

    K. Xue, X. Lin, Y . Shi, S. Kai, S. Xu, and C. Qian, “Escaping local optima in global placement,”arXiv:2402.18311, 2024

    2024 arXiv

  76. [84]

    Offline multi-objective optimization,

    K. Xue, R.-X. Tan, X. Huang, and C. Qian, “Offline multi-objective optimization,” inProceedings of the 41st International Conference on Machine Learning, Vienna, Austria, 2024, pp. 55 595–55 624

    2024

  77. [85]

    Multi-agent dynamic algorithm configuration,

    K. Xue, J. Xu, L. Yuan, M. Li, C. Qian, Z. Zhang, and Y . Yu, “Multi-agent dynamic algorithm configuration,” inAdvances in Neural Information Processing Systems 35, New Orleans, LA, 2022, pp. 20 147– 20 161

    2022

  78. [86]

    CircuitNet 2.0: An advanced dataset for promoting machine learning innovations in realistic chip design environment,

    J. Xun, Z. Chai, Y . Zhao, Y . Lin, R. Wang, and R. Huang, “CircuitNet 2.0: An advanced dataset for promoting machine learning innovations in realistic chip design environment,” inProceedings of the 12th In- ternational Conference on Learning Representations, Vienna, Austria, 2024

    2024

  79. [87]

    NAS-Bench-101: Towards reproducible neural architecture search,

    C. Ying, A. Klein, E. Christiansen, E. Real, K. Murphy, and F. Hutter, “NAS-Bench-101: Towards reproducible neural architecture search,” in Proceedings of the 36th International Conference on Machine Learning, Long Beach, CA, 2019, pp. 7105–7114

    2019

  80. [88]

    Y . Yu, H. Qian, and Y .-Q. Hu,Derivative-Free Optimization: Theoretical Foundations, Algorithms, and Applications. Springer, 2025

    2025

  81. [89]

    Zhang, R

    X. Zhang, R. Cheng, Y . Tian, and Y . Jin,Evolutionary Large-Scale Multi-Objective Optimization and Applications. John Wiley & Sons, 2024

    2024

  82. [90]

    DeepGate4: Efficient and effective representation learning for circuit design at scale,

    Z. Zheng, S. Huang, J. Zhong, Z. Shi, G. Dai, N. Xu, and Q. Xu, “DeepGate4: Efficient and effective representation learning for circuit design at scale,”arxiv:2502.01681, 2025

    2025 arXiv

  83. [91]

    Z.-H. Zhou, Y . Yu, and C. Qian,Evolutionary Learning: Advances in Theories and Algorithms. Springer, 2019

    2019

Pith tools

Reviewed August 4, 2026 · model on record in the stance chip above.