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REVIEW 4 major objections 6 minor 31 references

Medusa claims that a small number of tuned flag qubits can make an N-qubit adder-like circuit fail as rarely as an N-1-qubit circuit.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

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2026-08-03 21:09 UTC pith:NZTM523B

load-bearing objection The heuristic and simulations are plausible, but Algorithm 1's binary search is described upside down and the reported m values are not reproducible from the paper as written. the 4 major comments →

arxiv 2511.16289 v2 pith:NZTM523B submitted 2025-11-20 quant-ph

Medusa: Detecting and Removing Failures for Scalable Quantum Computing

Karoliina Oksanen , Quan Hoang , Alexandru Paler This is my paper
classification quant-ph
keywords flag qubitsfailure ratepost-selectionfault tolerancesurface codesICM circuitsadder circuitsquantum error correction
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Medusa is an automated compilation method that lowers a quantum circuit's failure rate by inserting flag qubits and then tuning how fault-tolerant those flags are. The paper's central claim is that for adder-like circuits, a few well-placed flags can make a large N-qubit circuit's post-selected failure rate match that of a smaller (N-1)-qubit circuit. The authors formalize failure and post-selected failure rate through stabilizer comparisons, rank candidate flags by the weight of the errors they catch, and use binary search over an error multiplier m to set the flag error rate needed to hit a target. They then convert m into surface-code distances and physical qubit counts. If the claim holds, structured computations could run on early fault-tolerant machines with less error-correction overhead than full quantum error correction would demand.

Core claim

Starting from CNOT-only circuits in ICM form, Medusa attaches unique X- and Z-flags so that errors are caught before they spread, post-selects runs where no flag fired, and defines the post-selected failure rate as missed failures divided by accepted runs. The key numerical discovery is that even a modest improvement in flag reliability---captured by an error multiplier m below 1---lowers the whole circuit's failure rate, and for adder-like topologies the required m is reachable with moderate-distance surface codes. Concretely, the paper demonstrates that an N-qubit adder-like circuit can be tuned, using about 5 log2 N flags, to reach the failure rate of an N-1-qubit circuit. This means the

What carries the argument

The central mechanism is the flag qubit combined with an error multiplier m. A flag is a qubit connected by two CNOTs around a stretch of circuit; its final measurement reveals whether an error occurred in that stretch. The error multiplier m scales the base depolarizing noise p_ncs down to p_f = m * p_ncs for the gates touching the flags. Medusa ranks unique flags by weight (the number of CNOTs they surround), simulates noisy flagged circuits against stabilizer truth tables to compute the post-selected failure rate, and binary-searches m so the circuit reaches a target failure rate such as the flagless failure rate of an (N-1)-qubit circuit. The m=0 perfect-flag simulation gives an upper bo

Load-bearing premise

The central premise is that only the gates touching the flags need protection--flag error rates can be set to m times the data error rate while the CNOTs linking flags to data are left out of the resource count; if those links must be error-corrected, the reported costs are too low.

What would settle it

Rerun the paper's simulations with noisy initialization and measurement, or include the flag-to-data CNOTs in the resource estimate, and check whether an N-qubit circuit with the predicted m still reaches the failure rate of the N-1 circuit.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

If this is right

  • For adder-like circuits, an N-qubit implementation can be tuned to the failure rate of an N-1-qubit implementation using a logarithmic number of flags, so error-correction cost need not track circuit size as steeply.
  • Smaller circuits require relatively more flag error correction than larger circuits to gain one qubit's worth of failure-rate improvement, since the required m is smaller for small N.
  • The perfect-flag simulation gives a numerical upper bound: for a chosen flag set, no amount of flag error correction can beat that failure rate.
  • A slight improvement in local flag fault-tolerance reduces the entire circuit's failure rate, supporting partial error correction instead of fully protected syndrome extraction.
  • The reported physical-qubit counts are lower bounds, because they exclude error correction of the CNOTs connecting flags to data qubits.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the connecting CNOTs between flags and data qubits must themselves be error corrected, the reported surface-code footprints would likely rise; the qualitative benefit may survive, but the cost break-even point would shift.
  • The same stabilizer-truth-table and binary-search recipe could transfer to other structured circuit families whose gate count scales with qubit number, such as QFT-like or QRAM-like circuits, though the required m values would need fresh simulation.
  • The one-step 'N behaves like N-1' result suggests a recursive strategy: repeated Medusa-style flagging could climb down several circuit sizes, trading full QEC for layers of protected flags, provided error accumulation across nested flags is checked.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

4 major / 6 minor

Summary. The paper introduces Medusa, an automated compilation method that inserts flag qubits into ICM-form quantum circuits to lower their post-selected failure rate (FR). The method uses a weight-based heuristic for placing unique flags, Stim-based noisy simulation to estimate FR, and a binary-search procedure over an 'error multiplier' m that scales the noise on gates touching the flags. The central benchmark shows that for adder-like circuits, an N-qubit circuit can be tuned to match the FR of an (N−1)-qubit circuit; the required m is then mapped to surface-code distances and physical qubit counts. The authors conclude that partially error-corrected flags offer a cost-effective way to reduce logical failure rates in structured circuits.

Significance. The idea of exploiting circuit structure to reduce QEC overhead is timely and potentially valuable for early fault-tolerant computation. The paper contributes a concrete flag-insertion heuristic, uses a reproducible simulator (Stim), and provides explicit resource estimates. If the results hold, the approach could inform practical compilation choices. However, the central numerical result—the m values in Fig. 4d—is not reproducible from the described Algorithm 1, and the resource estimates are explicitly incomplete because they omit the cost of protecting the flag–data CNOTs. These issues must be resolved before the quantitative claims can be accepted. The qualitative conclusion that better-protected flags lower FR is plausible and supported by Fig. 5, but the paper's current form overstates the reliability of its headline numbers.

major comments (4)
  1. [Sec. 2.4 / Algorithm 1] The binary-search update is inverted relative to the monotonicity of FR(m). Since p_f = m·p_ncs and Fig. 5 shows FR decreases as m decreases, FR is increasing in m. Therefore, when FR > FR_target the algorithm should decrease m by setting b←m. The pseudocode instead sets a←m, driving m upward; this cannot produce the interior m values reported in Fig. 4d. The accompanying text also reverses the terminology: m=0 (perfect flags) gives the lowest FR, hence is a lower bound on FR, not the 'upper bound' as stated. As written, the paper does not specify a procedure that yields the published m values.
  2. [Sec. 3.1 / Algorithm 1] The stopping tolerance ε=0.0005 is comparable to the binomial standard error of the FR estimate from 10^6 simulation runs (max sqrt(0.25/1e6)=0.0005). No error bars or confidence intervals are provided in Fig. 4d. The binary search may therefore be chasing sampling noise rather than a genuine threshold, and the reported m–N curves may not be reproducible. Please report repeated trials, confidence intervals, or increase the sample size / relax ε so that the tuning is statistically meaningful.
  3. [Sec. 3.4] The resource estimates in Fig. 4f explicitly exclude the qubits needed to error-correct the two-qubit gates between the flags and the data qubits, and the authors label the estimate a 'lower bound.' This omission is load-bearing for the cost-benefit conclusion, because the entire tuning mechanism relies on those connecting CNOTs having error rate p_f. If protecting these CNOTs is necessary or expensive, the reported qubit counts could be substantially too low. The paper should either quantify this overhead or substantially soften the claim that partially protected flags are 'cost-effective.'
  4. [Algorithm 1] The inner while-loop does not reset the binary-search bounds a and b when the number of flags f is incremented. Since adding a flag changes FR, a previously converged m is no longer valid for the new circuit, and carrying over the interval may cause the search to exit prematurely or oscillate. The exact search procedure over f needs to be specified precisely for the reported results to be reproducible.
minor comments (6)
  1. [Abstract / Sec. 1.3] The phrase 'numerically upper bound the failure rate' is misleading: perfect flags give the lowest possible FR for a given heuristic, i.e., a lower bound on the achievable failure rate, not an upper bound. Please correct the terminology.
  2. [Fig. 1 caption] Typo: 'wether' should be 'whether'.
  3. [Sec. 3.1] The paper uses at most 100 random input strings per circuit. For circuits with more than 100 qubits, this is a small sample of the input space; please discuss how representative this is for the stabilizer-based FR estimate.
  4. [Sec. 2.4] The statement that 'a and b are lower bounded by a threshold value that limits the depth of binary search' is vague, and the pseudocode contains no such threshold. Please clarify the termination criterion.
  5. [Sec. 3.3] The benchmark circuits are 'adder-like' after removing T and H gates from real adders. The paper is transparent about this, but the abstract's phrasing 'large-scale implementations' may overstate relevance to quantum algorithms that require T gates. Consider clarifying this limitation in the conclusion as well.
  6. [Sec. 2.2] There is no comparison of the weight-based flag selection to random placement or to a fixed number of flags. A baseline would strengthen the claim that the heuristic's ranking is effective.

Circularity Check

0 steps flagged

No significant circularity: Medusa's m-tuning result is an explicit inversion to an externally defined target, not a prediction reduced from its inputs.

full rationale

Medusa's central numerical claim is that an error multiplier m can be found so that FR_m(N) matches FR(N-1); this is an explicit target-inversion procedure, stated in Sec. 3.3 as "we wish to tune the value of m such that an N-circuit reaches a target FR_tar equivalent to the failure rate of a N-1 circuit" and implemented by the binary search in Alg. 1. Showing that such an m exists is a construction/feasibility statement, not a prediction extracted from the fitted value, so the fitted-input-called-prediction pattern does not apply. The perfect-flag m=0 simulation is a benchmark, and the target is defined by the flagless N-1 circuit rather than by the perfect-flag bound, so there is no definitional collapse. Self-citations [25,31] supply the ICM compilation formalism, but they are background and do not carry the failure-rate result; the numerical FR values come from independent Stim simulations, and the surface-code resource mapping uses an external formula from [24]. The paper explicitly labels the resource estimates as a lower bound because connecting-CNOT error correction is excluded (Sec. 3.4), which is a stated limitation rather than a hidden circular step. The Sec. 2.4 labels calling m=0 the 'upper bound' and m=1 the 'lower bound' appear reversed relative to Fig. 5, and the branch logic in Alg. 1 looks inverted relative to FR(m) monotonicity; these are reproducibility/correctness concerns, not circularity. No load-bearing step reduces to its own inputs.

Axiom & Free-Parameter Ledger

3 free parameters · 5 axioms · 0 invented entities

The central claims rest on a simplified depolarizing-noise model, the ability to error-protect flags independently of data, and a structural extrapolation from adder-like to adder circuits. No new physical entities are introduced.

free parameters (3)
  • error multiplier m = varies with N and p_ncs; see Fig. 4d
    Binary-searched to make FR reach FR(N-1); sets flag noise p_f = m*p_ncs via Alg. 1.
  • number of flags = 5 log2(N) = coefficient 5
    Ad hoc choice for benchmarks; the paper does not derive the optimal flag count or coefficient.
  • epsilon (binary search tolerance) = 0.0005
    Convergence threshold for Alg. 1; chosen by hand and not justified against simulation noise.
axioms (5)
  • domain assumption Arbitrary computations can be pre-compiled to ICM circuits (CNOT-only) without loss of generality.
    Invoked in Sec. 2 based on [25,31]; however, the paper then removes T and H gates, so the actual benchmark circuits are Clifford-only and not a faithful universal ICM representation.
  • domain assumption Noise model: only CNOT gates are depolarizing with rate p_ncs; qubit initialization and measurement are noiseless.
    Stated in Sec. 3.1; excludes state-prep and measurement errors that would affect flag readout and post-selection.
  • domain assumption Flags can be protected by surface codes so that gates touching them have error rate p_f = m*p_ncs, without error-correcting the connecting CNOTs.
    Core to Sec. 2.4 and 3.4; the paper acknowledges resource estimates are lower bounds because CNOT error correction is not included.
  • domain assumption Surface code logical error rate formula p_f = 0.08*(p_ncs/0.0053)^{0.58d-0.27} from [24] is correct for the regimes used.
    Used in Sec. 3.4 to map m to distance; an empirical fit from prior literature, not independently verified here.
  • domain assumption Randomly selected 100 input strings are representative for failure-rate estimation.
    Used in Sec. 3.1; no proof of representativeness for CNOT-only circuits, and no seed is reported.

pith-pipeline@v1.3.0-alltime-deepseek · 10530 in / 17892 out tokens · 154902 ms · 2026-08-03T21:09:16.342375+00:00 · methodology

0 comments
read the original abstract

Quantum circuits will experience failures that lead to computational errors. We introduce Medusa, an automated compilation method for lowering a circuit's failure rate. Medusa uses flags to predict the absence of high-weight errors. Our method can numerically upper bound the failure rate of a circuit in the presence of flags, and fine tune the fault-tolerance of the flags in order to reach this bound. We assume the flags can have an increased fault-tolerance as a result of applying surface QECs to the gates interacting with them. We use circuit level depolarizing noise to evaluate the effectiveness of these flags in revealing the absence of the high-weight stabilizers. Medusa reduces the cost of quantum-error-correction (QEC) because the underlying circuit has a lower failure rate. We benchmark our approach using structured quantum circuits representative of ripple-carry adders. In particular, our flag scheme demonstrates that for adder-like circuits, the failure rate of large-scale implementations can be lowered to fit the failure rates of smaller-scale circuits. We show numerically that a slight improvement in the local fault-tolerance of the flag-qubits can lead to a reduction in the overall failure rate of the entire quantum circuit.

Figures

Figures reproduced from arXiv: 2511.16289 by Alexandru Paler, Karoliina Oksanen, Quan Hoang.

Figure 1
Figure 1. Figure 1: Quantum circuits: (a) Medusa is based on ICM cir￾cuits [25, 31], e.g. gate teleportation, which consist entirely of CNOT gates, initializations and measurements; (b) A bit flip error occurring in location X in the original circuit is caught by the flag: the measurement of the flag would give 1 instead of 0 as the error is propagated to the flag through the blue CNOT gate. At the end of the circuit the erro… view at source ↗
Figure 2
Figure 2. Figure 2: Flag circuits obtained after adding a flag qubit and [PITH_FULL_IMAGE:figures/full_fig_p001_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Medusa for zoned architectures. Illustration for a hypothetical 4 qubit circuit (black circles): (a) The qubits are stored in the storage zone; (b) in order to add two flags to the circuit, two of the qubits are moved to a green encoding zone and are encoded into cat states (dark green), and the resulting encoded state is performing the first CNOT with a fault-tolerant flag (dark blue rectangle) residing i… view at source ↗
Figure 4
Figure 4. Figure 4: Benchmarking results for using 5 log2 (𝑁) flags, where N is the size of the adder-like circuit. The horizontal axis is the noise channel strength i.e. the error rate at each gate. (a) The failure rate after post selection the flags; (b) The acceptance rate i.e. what percentage of runs is accepted during post selection using the flags; (c) The difference in failure rate, i.e. the difference between the fail… view at source ↗
Figure 5
Figure 5. Figure 5: Improving a circuit’s total failure rate (horizontal [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗

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This paper was first reviewed by deepseek-v4-flash on August 3, 2026.