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arxiv: 2601.04363 · v2 · submitted 2026-01-07 · ❄️ cond-mat.supr-con · cs.ET

Inductorless Fast Phase Logic: Enabling Two-Order-of-Magnitude Density Scaling for Superconductor VLSI

Sasan Razmkhah , Douglas Scott Holmes , Massoud Pedram This is my paper

Pith reviewed 2026-05-16 16:04 UTC · model grok-4.3

classification ❄️ cond-mat.supr-con cs.ET
keywords fast phase logicjosephson junctionssuperconductor VLSIRSFQdensity scalingpi-junctionsinductorless circuitsNbTiN fabrication
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The pith

Fast phase logic replaces inductors with stacked Josephson junctions to reach 100x higher density in superconductor circuits.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Fast phase logic (FPL) introduces a new family of superconductor digital circuits that combines switching 0-Josephson junctions, non-switching 0-JJ stacks, and π-JJs. This mix creates compact cell layouts without large inductive loops, speeds pulse propagation, and lowers the bias current needed for operation. The paper projects that pairing FPL with a proposed NbTiN fabrication process using high-Jc self-shunted junctions and AlN dielectrics will deliver two orders of magnitude more integration density than conventional RSFQ logic plus a five-fold drop in supply current. These changes would shorten interconnect delays, raise overall throughput, and improve direct connections to CMOS electronics. The gains are shown through an architectural study of a fast Fourier transform circuit.

Core claim

Fast Phase Logic (FPL) is a digital superconductor logic family that employs switching 0-Josephson junctions, non-switching 0-JJ stacks, and π-JJs to create flexible, automatable cell layouts with minimized inductive loops. The approach reduces susceptibility to trapped flux and crosstalk while π-JJs cut the required bias current. When implemented with the proposed NbTiN-based process featuring high-Jc self-shunted junctions and AlN dielectrics, FPL is projected to achieve a two-order-of-magnitude increase in integration density over RSFQ logic and a five-fold reduction in supply current, lowering latency and improving CMOS compatibility as evaluated in an FFT architectural study.

What carries the argument

The central mechanism is the replacement of inductive loops with non-switching 0-JJ stacks and phase-shifting π-JJs, which enables compact, inductorless cell layouts while reducing bias current and trapped-flux susceptibility.

Load-bearing premise

The proposed NbTiN fabrication process with high-Jc self-shunted Josephson junctions and AlN dielectrics will produce the compact layouts and low flux susceptibility without major yield or performance shortfalls.

What would settle it

Fabrication and high-speed testing of a prototype FPL FFT circuit that either reaches or falls short of the projected 100x density gain and 5x supply-current reduction compared with an equivalent RSFQ implementation.

Figures

Figures reproduced from arXiv: 2601.04363 by Douglas Scott Holmes, Massoud Pedram, Sasan Razmkhah.

Figure 1
Figure 1. Figure 1: Josephson junction and different Josephson [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FPL circuit and cell design: (a) With π￾JJs, two types of loops are formed, loops with odd or even numbers of πs. The odd-number loop will have a permanent screening current flowing through it. (b) A pulse propagation cell in FPL, (c) A DFF cell that can also be used as shift register memory, (d) A pulse splitter cell that will double the incoming pulse and send it on two different paths, (e) A logic OR ga… view at source ↗
Figure 4
Figure 4. Figure 4: FPL asynchronous AND gate schematic and NGSPICE simulation results. The inputs are applied to a DC/FPL cell over a 50 Ω resistor. The DC/FPL converters trigger on the rising edge of the input and generate flux-quantized pulses whenever the voltage crosses a defined threshold. The gate operates on a threshold principle, producing an output pulse when the combined input currents exceed the critical current o… view at source ↗
Figure 6
Figure 6. Figure 6: The block diagram architecture of an SDF [PITH_FULL_IMAGE:figures/full_fig_p008_6.png] view at source ↗
Figure 5
Figure 5. Figure 5: FPL VLSI: (a) An H-tree for clock distribution between macrocells, (b) Macrocell (4-1 parallel to serial converter) implementation with the JTL delay lines, the solid green cells are logic, and the rest are splitter and delay lines, (c) A tool designed for automated cell layout design and optimization, (d) shift register and random access memory design for pulse-based technology particularly effective in s… view at source ↗
Figure 7
Figure 7. Figure 7: Our proposed stacking method is based on [PITH_FULL_IMAGE:figures/full_fig_p010_7.png] view at source ↗
read the original abstract

Fast phase logic (FPL) is a novel digital superconductor electronic (SCE) logic family that employs multiple junction types, including switching 0-Josephson junctions (0-JJs), non-switching 0-JJ stacks, and $\pi$-JJs. FPL enables flexible, automatable cell layouts, faster pulse propagation, reduced bias current via phase-shifting $\pi$-JJs, and minimized inductive loops, thereby reducing susceptibility to trapped flux and crosstalk. A fabrication process to support FPL is proposed. NbTiN superconductors offer small grain sizes, smooth surfaces, and thermal stability up to 400~$^\circ$C, while high-$J_c$, self-shunted JJs enable compact devices. AlN dielectrics provide good crystal matching to NbTiN, improving superconducting properties. Projections indicate that FPL, combined with the proposed process, can achieve a two-order-of-magnitude increase in integration density over conventional RSFQ logic and a five-fold reduction in supply current. The increased density reduces latency and improves computational throughput, while NbTiN-based devices provide higher output voltage and impedance, improving compatibility with CMOS circuits. Further fabrication advancements, such as higher-$J_c$ NbTiN-based JJs, higher processing temperatures, and stacked JJ structures, could enhance FPL implementation and scalability toward very large-scale integration (VLSI). FPL has the potential to significantly advance SCE technology, with near-term applications in accelerator cores for signal processing and artificial intelligence, and long-term potential in supercomputing. Its advantages are evaluated through an architectural study of a fast Fourier transform (FFT) circuit, with comparisons to CMOS and SFQ technologies.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 2 minor

Summary. The manuscript introduces Fast Phase Logic (FPL), a new superconductor digital logic family that uses switching 0-Josephson junctions, non-switching 0-JJ stacks, and phase-shifting π-JJs to enable inductorless cell layouts. It proposes a NbTiN-based fabrication process with high-Jc self-shunted junctions and AlN dielectrics for improved thermal stability and lattice matching. Projections based on this process and an architectural study of an FFT circuit claim a two-order-of-magnitude increase in integration density over conventional RSFQ logic together with a five-fold reduction in supply current, plus improved CMOS compatibility via higher output voltage and impedance.

Significance. If the assumed NbTiN/AlN process parameters can be realized, FPL would represent a substantial advance in superconductor electronics by removing inductive loops, lowering trapped-flux susceptibility, and enabling VLSI-scale integration. The architectural FFT comparison provides a concrete, falsifiable benchmark against RSFQ and CMOS that could guide further development. The proposal of multiple junction types and stacked structures is a genuine conceptual contribution even if the quantitative scaling factors require additional validation.

major comments (3)
  1. [Abstract] Abstract and the projections paragraph: the stated 100× density gain and 5× bias-current reduction are presented as direct outcomes of the proposed NbTiN process and FPL cell library, yet no layout-area calculations, inductance values, or circuit-level simulations are supplied to derive these factors from the assumed Jc, grain size, or dielectric properties.
  2. [Architectural study] Architectural FFT study section: the comparison to RSFQ and CMOS reports latency and throughput improvements but supplies no parameter-spread analysis, Monte-Carlo yield estimates, or error bars on the projected density and current figures, leaving the scaling claims sensitive to any deviation in the assumed high-Jc self-shunted JJ characteristics.
  3. [Fabrication process] Fabrication process proposal: the claim that NbTiN offers thermal stability to 400 °C, small grain size, and good AlN lattice matching simultaneously enabling compact inductorless layouts rests on literature values rather than process-specific data or test structures; if any of these properties fall short, the inductorless advantage and derived density numbers do not follow.
minor comments (2)
  1. [Introduction] Notation for the three junction types (0-JJ, 0-JJ stack, π-JJ) is introduced without a compact table summarizing their roles, critical currents, and phase shifts; a single summary table would improve readability.
  2. [Abstract] The abstract states that FPL reduces susceptibility to trapped flux and crosstalk but does not quantify the reduction in loop area or mutual inductance relative to RSFQ; a brief numerical estimate would strengthen the claim.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for the constructive and insightful comments, which help clarify the presentation of our projections and assumptions. We agree that the manuscript would benefit from greater transparency on how the scaling estimates are derived and from explicit qualification of the fabrication proposal. Below we respond point by point to the major comments. We will incorporate revisions to address each point while preserving the conceptual focus of the work.

read point-by-point responses

  1. Referee: [Abstract] Abstract and the projections paragraph: the stated 100× density gain and 5× bias-current reduction are presented as direct outcomes of the proposed NbTiN process and FPL cell library, yet no layout-area calculations, inductance values, or circuit-level simulations are supplied to derive these factors from the assumed Jc, grain size, or dielectric properties.

    Authors: We agree that the abstract and projections would be strengthened by explicit derivation of the scaling factors. The 100× density estimate follows from the removal of large inductive loops (typically 50–70 % of RSFQ cell area) plus the use of compact high-Jc self-shunted junctions and thin AlN dielectrics; the 5× bias-current reduction arises from π-JJ phase shifting that eliminates large bias resistors. These are order-of-magnitude arguments based on the cell topologies described in the manuscript. In revision we will add a short subsection with explicit area estimates using representative junction diameters and layout rules drawn from the cited literature, and we will qualify the numbers as estimates pending full circuit simulation. revision: yes

  2. Referee: [Architectural study] Architectural FFT study section: the comparison to RSFQ and CMOS reports latency and throughput improvements but supplies no parameter-spread analysis, Monte-Carlo yield estimates, or error bars on the projected density and current figures, leaving the scaling claims sensitive to any deviation in the assumed high-Jc self-shunted JJ characteristics.

    Authors: The FFT study is a high-level architectural comparison using nominal parameters from the proposed process. We acknowledge the absence of quantitative sensitivity analysis. In the revised manuscript we will add a dedicated paragraph discussing the principal assumptions (Jc uniformity, junction critical-current spread, and dielectric thickness variation) and will include qualitative error estimates and bounding cases drawn from published NbTiN and AlN process data. Full Monte-Carlo yield modeling lies outside the scope of this proposal paper and will be noted as future work. revision: partial

  3. Referee: [Fabrication process] Fabrication process proposal: the claim that NbTiN offers thermal stability to 400 °C, small grain size, and good AlN lattice matching simultaneously enabling compact inductorless layouts rests on literature values rather than process-specific data or test structures; if any of these properties fall short, the inductorless advantage and derived density numbers do not follow.

    Authors: The fabrication section presents a process proposal grounded in established NbTiN and AlN literature values, as is standard for conceptual device papers. We will revise the text to state explicitly that the claimed properties are literature-supported projections and to add further references to experimental NbTiN/AlN studies. The inductorless advantage is conditional on realizing the stated parameters; we will emphasize this conditionality and outline the minimal experimental validation steps required to confirm the projections. revision: yes

Circularity Check

0 steps flagged

No significant circularity in derivation chain

full rationale

The paper introduces FPL as a novel logic family using multiple JJ types and proposes a NbTiN/AlN fabrication process, then states density and current projections as combined outcomes. No self-definitional loops, fitted parameters renamed as predictions, or load-bearing self-citations appear in the abstract or described content. The FFT architectural comparison is presented as an evaluation rather than a derivation that reduces to its own inputs by construction. Claims rest on forward-looking assumptions about process performance, which are independent of the stated results and do not exhibit the enumerated circular patterns.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 1 invented entities

The central projections rest on unverified assumptions about material behavior and device scaling that are stated without independent evidence in the abstract.

free parameters (1)
  • density scaling factor
    The two-order-of-magnitude density gain is projected from reduced inductive loops and compact layouts but no explicit fitting procedure is shown.
axioms (1)
  • domain assumption NbTiN offers small grain sizes, smooth surfaces, and thermal stability up to 400°C while AlN provides good crystal matching
    Invoked to justify the proposed fabrication process and improved superconducting properties.
invented entities (1)
  • Fast Phase Logic (FPL) cell library no independent evidence
    purpose: Inductorless logic family using mixed 0-JJ and pi-JJ types
    New logic style introduced to achieve the density claims; no independent experimental evidence provided.

pith-pipeline@v0.9.0 · 5618 in / 1495 out tokens · 57145 ms · 2026-05-16T16:04:14.272138+00:00 · methodology

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