arxiv: 2601.21528 · v2 · submitted 2026-01-29 · 🪐 quant-ph

Recognition: 2 theorem links

· Lean Theorem

High-Coherence and High-frequency Quantum Computing: The Design of a High-Frequency, High-Coherence and Scalable Quantum Computing Architecture

Masroor H. S. Bukhari

Authors on Pith no claims yet

Pith reviewed 2026-05-16 09:51 UTC · model grok-4.3

classification 🪐 quant-ph

keywords high-frequency transmonquantum computing architecturesuperconducting qubitstantalum junctionscoherence timequality factorscalable quantum computinghigh-coherence design

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The pith

A proposed 8-qubit transmon chip operates at 12 GHz using tantalum and niobium tri-layer junctions to reach 1.9 ms relaxation times and quality factors of 2.75 x 10^7.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper proposes a high-frequency transmon architecture that runs qubits in the 11-13.5 GHz band, centered at 12 GHz, to improve coherence and enable more compact, scalable quantum processors. The design incorporates a new connection topology for an initial 8-qubit layout that can expand to 72 qubits on one chip, relying on tantalum and Nb/Al/AlOx tri-layer junctions fabricated on high-resistivity silicon. If the targeted performance holds, the longer relaxation times would support faster gates, lower charge noise, and operation at somewhat higher temperatures than standard few-GHz transmons. The work draws on external advances in junction manufacturing to minimize losses that typically limit high-frequency operation.

Core claim

The report presents the proposal and preliminary design of an 8-qubit transmon architecture (with possible upgrade to up to 72 qubits on a chip) working beyond 10 GHz in the range of 11 to 13.5 GHz, with a central optimal operating frequency of 12.0 GHz and a new connection topology, with the aim to achieve average relaxation times of up to 1.9 ms with average quality factors of up to 2.75 x 10^7 by exploiting advances in superconducting junction manufacturing using tantalum and niobium/aluminum/aluminum oxide tri-layer structures on high-resistivity silicon substrates.

What carries the argument

High-frequency transmon qubit design using tantalum and Nb/Al/AlOx tri-layer junctions on high-resistivity silicon, together with a new connection topology for the multi-qubit layout.

Load-bearing premise

The referenced advances in tantalum and Nb/Al/AlOx tri-layer junction fabrication will deliver the stated coherence times and quality factors when operated in the 11-13.5 GHz range without new high-frequency loss mechanisms.

What would settle it

Fabricated devices measured at 12 GHz showing average relaxation times well below 1.9 ms or quality factors well below 2.75 x 10^7 would disprove the performance targets.

Figures

Figures reproduced from arXiv: 2601.21528 by Masroor H. S. Bukhari.

**Figure 1.** Figure 1: A Simple Tunable Transmon Qubit with Two Josephson Junctions and a Large Shunt/Bias Capacitor (and Flux Biasing) [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗

**Figure 2.** Figure 2: A Complete Transmon and Resonator System with various Quantum Buses. [PITH_FULL_IMAGE:figures/full_fig_p006_2.png] view at source ↗

**Figure 3.** Figure 3: illustrates an overview of a proposal of the simple Quad -Transmon-Coupler (QTC) architecture, presented here. The transmons are depicted by a “Q”, such that four transmons are connected via their respective couplers (depicted by a symbol of capacitor) to one resonator (depicted by an orange square in the centre.) There can be many variations of this simple topology where the number of transmons, as well a… view at source ↗

**Figure 5.** Figure 5: The Experimental Setup Overview: A Schematic of readout and control electronics, including the [PITH_FULL_IMAGE:figures/full_fig_p016_5.png] view at source ↗

**Figure 6.** Figure 6: A Schematic of the Readout and Control Electronics, the Central Part of the Scheme is a Xilinx Corp. [PITH_FULL_IMAGE:figures/full_fig_p017_6.png] view at source ↗

**Figure 7.** Figure 7: The Complete Measurement Setup on Mounted on a Dilution Refrigerator (the drawing of the dilution refrigerator is inspired by the work by Cai et al. [46]). In terms of fabrication, packaging and three-dimensional integration of this or any highfrequency high-coherence qubit design the main concerns should be reducing the parasitic twolevel system losses among other things [PITH_FULL_IMAGE:figures/full_f… view at source ↗

**Figure 8.** Figure 8: An Overview of Chip Connections and Packaging as well as the Triple [PITH_FULL_IMAGE:figures/full_fig_p019_8.png] view at source ↗

read the original abstract

High-coherence, fault-tolerant and scalable quantum computing architectures with unprecedented long coherence times, faster gates, low losses and low bit-flip errors may be one of the only ways forward to achieve the true quantum advantage. In this context, high-frequency high-coherence (HCQC) qubits with new high-performance topologies could be a significant step towards efficient and high-fidelity quantum computing by facilitating compact size, higher scalability and higher than conventional operating temperatures. Although transmon type qubits are designed and manufactured routinely in the range of a few Giga-Hertz, normally from 4 to 6 GHz (and, at times, up to around 10GHz), achieving higher-frequency operation has challenges and entails special design and manufacturing considerations. This report presents the proposal and preliminary design of an 8-qubit transmon (with possible upgrade to up to 72 qubits on a chip) architecture working beyond an operation frequency of 10GHz, as well as presents a new connection topology. The current design spans a range of around 11 to 13.5 GHz (with a possible full range of 9-12GHz at the moment), with a central optimal operating frequency of 12.0 GHz, with the aim to possibly achieve a stable, compact and low-charge-noise operation, as lowest as possible as per the existing fabrication techniques. The aim is to achieve average relaxation times of up to 1.9ms with average quality factors of up to 2.75 x 10^7 after trials, while exploiting the new advances in superconducting junction manufacturing using tantalum and niobium/aluminum/aluminum oxide tri-layer structures on high-resistivity silicon substrates (carried out elsewhere by other groups and referred in this report).

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

This is a design proposal for an 8-qubit transmon chip at 12 GHz that projects 1.9 ms relaxation times, but the numbers are taken from external papers without any supporting calculations or simulations for the higher frequency.

read the letter

This paper is a design proposal for an 8-qubit transmon system operating around 12 GHz, with the goal of reaching relaxation times of 1.9 ms and quality factors of 2.75e7 using tantalum and Nb/Al/AlOx structures. The central numbers are drawn from external fabrication results rather than derived or simulated here. The work does lay out a specific topology and frequency band from 11 to 13.5 GHz, along with plans for scaling up to 72 qubits. It references recent material improvements and discusses how higher frequencies might allow denser layouts and relaxed cooling needs. That part is straightforward engineering thinking. The soft spot is that no frequency-dependent loss analysis appears in the manuscript. The targets assume the cited lower-frequency coherence results will translate directly to 12 GHz, without estimates for increased losses from quasiparticles, radiation, or dielectric effects that often worsen at higher frequencies. There are no simulations of the qubit geometry or any new calculations to support the projections. This is the kind of paper that might appeal to groups focused on superconducting qubit fabrication and chip design. Someone looking for validated measurements or first-principles modeling will not find it here. It could go to peer review so that experts can comment on the proposed layout and whether the material citations are applied reasonably, but the performance claims will require more evidence to hold up.

Referee Report

2 major / 1 minor

Summary. The manuscript proposes a preliminary design for an 8-qubit (scalable to 72-qubit) transmon architecture operating in the 11–13.5 GHz band with a central frequency of 12 GHz. It introduces a new connection topology and targets average relaxation times of 1.9 ms and quality factors of 2.75 × 10^7 by leveraging external advances in tantalum and Nb/Al/AlOx tri-layer junctions fabricated on high-resistivity silicon, with the performance figures presented as aims to be realized after trials.

Significance. If the stated coherence and quality-factor targets can be realized at these elevated frequencies, the architecture could enable more compact qubit layouts, faster gates, and improved scalability for fault-tolerant quantum computing. The design's emphasis on high-frequency operation and new topologies is a potentially useful contribution to the literature on superconducting qubit engineering, provided the projections are substantiated.

major comments (2)

[Abstract] Abstract: The central performance targets (T1 up to 1.9 ms and Q up to 2.75 × 10^7 at 12 GHz) are presented as design aims based on cited external fabrication results. No frequency-dependent loss modeling, electromagnetic simulations, or scaling analysis is supplied to justify why the referenced lower-frequency coherence data remain valid in the 11–13.5 GHz regime, where mechanisms such as quasiparticle generation, dielectric-loss scaling with ω, or radiation into higher-order modes could degrade performance.
The manuscript states that the targets will be achieved 'after trials' but supplies neither a quantitative estimate of additional high-frequency loss channels nor any circuit-QED simulation of the proposed geometry at the target frequencies. This leaves the load-bearing claim that the architecture can meet the quoted metrics unsupported by internal analysis.

minor comments (1)

[Abstract] The sentence 'with the aim to possibly achieve a stable, compact and low-charge-noise operation, as lowest as possible as per the existing fabrication techniques' is grammatically awkward and should be rephrased for clarity.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their insightful comments regarding the justification of the high-frequency performance targets. We have revised the manuscript to address these concerns by adding discussions on potential loss mechanisms and clarifying the preliminary nature of our design proposal.

read point-by-point responses

Referee: [Abstract] Abstract: The central performance targets (T1 up to 1.9 ms and Q up to 2.75 × 10^7 at 12 GHz) are presented as design aims based on cited external fabrication results. No frequency-dependent loss modeling, electromagnetic simulations, or scaling analysis is supplied to justify why the referenced lower-frequency coherence data remain valid in the 11–13.5 GHz regime, where mechanisms such as quasiparticle generation, dielectric-loss scaling with ω, or radiation into higher-order modes could degrade performance.

Authors: We acknowledge the validity of this observation. The targets are extrapolated from lower-frequency results cited in the manuscript. In the revised version, we have added a new paragraph in the design section discussing frequency-dependent loss mechanisms, including references to studies on quasiparticle effects and dielectric losses at higher frequencies. We emphasize that the design aims to leverage material improvements to mitigate these effects, though full quantitative modeling is left for future experimental work. The abstract has been updated to reflect this. revision: yes
Referee: [—] The manuscript states that the targets will be achieved 'after trials' but supplies neither a quantitative estimate of additional high-frequency loss channels nor any circuit-QED simulation of the proposed geometry at the target frequencies. This leaves the load-bearing claim that the architecture can meet the quoted metrics unsupported by internal analysis.

Authors: We agree that additional analysis would be beneficial. We have included estimates of potential additional losses due to higher-order modes and radiation, based on analytical approximations, and referenced relevant circuit-QED literature. The phrase 'after trials' has been clarified to indicate that it refers to iterative fabrication and testing by the groups providing the material advancements. This provides better support for the projected metrics within the context of a design proposal. revision: yes

Circularity Check

1 steps flagged

Performance targets (1.9 ms T1, 2.75e7 Q at 12 GHz) imported from external citations without internal derivation or frequency-scaling analysis

specific steps

fitted input called prediction [Abstract]
"The aim is to achieve average relaxation times of up to 1.9ms with average quality factors of up to 2.75 x 10^7 after trials, while exploiting the new advances in superconducting junction manufacturing using tantalum and niobium/aluminum/aluminum oxide tri-layer structures on high-resistivity silicon substrates (carried out elsewhere by other groups and referred in this report)."

The specific numerical targets are presented as the intended outcome of the proposed architecture, yet they are not computed, simulated, or scaled from any design parameter inside the manuscript; they are directly adopted from the referenced external fabrication results. The 'prediction' is therefore the input citation restated as a design goal.

full rationale

The manuscript is a design proposal whose central performance claims are not obtained from any equation, simulation, or first-principles argument inside the paper. The quoted relaxation time and quality-factor numbers are explicitly labeled as aims that will be reached 'after trials' by exploiting fabrication advances 'carried out elsewhere by other groups and referred in this report.' No load-bearing derivation chain exists to reduce; the numbers are simply restated expectations from the cited literature. This matches the 'fitted input called prediction' pattern at the level of the abstract claim, producing partial circularity (score 6) but not a fully self-contained loop.

Axiom & Free-Parameter Ledger

2 free parameters · 1 axioms · 0 invented entities

The proposal rests on standard transmon assumptions plus external fabrication results; no new free parameters are fitted here, but the target performance numbers function as design goals drawn from prior literature.

free parameters (2)

Central operating frequency = 12.0 GHz
Chosen as 12.0 GHz within the 11-13.5 GHz design window to optimize for low charge noise.
Target relaxation time = 1.9 ms
Projected maximum of 1.9 ms based on expected quality factor from external fabrication.

axioms (1)

domain assumption Higher operating frequency reduces charge noise and enables compact, scalable layouts while preserving coherence when using advanced materials.
Invoked throughout the abstract as the rationale for moving beyond 10 GHz.

pith-pipeline@v0.9.0 · 5629 in / 1395 out tokens · 22355 ms · 2026-05-16T09:51:47.074576+00:00 · methodology

discussion (0)

Lean theorems connected to this paper

Citations machine-checked in the Pith Canon. Every link opens the source theorem in the public Lean library.

IndisputableMonolith/Cost/FunctionalEquation.lean washburn_uniqueness_aczel unclear

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unclear
Relation between the paper passage and the cited Recognition theorem.

The transition frequency ... v01 = √(8 EJ EC)/h - EC/h ... EJ = Φ0 Ic / 2π, EC = e² / 2 CΣ
IndisputableMonolith/Foundation/AlphaDerivationExplicit.lean alphaInverseRS unclear

?

unclear
Relation between the paper passage and the cited Recognition theorem.

aim to achieve average relaxation times of up to 1.9 ms with average quality factors of up to 2.75 × 10^7 at 12.0 GHz

What do these tags mean?

matches: The paper's claim is directly supported by a theorem in the formal canon.
supports: The theorem supports part of the paper's argument, but the paper may add assumptions or extra steps.
extends: The paper goes beyond the formal theorem; the theorem is a base layer rather than the whole result.
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contradicts: The paper's claim conflicts with a theorem or certificate in the canon.
unclear: Pith found a possible connection, but the passage is too broad, indirect, or ambiguous to say the theorem truly supports the claim.

Reference graph

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