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arxiv: 2604.05147 · v1 · submitted 2026-04-06 · 💻 cs.CV · cs.CR

Lightweight True In-Pixel Encryption with FeFET Enabled Pixel Design for Secure Imaging

Md Rahatul Islam Udoy , Diego Ferrer , Wantong Li , Kai Ni , Sumeet Kumar Gupta , Ahmedullah Aziz This is my paper

Pith reviewed 2026-05-10 19:50 UTC · model grok-4.3

classification 💻 cs.CV cs.CR
keywords in-pixel encryptionFeFETsecure imagingCMOS pixelferroelectric transistoranalog encryptionimage sensor securityneural network attack resistance
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The pith

A CMOS pixel design encrypts photodiode signals in-place using programmable FeFET polarization states before any readout occurs.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents SecurePix, a compact pixel architecture that performs true in-pixel encryption by programming non-volatile multidomain polarization states in a ferroelectric field-effect transistor to create a key-specific analog transfer function. This converts raw photodiode voltage directly into an encrypted analog output inside the pixel, preventing exposure on readout lines. Simulations show the encryption drops ResNet-18 accuracy from 99.29 percent to 9.58 percent on MNIST and from 91.33 percent to 6.98 percent on CIFAR-10. Authorized recovery uses a lookup-table inverse mapping with the same symmetric key. The approach targets hardware-level protection with low power-delay products while fitting standard 45 nm CMOS layouts.

Core claim

SecurePix integrates a ferroelectric field-effect transistor into each CMOS pixel so that its programmable, non-volatile multidomain polarization states define a unique analog transfer characteristic. The photodiode voltage is thereby converted to an encrypted analog output within the pixel itself. Full-image tests confirm that this mapping reduces ResNet-18 recognition accuracy to near-random levels on standard datasets, while the same symmetric key enables lookup-table-based recovery for authorized users. Layouts achieve a pixel pitch of 2.33 by 3.01 square micrometers with per-pixel programming and sensing power-delay products of 17 and 1.25 microwatt-microseconds.

What carries the argument

Programmable non-volatile multidomain polarization states of the ferroelectric field-effect transistor that set each pixel's analog transfer characteristic for symmetric-key encryption.

If this is right

  • Authorized receivers recover original images via lookup-table inverse mapping using the shared symmetric key.
  • The design provides hardware-level security by encrypting before any data reaches readout lines or external interfaces.
  • Per-pixel power-delay products remain low at 17 microwatt-microseconds for programming and 1.25 for sensing.
  • The layout fits within a 2.33 by 3.01 square micrometer pitch in standard 45 nm CMOS, supporting dense arrays.
  • Neural-network-based inference attacks on captured images are strongly resisted as shown by the reported accuracy collapses.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • This analog encryption method could apply to other sensor types where pre-readout scrambling is needed to limit data leakage in edge devices.
  • If the polarization states prove stable across temperature and aging, the approach might reduce dependence on software encryption layers in power-constrained imaging systems.
  • Integration with existing CMOS image sensor processes appears feasible without major changes to array architecture.
  • Real-world testing under varied illumination and with actual noise sources would be required to confirm the encryption strength beyond simulation.

Load-bearing premise

The FeFET polarization states can be programmed reliably and stably to produce consistent analog encryption without being undermined by process variation, noise, or readout artifacts in actual fabricated hardware.

What would settle it

Fabricate a SecurePix array in silicon and measure whether the observed neural-network accuracy drops on MNIST and CIFAR-10 match the simulated values under real process variation and readout noise, or whether decryption lookup tables fail due to inconsistent transfer characteristics.

Figures

Figures reproduced from arXiv: 2604.05147 by Ahmedullah Aziz, Diego Ferrer, Kai Ni, Md Rahatul Islam Udoy, Sumeet Kumar Gupta, Wantong Li.

Figure 1
Figure 1. Figure 1: (a) A threat model: The image sensor operates entirely in a trusted domain and produces an unencrypted pixel array. During transmission through an untrusted channel, both a passive eavesdropper and an ML-based adversary can directly access the unencrypted pixel stream, enabling unauthorized scene reconstruction or automated recognition. (b) Proposed secure image sensor system. Each pixel produces an encryp… view at source ↗
Figure 2
Figure 2. Figure 2: (a) Schematic of a standard 3-transistor (3-T) active pixel circuit where, XRST, XSF, and XSL denote the reset, source-follower, and selector transistors, respectively. (b) Timing diagram of the 3-T pixel operation illustrating the integration (TINT), readout (TRD), and reset (TRST) phases. (c) Structure of an HfO2-based ferroelectric FET (FeFET). (d) Circuit-level symbol of the FeFET. (e) Multidomain pola… view at source ↗
Figure 3
Figure 3. Figure 3: (d), before setting the FeFET to the desired state, a negative gate pulse is first applied to drive the device toward the outer branch of its hysteresis loop. This step ensures that the initial ferroelectric domain configuration is well defined and consistent across programming cycles. Once the negative pulse has established this baseline state, a positive programming pulse is applied. The amplitude of thi… view at source ↗
Figure 4
Figure 4. Figure 4: (a) Array-level wiring diagram. All pixels in the same column share the FeFET gate-control line (VG ) and the pixel output metal lines. All pixels in the same row share the VDD, RST, GND, SL and Dis metal lines. (b) Layout of a section of the SecurePix array, implemented in Cadence Virtuoso using a 45-nm CMOS PDK. The figure shows the tiled arrangement of individual pixels along with the horizontal (≈2.33 … view at source ↗
Figure 5
Figure 5. Figure 5: Row-by-row FeFET programming procedure in the SecurePix array. (a) Initial stage of programming, where each pixel is assigned a target programming-voltage level (L1, L2, L3 …), corresponding to the desired FeFET polarization state. The G lines distribute the programming voltages, while the Dis and SL lines determine which row is actively programmed. (b) First-row programming. Sample programming voltages (L… view at source ↗
Figure 6
Figure 6. Figure 6: Sample encryption and decryption results produced by the proposed SecurePix system. (a–d) Each subfigure shows the input scene, the corresponding encrypted image generated by in-pixel FeFET modulation, and the decrypted reconstruction at the authorized receiver. (a) Real-world license plate example. (b) The standard Barbara test image.(c) CIFAR-10 sample. (d) MNIST digit sample. In all cases, the encrypted… view at source ↗
Figure 7
Figure 7. Figure 7: Recovery PSNR distribution across large-scale test sets for the proposed SecurePix system. (a) CIFAR-10 recovery PSNR distribution evaluated over 10,000 images. (b) MNIST recovery PSNR distribution evaluated over 10,000 images. Both histograms demonstrate consistently high reconstruction fidelity across the full datasets [PITH_FULL_IMAGE:figures/full_fig_p008_7.png] view at source ↗
read the original abstract

Ensuring end-to-end security in image sensors has become essential as visual data can be exposed through multiple stages of the imaging pipeline. Advanced protection requires encryption to occur before pixel values appear on any readout lines. This work introduces a secure pixel sensor (SecurePix), a compact CMOS-compatible pixel architecture that performs true in-pixel encryption using a symmetric key realized through programmable, non-volatile multidomain polarization states of a ferroelectric field-effect transistor. The pixel and array operations are designed and simulated in HSPICE, while a 45 nm CMOS process design kit is used for layout drawing. The resulting layout confirms a pixel pitch of 2.33 x 3.01 um^2. Each pixel's non-volatile programming level defines its analog transfer characteristic, enabling the photodiode voltage to be converted into an encrypted analog output within the pixel. Full-image evaluation shows that ResNet-18 recognition accuracy drops from 99.29 percent to 9.58 percent on MNIST and from 91.33 percent to 6.98 percent on CIFAR-10 after encryption, indicating strong resistance to neural-network-based inference. Lookup-table-based inverse mapping enables recovery for authorized receivers using the same symmetric key. Based on HSPICE simulation, the SecurePix achieves a per-pixel programming power-delay product of 17 uW us and a per-pixel sensing power-delay product of 1.25 uW us, demonstrating low-overhead hardware-level protection.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

1 major / 2 minor

Summary. The paper introduces SecurePix, a compact CMOS-compatible pixel architecture for true in-pixel encryption. It uses programmable non-volatile multidomain polarization states in a ferroelectric field-effect transistor (FeFET) to realize a symmetric-key analog transfer function that scrambles photodiode voltage into an encrypted output before readout. HSPICE simulations with a 45 nm PDK and corresponding layout are presented, reporting a pixel pitch of 2.33 × 3.01 μm², per-pixel programming power-delay product of 17 μW·μs, sensing power-delay product of 1.25 μW·μs, and post-encryption ResNet-18 accuracy collapse from 99.29 % to 9.58 % on MNIST and from 91.33 % to 6.98 % on CIFAR-10. Authorized decryption is performed via a lookup-table inverse mapping that uses the same key.

Significance. If the reported accuracy collapses prove robust under realistic device variation, the work would constitute a meaningful hardware-level contribution to end-to-end secure imaging by moving encryption inside the pixel with modest area and power overhead. The FeFET-based analog encryption approach and the concrete MNIST/CIFAR-10 numbers are the strongest elements; the 45 nm layout and explicit power-delay products also provide useful engineering data. The absence of variability or noise analysis, however, leaves the central security claim incompletely supported.

major comments (1)
  1. [Abstract / Simulation Results] Abstract and simulation description: the central security claim—that the FeFET-programmed analog transfer curves produce outputs that reduce ResNet-18 accuracy to ~7–10 %—rests entirely on nominal HSPICE runs. No Monte-Carlo analysis, FeFET-specific variation models (imprint, fatigue, threshold-voltage spread), retention-drift simulation, or photodiode-to-output noise budget is reported. Because even modest variation could collapse the intended output distribution and restore usable accuracy, this omission directly undermines the evidence for “strong resistance to neural-network-based inference.”
minor comments (2)
  1. [Abstract] Abstract: power-delay products are written as “17 uW us” and “1.25 uW us”; standard SI notation (μW·μs) and explicit units for both programming and sensing phases would improve clarity.
  2. [Evaluation] The manuscript states that “full-image evaluation” was performed but provides no information on the number of images, preprocessing, or whether the encrypted analog values were quantized before being fed to ResNet-18.

Simulated Author's Rebuttal

1 responses · 0 unresolved

We thank the referee for the constructive feedback and for recognizing the potential contribution of the FeFET-based in-pixel encryption approach. We address the major comment on variability analysis below and will strengthen the manuscript accordingly.

read point-by-point responses

  1. Referee: [Abstract / Simulation Results] Abstract and simulation description: the central security claim—that the FeFET-programmed analog transfer curves produce outputs that reduce ResNet-18 accuracy to ~7–10 %—rests entirely on nominal HSPICE runs. No Monte-Carlo analysis, FeFET-specific variation models (imprint, fatigue, threshold-voltage spread), retention-drift simulation, or photodiode-to-output noise budget is reported. Because even modest variation could collapse the intended output distribution and restore usable accuracy, this omission directly undermines the evidence for “strong resistance to neural-network-based inference.”

    Authors: We agree that the security claims would be more robust with explicit variability analysis, as the current results are based on nominal HSPICE simulations. In the revised manuscript we will add Monte-Carlo runs that incorporate FeFET variation models drawn from published literature (threshold-voltage spread, imprint, and fatigue) together with a first-order photodiode-to-output noise budget. These additions will quantify how the encrypted output distributions and downstream ResNet-18 accuracy behave under realistic device non-idealities. We expect the accuracy collapse to remain substantial, but the new data will allow readers to assess the margin directly. revision: yes

Circularity Check

0 steps flagged

No significant circularity; results derive from independent simulations

full rationale

The paper describes a FeFET-based pixel design, simulates its analog transfer characteristics and encryption behavior in HSPICE using a 45 nm PDK, then evaluates the resulting encrypted images on ResNet-18 for MNIST and CIFAR-10 accuracy drops, plus computes power-delay products from the same simulations. These quantities are produced outputs rather than quantities defined in terms of themselves or fitted parameters that presuppose the result. No self-citations are load-bearing for the core claims, no uniqueness theorems are invoked, and no ansatz or renaming reduces the derivation to its inputs by construction. The chain is self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

1 free parameters · 1 axioms · 1 invented entities

The design rests on standard assumptions about FeFET integration into CMOS and the ability of polarization states to produce stable analog encryption mappings; no new physical entities are postulated beyond the proposed pixel circuit.

free parameters (1)
  • FeFET polarization programming levels
    The specific multidomain states used to realize the symmetric key are chosen or tuned to achieve the desired encryption transfer function.
axioms (1)
  • domain assumption FeFET devices can be integrated into standard 45 nm CMOS processes with reliable non-volatile multidomain polarization control
    Invoked implicitly when claiming CMOS compatibility and programmable states for encryption.
invented entities (1)
  • SecurePix pixel architecture no independent evidence
    purpose: To realize true in-pixel encryption via FeFET states
    The pixel circuit is the novel design contribution; no independent evidence beyond simulation is provided.

pith-pipeline@v0.9.0 · 5574 in / 1508 out tokens · 61998 ms · 2026-05-10T19:50:17.092686+00:00 · methodology

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Reference graph

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