arxiv: 2604.11266 · v1 · submitted 2026-04-13 · ❄️ cond-mat.mes-hall

Recognition: unknown

Multiplexed cryo-CMOS control of an isolated double quantum dot

Mathieu Darnas , Mathilde Ouvrier-Buffet , Antoine Faurie , Jean-Baptiste Casanova , Benoit Bertrand , Candice Thomas , Jean Charbonnier , Jean-Philippe Michel

show 7 more authors

Bruna Cardoso Paz Yvain Thonnart Franck Badets Franck Balestro Matias Urdampilleta Tristan Meunier Baptiste Jadot

Authors on Pith no claims yet

Pith reviewed 2026-05-10 15:38 UTC · model grok-4.3

classification ❄️ cond-mat.mes-hall

keywords cryo-CMOSquantum dotsmultiplexingsample-and-holdsilicon DQDcharge stabilityspin qubits

0 comments

The pith

A cryo-CMOS multiplexing circuit reliably biases and pulses an isolated silicon double quantum dot at 0.5 K.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper tests whether sample-and-hold multiplexing implemented in a cryo-CMOS circuit can maintain the voltage stability required to operate a silicon double quantum dot. Working in the isolated regime where electrons remain trapped on the dots, the circuit sequentially refreshes voltages yet still permits deterministic loading of four electrons and stable access to every charge configuration from (4,0) to (0,4). The same hardware also supports fast voltage pulses that resolve single-electron tunneling events and stochastic switching at the (1,3)-(0,4) transition. Reducing the number of control lines while preserving charge and tunneling fidelity addresses a central obstacle to scaling spin-qubit processors beyond a few dozen dots.

Core claim

We experimentally demonstrate that a multiplexing cryo-CMOS circuit can reliably bias a silicon double quantum dot (DQD) at 0.5K. Exploiting the isolated regime, we show deterministic loading and isolation of four electrons and stable access to all five charge configurations from (4,0) to (0,4), despite the sequential voltage refreshing. We further demonstrate rapid voltage pulsing across an inter-dot transition, resolving single-electron tunneling events and stochastic switching at the (1,3)-(0,4) transition. These results confirm that SH-based multiplexed control is compatible with both static biasing and pulsing of isolated quantum dots.

What carries the argument

Sample-and-hold (SH) multiplexing in a cryo-CMOS circuit, which sequentially programs multiple gate voltages from a small number of input lines while holding each voltage steady on the device.

If this is right

Multiplexed control supports both static charge configurations and rapid pulsing without loss of tunneling resolution.
All charge states from (4,0) to (0,4) remain accessible and stable under sequential refreshing.
The approach reduces wiring density and thermal load, directly addressing scalability limits for large spin-qubit arrays.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The same multiplexing scheme could extend to arrays containing many more dots provided charge stability remains comparable.
Measuring the maximum refresh rate or channel count before noise appears would give a practical bound on scalability.
The technique may transfer to other gate-defined quantum systems that operate in similarly isolated regimes.

Load-bearing premise

The isolated regime of the double quantum dot supplies enough charge stability that sequential voltage refreshing during sample-and-hold multiplexing does not cause measurable charge leakage, excess noise, or loss of tunneling resolution.

What would settle it

Observation of charge leakage between dots, excess noise during voltage hold periods, or loss of single-electron tunneling resolution while the multiplexing circuit is active would falsify the compatibility claim.

Figures

Figures reproduced from arXiv: 2604.11266 by Antoine Faurie, Baptiste Jadot, Benoit Bertrand, Bruna Cardoso Paz, Candice Thomas, Franck Badets, Franck Balestro, Jean-Baptiste Casanova, Jean Charbonnier, Jean-Philippe Michel, Mathieu Darnas, Mathilde Ouvrier-Buffet, Matias Urdampilleta, Tristan Meunier, Yvain Thonnart.

**Figure 2.** Figure 2: FIG. 2. Voltage drift of the analog cell reconstructed with Coulomb peaks. [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗

**Figure 3.** Figure 3: FIG. 3. Inter-dot charge transitions between B2 and B3 for a [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

**Figure 4.** Figure 4: FIG. 4 [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗

**Figure 5.** Figure 5: FIG. 5. Illustration of the charge isolation protocol for the [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗

read the original abstract

Scalable spin-based quantum computing demands precise and stable control of a large number of gate-defined quantum dots while minimizing wiring complexity and thermal load. Control architectures based on sample-and-hold (SH) multiplexing techniques offer a promising solution by enabling sequential programming of several gate voltages using a limited number of input lines. However, the compatibility of such dynamic voltage refreshing with the stringent stability, noise, and speed requirements of quantum dot operation is an active subject of study. Here we experimentally demonstrate that a multiplexing cryo-CMOS circuit can reliably bias a silicon double quantum dot (DQD) at 0.5K. Exploiting the isolated regime, we show deterministic loading and isolation of four electrons and stable access to all five charge configurations from (4,0) to (0,4), despite the sequential voltage refreshing. We further demonstrate rapid voltage pulsing across an inter-dot transition, resolving single-electron tunneling events and stochastic switching at the (1,3)-(0,4) transition. These results confirm that SH-based multiplexed control is compatible with both static biasing and pulsing of isolated quantum dots, representing an important milestone toward scalable cryogenic control architectures for large-scale spin-qubit processors.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

This paper shows sample-and-hold cryo-CMOS multiplexing can bias and pulse an isolated Si DQD at 0.5 K with stable charge states and resolved tunneling, but lacks any non-multiplexed baseline so the actual overhead from refreshing stays unmeasured.

read the letter

The main point is that this experiment shows a cryo-CMOS sample-and-hold multiplexer can reliably set gate voltages on an isolated silicon double quantum dot at 0.5 K. They achieve stable access to charge states from (4,0) to (0,4) and can pulse to observe single-electron tunneling and stochastic switching at the (1,3)-(0,4) transition. The new element is the direct test on a functioning DQD rather than circuit-level validation alone. By working in the isolated regime, they demonstrate that the sequential refreshing does not prevent deterministic electron loading or the resolution of tunneling events. This is a useful compatibility check for reducing wiring and heat load in larger quantum dot arrays. It does well by focusing on a modest but relevant claim and delivering the basic functionality. The fact that they resolve real physics like stochastic switching indicates the system remains functional enough for quantum dot work. The weaker part is the missing baseline. All data are taken with the multiplexer active, with no comparison to continuous biasing on the same gates. Without numbers on charge noise during hold periods, leakage rates, or how long states remain stable, it's difficult to measure any penalty from the multiplexing cycle. The abstract is short on quantitative details and statistics, so the robustness is hard to assess without the full figures and methods. The stress-test concern holds based on what's described. This paper is for groups building cryogenic control hardware for spin qubits. It gives a practical data point on multiplexing viability that hardware designers can use when choosing architectures. I recommend it goes to peer review. The work is experimental and addresses a known bottleneck, so it deserves referee input even if it needs added controls and metrics.

Referee Report

2 major / 1 minor

Summary. The manuscript experimentally demonstrates that a sample-and-hold (SH) multiplexing cryo-CMOS circuit can bias and pulse an isolated silicon double quantum dot (DQD) at 0.5 K. It reports deterministic loading and isolation of four electrons with stable access to all charge configurations from (4,0) to (0,4), plus resolution of single-electron tunneling events and stochastic switching at the (1,3)-(0,4) transition, despite sequential voltage refreshing.

Significance. If the compatibility claim holds under quantitative scrutiny, the result is significant as a proof-of-principle that SH-based multiplexed control can meet the stability and noise requirements of isolated quantum dots, advancing scalable cryogenic architectures that reduce wiring complexity and thermal load for large-scale spin-qubit processors.

major comments (2)

[Abstract / Results] Abstract and main results: the central claim that SH multiplexing is 'compatible with both static biasing and pulsing' rests on qualitative observations of charge configurations and tunneling events under multiplexed operation only. No quantitative metrics (charge-noise PSD during hold intervals, hold-time leakage rates, tunneling-rate statistics, or stability-time distributions) are provided to bound any degradation from the refreshing cycle.
[Results] Results section: no baseline data with continuous (non-multiplexed) gate biasing on the same device are shown. Without this control, the observations are consistent with compatibility but do not isolate the incremental effect of sequential voltage refreshing on charge leakage, excess noise, or tunneling resolution.

minor comments (1)

[Introduction] The description of the isolated regime and its role in suppressing leakage during hold intervals could be expanded with a brief reference to prior literature on charge stability in Si DQDs.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the careful and constructive review of our manuscript. We address the major comments point by point below, providing clarifications on the evidence presented and indicating where revisions will be made to strengthen the manuscript.

read point-by-point responses

Referee: [Abstract / Results] Abstract and main results: the central claim that SH multiplexing is 'compatible with both static biasing and pulsing' rests on qualitative observations of charge configurations and tunneling events under multiplexed operation only. No quantitative metrics (charge-noise PSD during hold intervals, hold-time leakage rates, tunneling-rate statistics, or stability-time distributions) are provided to bound any degradation from the refreshing cycle.

Authors: The central claim is grounded in the experimental observation that, under SH multiplexing with its inherent sequential refreshing, the device supports deterministic loading and isolation of four electrons, stable access to all charge configurations from (4,0) to (0,4), and clear resolution of single-electron tunneling events including stochastic switching at the (1,3)-(0,4) transition during fast pulsing. These outcomes were achieved without apparent failure attributable to the refreshing cycle, providing direct evidence of compatibility for the targeted operations. We agree that quantitative metrics such as charge-noise PSD or hold-time leakage rates would allow tighter bounds on any degradation and would strengthen the presentation. In the revised manuscript we will add a discussion of the observed hold intervals and the durations over which charge configurations remained stable, together with any available estimates of leakage or noise inferred from the charge stability diagrams. revision: partial
Referee: [Results] Results section: no baseline data with continuous (non-multiplexed) gate biasing on the same device are shown. Without this control, the observations are consistent with compatibility but do not isolate the incremental effect of sequential voltage refreshing on charge leakage, excess noise, or tunneling resolution.

Authors: We acknowledge that a direct comparison with continuous biasing on the identical device would more cleanly isolate any incremental effects of the refreshing cycle. The present experimental setup and cryo-CMOS circuit are configured specifically for multiplexed operation; reconfiguring for continuous biasing on the same device would require substantial hardware modifications not available within this study. The data nevertheless show that all required functionalities—stable multi-electron configurations and resolved tunneling dynamics—are achieved under multiplexed control. We interpret this as evidence that any effects from refreshing remain compatible with the demonstrated level of performance. In revision we will explicitly note this limitation in the discussion section and clarify that the results establish functional compatibility rather than a quantitative decomposition of incremental degradation. revision: no

Circularity Check

0 steps flagged

No derivation chain present; purely experimental

full rationale

The manuscript is an experimental report demonstrating multiplexed cryo-CMOS biasing of an isolated silicon DQD at 0.5 K. It contains no equations, fitted models, ansatzes, uniqueness theorems, or derivation steps that could reduce to inputs by construction. All claims rest on direct measurements of charge states ((4,0) to (0,4)) and single-electron tunneling events under the multiplexed protocol. No self-citation load-bearing arguments or renaming of known results appear. The result is therefore self-contained as an empirical observation and receives the default non-circularity score.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

Experimental demonstration paper; no explicit free parameters or invented entities are introduced in the abstract. The central claim rests on one domain assumption about charge stability.

axioms (1)

domain assumption Charge stability in the isolated regime of the DQD is sufficient to maintain configurations during the hold periods of sample-and-hold multiplexing.
Invoked to explain compatibility of sequential refreshing with stable biasing and pulsing; appears in the abstract's emphasis on the isolated regime.

pith-pipeline@v0.9.0 · 5572 in / 1393 out tokens · 124757 ms · 2026-05-10T15:38:51.533382+00:00 · methodology

discussion (0)

Reference graph

Works this paper leans on

17 extracted references · 2 canonical work pages · 1 internal anchor

[1]

S. G. J. Philips, M. T. Mądzik, S. V. Amitonov, S. L. de Snoo, M. Russ, N. Kalhor, C. Volk, W. I. L. Lawrie, D. Brousse, L. Tryputen, B. P. Wuetz, A. Sammak, M. Veldhorst, G. Scappucci, and L. M. K. Vandersypen, Universal control of a six-qubit quantum processor in sil- icon, Nature609, 919 (2022)

2022
[2]

J. Y. Huang, R. Y. Su, W. H. Lim, M. Feng, B. van Straaten, B. Severin, W. Gilbert, N. Dumoulin Stuyck, T. Tanttu, S. Serrano, J. D. Cifuentes, I. Hansen, A. E. Seedhouse, E. Vahapoglu, R. C. C. Leon, N. V. Abrosi- mov, H.-J. Pohl, M. L. W. Thewalt, F. E. Hudson, C. C. Escott, N. Ares, S. D. Bartlett, A. Morello, A. Saraiva, A. Laucht, A. S. Dzurak, and C...

2024
[3]

Takeda, A

K. Takeda, A. Noiri, T. Nakajima, T. Kobayashi, and S. Tarucha, Quantum error correction with silicon spin qubits, Nature608, 682 (2022)

2022
[4]

A. J. Weinstein, M. D. Reed, A. M. Jones, R. W. An- drews, D. Barnes, J. Z. Blumoff, L. E. Euliss, K. Eng, B. H. Fong, S. D. Ha, D. R. Hulbert, C. A. C. Jack- son, M. Jura, T. E. Keating, J. Kerckhoff, A. A. Kiselev, J. Matten, G. Sabbir, A. Smith, J. Wright, M. T. Rakher, T. D. Ladd, and M. G. Borselli, Universal logic with en- coded spin qubits in silic...

2023
[5]

Chatterjee, P

A. Chatterjee, P. Stevenson, S. De Franceschi, A. Morello, N. P. de Leon, and F. Kuemmeth, Semicon- ductor qubits in practice, Nature Reviews Physics3, 157 (2021)

2021
[6]

A. M. J. Zwerver, T. Krähenmann, T. F. Watson, L. Lampert, H. C. George, R. Pillarisetty, S. A. Bojarski, P. Amin, S. V. Amitonov, J. M. Boter, R. Caudillo, D. Correas-Serrano, J. P. Dehollain, G. Droulers, E. M. Henry, R. Kotlyar, M. Lodari, F. Lüthi, D. J. Michalak, B. K. Mueller, S. Neyens, J. Roberts, N. Samkharadze, G. Zheng, O. K. Zietz, G. Scappucc...

2022
[7]

Steinacker, N

P. Steinacker, N. Dumoulin Stuyck, W. H. Lim, T. Tanttu, M. Feng, S. Serrano, A. Nickl, M. Candido, J. D. Cifuentes, E. Vahapoglu, S. K. Bartee, F. E. Hud- son, K. W. Chan, S. Kubicek, J. Jussot, Y. Canvel, S. Beyne, Y. Shimura, R. Loo, C. Godfrin, B. Raes, S. Baudot, D. Wan, A. Laucht, C. H. Yang, A. Saraiva, C. C. Escott, K. De Greve, and A. S. Dzurak, ...

2025
[8]

Dartiailh, Biel Martinez, Benoit Bertrand, Heimanu Niebojewski, Maud Vinet, Christopher Bäuerle, Franck Bale- stro, Tristan Meunier, and Matias Urdampilleta

P. Hamonic, M. Toubeix, G. Haas, J. Nath, M. C. Dartiailh, B. Martinez, B. Bertrand, H. Niebojewski, M. Vinet, C. Bäuerle, F. Balestro, T. Meunier, and M. Urdampilleta, A foundry-fabricated spin qubit unit cell with in-situ dispersive readout (2025), _eprint: 2504.20572

work page arXiv 2025
[9]

E. J. Thomas, V. N. Ciriano-Tejel, D. F. Wise, D. Prete, M. d. Kruijf, D. J. Ibberson, G. M. Noah, A. Gomez-Saiz, M. F. Gonzalez-Zalba, M. A. I. Johnson, and J. J. L. Morton, Rapid cryogenic characterization of 1,024 inte- grated silicon quantum dot devices, Nature Electronics 8, 75 (2025)

2025
[10]

Contamin, B

L. Contamin, B. C. Paz, B. M. Diaz, B. Bertrand, H. Niebojewski, V. Labracherie, A. Sadik, E. Catapano, M. Cassé, E. Nowak, Y.-M. Niquet, F. Gaillard, T. Me- unier, P.-A. Mortemousque, and M. Vinet, Methodology for an efficient characterization flow of industrial grade Si-based qubit devices, in2022 International Electron Devices Meeting (IEDM)(2022) pp. ...

2022
[11]

M. E. Beverland, P. Murali, M. Troyer, K. M. Svore, T. Hoefler, V. Kliuchnikov, G. H. Low, M. Soeken, A. Sundaram, and A. Vaschillo, Assessing requirements to scale to practical quantum advantage (2022), _eprint: 6 2211.07629

work page internal anchor Pith review arXiv 2022
[12]

Jadot, M

B. Jadot, M. Zurita, G. Billiot, Y. Thonnart, L. L. Guevel, M. Darnas, C. Thomas, J. Charbonnier, T. Meu- nier, M. Vinet, F. Badets, and G. Pillonnet, A Cryogenic Active Router for Qubit Array Biasing from DC to 320 MHz at 100 nm Gate Pitch, inESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESS- CIRC)(2023) pp. 157–160

2023
[13]

S. K. Bartee, W. Gilbert, K. Zuo, K. Das, T. Tanttu, C. H. Yang, N. Dumoulin Stuyck, S. J. Pauka, R. Y. Su, W. H. Lim, S. Serrano, C. C. Escott, F. E. Hudson, K. M. Itoh, A. Laucht, A. S. Dzurak, and D. J. Reilly, Spin-qubitcontrolwithamilli-kelvinCMOSchip,Nature 643, 382 (2025)

2025
[14]

Enthoven, J

L. Enthoven, J. van Staveren, J. Gong, M. Babaie, and F. Sebastiano, A 3V 15b 157µW Cryo-CMOS DAC for Multiplexed Spin-Qubit Biasing, in2022 IEEE Sympo- sium on VLSI Technology and Circuits (VLSI Technology and Circuits)(2022) pp. 228–229

2022
[15]

Subramanian, T

S. Subramanian, T. M. Mladenov, S. Schaal, B. Patra, L. Lampert, N. K. Robinson, J. Roberts, and S. Peller- ano, A Scalable mK Cryo-CMOS Demultiplexer Chip for Voltage Biasing and High-Speed Control of Silicon Qubit Gates, in2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)(2024) pp. 1–2

2024
[16]

Schreckenberg, R

L. Schreckenberg, R. Otten, P. Vliex, R. Xue, J.-S. Tu, I.Seidler, S.Trellenkamp, L.R.Schreiber, H.Bluhm,and S. Van Waasen, SiGe Qubit Biasing with a Cryogenic CMOS DAC at mK Temperature, inEuropean Solid- State Circuits Conference, Vol. 2023-September (2023) pp. 161–164

2023
[17]

Bertrand, B

B. Bertrand, B. Martinez, J. Li, B. C. Paz, V. Mil- lory, V. Labracherie, L. Brévard, H. Sahin, G. Rous- sely, A. Sarrazin, T. Meunier, M. Vinet, Y.-M. Niquet, B. Brun, R. Maurand, S. De Franceschi, and H. Niebo- jewski, Tunnel and capacitive coupling optimization in FDSOI spin-qubit devices, in2023 International Electron Devices Meeting (IEDM)(2023) pp. 1–4

2023