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arxiv: 2604.11379 · v1 · submitted 2026-04-13 · 🪐 quant-ph

From GDSII to Wafer: EDA Design Flow and Data Conversion for Wafer-Scale Manufacturing of Superconducting Quantum Chips

Ling Qiao , Fumin Luo , Qinglang Guo This is my paper

Pith reviewed 2026-05-10 14:55 UTC · model grok-4.3

classification 🪐 quant-ph
keywords superconducting quantum chipswafer-scale fabricationQ-EDAGDSIIdesign rule checkingmask data preparationquantum computingelectronic design automation
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The pith

A complete data-conversion pipeline from GDSII to foundry files is needed for reliable wafer-scale fabrication of superconducting quantum chips.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes that scaling superconducting quantum processors to wafer-scale production requires an electronic design automation system (Q-EDA) capable of converting GDSII layout files into complete manufacturing data sets. It walks through the necessary stages: PDK-driven design rule checking, LVS verification, DFM optimization, wafer layout planning, and mask data preparation. The authors supply a concrete system architecture, a multi-layer process stack model, and nine quantum-specific DRC rules grounded in physical constraints of superconducting circuits. They further benchmark how well existing mainstream tools cover this end-to-end flow. This matters because incomplete data translation currently blocks cost-effective, high-volume quantum chip manufacturing.

Core claim

Starting from GDSII as the single authoritative data source, the paper analyzes the key stages including PDK-based DRC, LVS verification, DFM optimization, wafer layout planning, and MDP. It describes the concrete architecture of a Q-EDA system, presents nine quantum-specific DRC rules together with their physical underpinnings and a multi-layer process stack model, and benchmarks the manufacturing data-flow coverage of mainstream Q-EDA tools.

What carries the argument

The Q-EDA system architecture that uses a multi-layer process stack model together with nine quantum-specific DRC rules to enforce physical constraints during conversion from GDSII layouts to wafer foundry files.

If this is right

  • Designs must satisfy the nine quantum-specific DRC rules to avoid fabrication failures at wafer scale.
  • Mainstream EDA tools currently provide only partial coverage of the full GDSII-to-wafer data-conversion pipeline.
  • The multi-layer process stack model allows systematic integration of quantum physical constraints into layout verification.
  • DFM optimization and MDP steps become mandatory for cost-effective production of large superconducting processors.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Standardization bodies for quantum foundries could adopt the nine rules and stack model as baseline submission requirements.
  • Closing the coverage gaps identified in the benchmarking would shorten design-to-fabrication cycles for next-generation devices.
  • Automated feedback loops from the proposed pipeline into circuit simulators could reduce the number of costly layout iterations.
  • The framework points to a practical route for moving from small prototype chips to million-qubit systems without redesigning the entire manufacturing stack.

Load-bearing premise

The nine quantum-specific DRC rules are both necessary and sufficient for reliable wafer-scale fabrication and that mainstream tools can be benchmarked against the full proposed pipeline without further validation data.

What would settle it

Fabricating identical quantum circuit designs on the same wafer process once with and once without enforcement of the nine proposed DRC rules and measuring differences in yield, defect density, or electrical performance would test whether the rules are essential.

Figures

Figures reproduced from arXiv: 2604.11379 by Fumin Luo, Ling Qiao, Qinglang Guo.

Figure 1
Figure 1. Figure 1: Q-EDA system architecture for wafer-scale quantum chip design. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: End-to-end data flow implemented by the Q-EDA prototype system, [PITH_FULL_IMAGE:figures/full_fig_p007_2.png] view at source ↗
read the original abstract

Superconducting quantum computing is advancing toward the thousand- and even million-qubit regime, making wafer-scale fabrication an essential pathway for achieving large-scale, cost-effective quantum processors. This manufacturing paradigm imposes new requirements on quantum-chip electronic design automation (Q-EDA): design tools must not only generate layouts (GDSII files) that satisfy quantum-circuit physical constraints but also ensure that the design data can be seamlessly converted into a complete set of manufacturing files executable by a wafer foundry, thereby enabling reliable translation from design intent to physical chip. This paper focuses on this critical data-conversion pipeline and presents a systematic treatment of the Q-EDA technology stack for wafer-scale fabrication. Starting from GDSII as the single authoritative data source, we analyze the key stages including process-design-kit (PDK)-based design rule checking (DRC), layout-versus-schematic (LVS) verification, design for manufacturability (DFM) optimization, wafer layout planning, and mask data preparation (MDP). We describe the concrete architecture of a Q-EDA system, present nine quantum-specific DRC rules together with their physical underpinnings and a multi-layer process stack model, and benchmark the manufacturing data-flow coverage of mainstream Q-EDA tools. Finally, we discuss the core challenges and future directions in this field.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The paper claims to provide a systematic treatment of the Q-EDA data-conversion pipeline for wafer-scale superconducting quantum chip fabrication. Starting from GDSII as the authoritative source, it analyzes PDK-based DRC, LVS verification, DFM optimization, wafer layout planning, and MDP; describes a concrete Q-EDA system architecture; presents nine quantum-specific DRC rules with physical underpinnings and a multi-layer process stack model; and benchmarks the manufacturing data-flow coverage of mainstream Q-EDA tools.

Significance. If the nine rules and pipeline are shown to be effective, the work could help standardize design-to-fab flows for large-scale quantum processors and reduce the gap between quantum circuit design and foundry processes. The descriptive architecture and benchmarking tables provide a useful reference point for the community, though the absence of empirical validation data limits the strength of claims about reliability and completeness.

major comments (2)
  1. [Section on quantum-specific DRC rules and multi-layer process stack] The section presenting the nine quantum-specific DRC rules: the rules are motivated by physical considerations (junction area variation, resonator loss, flux-trapping) and a multi-layer stack model, but no process simulation, test-structure measurements, or foundry yield data are supplied to demonstrate that adherence measurably improves coherence or yield metrics, or that any omitted rule would introduce a dominant failure mode. This leaves the claim that the rules are necessary and sufficient for reliable wafer-scale fabrication unsupported.
  2. [Benchmarking of mainstream Q-EDA tools] The benchmarking section: coverage tables for mainstream Q-EDA tools are presented without quantitative comparison to actual mask-shop or fab data, process simulation outputs, or failure-mode statistics, so the assessment of manufacturing data-flow coverage remains qualitative and does not directly test the pipeline's end-to-end correctness.
minor comments (1)
  1. [Abstract] The abstract could explicitly distinguish between the descriptive contributions (architecture, rule list, coverage tables) and any novel technical results.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments on our manuscript describing the Q-EDA data-conversion pipeline. We address each major comment below, clarifying the scope of the work and indicating the revisions we will make.

read point-by-point responses

  1. Referee: [Section on quantum-specific DRC rules and multi-layer process stack] The section presenting the nine quantum-specific DRC rules: the rules are motivated by physical considerations (junction area variation, resonator loss, flux-trapping) and a multi-layer stack model, but no process simulation, test-structure measurements, or foundry yield data are supplied to demonstrate that adherence measurably improves coherence or yield metrics, or that any omitted rule would introduce a dominant failure mode. This leaves the claim that the rules are necessary and sufficient for reliable wafer-scale fabrication unsupported.

    Authors: We agree that empirical validation through process simulations, test structures, or yield data would strengthen claims about the rules' impact on coherence and yield. The manuscript's primary contribution is the systematic Q-EDA architecture and data-flow description, with the nine rules derived from established physical considerations and the multi-layer stack model to inform designers. We do not claim the rules have been experimentally proven necessary and sufficient in this work. We will revise the relevant section and abstract to explicitly delimit the scope, add a forward-looking statement on the need for future foundry-based validation, and avoid any implication of proven sufficiency. This is a textual clarification rather than addition of new data. revision: partial

  2. Referee: [Benchmarking of mainstream Q-EDA tools] The benchmarking section: coverage tables for mainstream Q-EDA tools are presented without quantitative comparison to actual mask-shop or fab data, process simulation outputs, or failure-mode statistics, so the assessment of manufacturing data-flow coverage remains qualitative and does not directly test the pipeline's end-to-end correctness.

    Authors: We concur that the benchmarking tables provide a qualitative feature-coverage assessment derived from tool documentation and specifications, without direct quantitative comparison to mask-shop outputs or fab statistics. The intent is to offer a community reference on alignment with the proposed pipeline rather than an end-to-end correctness proof. We will revise the benchmarking section to state this limitation explicitly, clarify the data sources used for the tables, and include a brief discussion of potential quantitative metrics (e.g., mask error rates or DFM compliance scores) that could be pursued in follow-on studies. revision: partial

Circularity Check

0 steps flagged

No circularity: purely descriptive EDA pipeline survey with no derivations or predictions

full rationale

The paper describes the GDSII-to-wafer data conversion stages for superconducting quantum chips, including PDK-based DRC, LVS, DFM, wafer layout, and MDP. It presents nine quantum-specific DRC rules together with physical motivations and a multi-layer process stack model, plus benchmarking of mainstream tool coverage. No equations, fitted parameters, predictions, or first-principles derivations appear in the provided text or abstract. No self-citations are invoked to justify a central result, and no claim reduces by construction to its own inputs. The work is self-contained as a descriptive architecture and rule enumeration without circular reasoning.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

The paper is an engineering overview and does not introduce mathematical derivations, fitted parameters, or new physical entities.

pith-pipeline@v0.9.0 · 5540 in / 1152 out tokens · 34585 ms · 2026-05-10T14:55:01.654585+00:00 · methodology

discussion (0)

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Reference graph

Works this paper leans on

23 extracted references · 23 canonical work pages

  1. [1]

    EDA-Q: Electronic design automation for superconducting quantum chip,

    B. Zhao, Z. Li, X. Yu, B. Yuan, C. Zhang, Y . Gao, W. Wang, Q. Mu, S. Wang, H. Sun, T. Yang, M. Zhang, C. Han, P. Xu, W. Wang, and Z. Shan, “EDA-Q: Electronic design automation for superconducting quantum chip,”IEEE Transactions on Computer-Aided Design of Inte- grated Circuits and Systems, 2025

    work page 2025

  2. [2]

    Quantum supremacy using a programmable superconducting processor,

    F. Arute, K. Arya, R. Babbush, D. Bacon, J. C. Bardin, R. Barends, R. Biswas, S. Boixo, F. G. Brandao, D. A. Buellet al., “Quantum supremacy using a programmable superconducting processor,”Nature, vol. 574, no. 7779, pp. 505–510, 2019

    work page 2019

  3. [3]

    Advanced cmos manufacturing of superconducting qubits on 300 mm wafers,

    J. Van Damme, S. Massar, R. Acharya, T. Ivanov, D. Perez Lozano, Y . Canvel, M. Demarets, D. Vangoidsenhoven, Y . Hermans, J. Laiet al., “Advanced cmos manufacturing of superconducting qubits on 300 mm wafers,”Nature, vol. 634, no. 8032, pp. 74–79, 2024

    work page 2024

  4. [4]

    GDSII stream format manual,

    Calma Company, “GDSII stream format manual,” 1987, release 6.0

    work page 1987

  5. [5]

    Practical guide for building superconducting quantum devices,

    Y . Y . Gao, M. A. Rol, S. Touzard, and C. Wang, “Practical guide for building superconducting quantum devices,”PRX Quantum, vol. 2, no. 4, p. 040202, 2021

    work page 2021

  6. [6]

    Fabrication of al/alox/al junctions with high uniformity and reproducibility,

    Y . Zhenget al., “Fabrication of al/alox/al junctions with high uniformity and reproducibility,”Scientific Reports, vol. 13, no. 1, p. 9636, 2023

    work page 2023

  7. [7]

    A review of design concerns in superconducting quantum circuits,

    E. M. Levenson-Falk and S. A. Shanto, “A review of design concerns in superconducting quantum circuits,”Materials for Quantum Technology, 2025, arXiv:2411.16967

    work page arXiv 2025

  8. [8]

    Design automation of super- conductive digital circuits: A review,

    G. Krylov, J. Kawa, and E. G. Friedman, “Design automation of super- conductive digital circuits: A review,”IEEE Nanotechnology Magazine, vol. 15, no. 6, pp. 54–67, 2021

    work page 2021

  9. [9]

    Superconducting qubits: Current state of play,

    M. Kjaergaard, M. E. Schwartz, J. Braum ¨uller, P. Krantz, J. I.-J. Wang, S. Gustavsson, and W. D. Oliver, “Superconducting qubits: Current state of play,”Annual Review of Condensed Matter Physics, vol. 11, pp. 369– 395, 2020

    work page 2020

  10. [10]

    Qiskit metal: An open-source framework for quan- tum device design & analysis,

    IBM Quantum, “Qiskit metal: An open-source framework for quan- tum device design & analysis,” https://qiskit-community.github.io/ qiskit-metal/, 2021, accessed: 2026-03-01

    work page 2021

  11. [11]

    Layout versus schematic with design/magnetic rule checking for superconduct- ing integrated circuit layouts,

    R. van Staden, J. A. Delport, J. A. Coetzee, and C. J. Fourie, “Layout versus schematic with design/magnetic rule checking for superconduct- ing integrated circuit layouts,” in2019 IEEE International Supercon- ductive Electronics Conference (ISEC). IEEE, 2019, pp. 1–5

    work page 2019

  12. [12]

    Advanced fabrication processes for superconducting very large-scale integrated circuits,

    S. K. Tolpygo, “Advanced fabrication processes for superconducting very large-scale integrated circuits,”IEEE Transactions on Applied Superconductivity, vol. 26, no. 3, pp. 1–10, 2016

    work page 2016

  13. [13]

    GDSFactory: Python library for chip de- sign,

    GDSFactory Contributors, “GDSFactory: Python library for chip de- sign,” https://gdsfactory.github.io/, 2023, accessed: 2026-03-01

    work page 2023

  14. [14]

    White paper: A process design kit for superconducting components,

    N. Kohli, C. Paradis, S. Grayli, and U. Mendes, “White paper: A process design kit for superconducting components,” CMC Microsystems, Tech. Rep., 2023

    work page 2023

  15. [15]

    Coplanar waveguide resonators for circuit quantum electrodynamics,

    M. G ¨oppl, A. Fragner, M. Baur, R. Bianchetti, S. Filipp, J. Fink, P. Leek, G. Puebla, L. Steffen, and A. Wallraff, “Coplanar waveguide resonators for circuit quantum electrodynamics,”Journal of Applied Physics, vol. 104, no. 11, p. 113904, 2008

    work page 2008

  16. [16]

    Electronic design automation tools for superconducting circuits,

    C. J. Fourie, “Electronic design automation tools for superconducting circuits,”Journal of Physics: Conference Series, vol. 1590, no. 1, p. 012040, 2020

    work page 2020

  17. [17]

    Microwave package design for superconducting quantum processors,

    S. Huang, B. Lienhard, G. Calusine, A. Veps ¨al¨ainen, J. Braum¨uller, D. K. Kim, A. J. Melville, B. M. Niedzielski, J. L. Yoder, B. Kannanet al., “Microwave package design for superconducting quantum processors,” PRX Quantum, vol. 2, no. 2, p. 020306, 2021

    work page 2021

  18. [18]

    New material platform for superconducting transmon qubits with coherence times exceeding 0.3 milliseconds,

    A. P. Place, L. V . Rodgers, P. Mundada, B. M. Smitham, M. Fitzpatrick, Z. Leng, A. Premkumar, J. Bryon, A. Vrajitoarea, S. Sussmanet al., “New material platform for superconducting transmon qubits with coherence times exceeding 0.3 milliseconds,”Nature Communications, vol. 12, no. 1, p. 1779, 2021

    work page 2021

  19. [19]

    Fabrication and characterization of aluminum airbridges for superconducting microwave circuits,

    Z. Chen, A. Megrant, J. Kelly, R. Barends, J. Bochmann, Y . Chen, B. Chiaro, A. Dunsworth, E. Jeffrey, J. Mutuset al., “Fabrication and characterization of aluminum airbridges for superconducting microwave circuits,”Applied Physics Letters, vol. 104, no. 5, p. 052602, 2014

    work page 2014

  20. [20]

    KQCircuits: KLayout Python library for automating the design of superconducting quantum circuits,

    IQM Finland, “KQCircuits: KLayout Python library for automating the design of superconducting quantum circuits,” https://github.com/ iqm-finland/KQCircuits, 2022, accessed: 2026-03-01

    work page 2022

  21. [21]

    Superconducting qubits in a flip-chip architecture,

    C. R. Conner, A. Bienfait, H.-S. Chang, M.-H. Chou, ´E. Dumur, J. Grebel, G. A. Peairs, R. G. Povey, H. Yan, Y . P. Zhonget al., “Superconducting qubits in a flip-chip architecture,”Applied Physics Letters, vol. 118, no. 23, p. 232602, 2021

    work page 2021

  22. [22]

    3d integrated superconducting qubits,

    D. Rosenberg, D. Kim, R. Das, D. Yost, S. Gustavsson, D. Hover, P. Krantz, A. Melville, L. Racz, G. Samachet al., “3d integrated superconducting qubits,”npj Quantum Information, vol. 3, no. 1, p. 42, 2017

    work page 2017

  23. [23]

    Chip and package- scale interconnects for general-purpose, domain-specific, and quantum computing systems—overview, challenges, and opportunities,

    A. Das, M. Palesi, J. Kim, and P. P. Pande, “Chip and package- scale interconnects for general-purpose, domain-specific, and quantum computing systems—overview, challenges, and opportunities,”IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 14, no. 3, pp. 354–370, 2024

    work page 2024