Building reliable 3D photonic integrated circuits and cavities at the wafer scale

Chao Xiang; Mingfei Liu; Yaoran Huang; Yuemin Li; Yuhao Huang; Yunqi Fu; Yu Xia; Zhaoting Geng; Zheng Li

arxiv: 2604.12889 · v1 · submitted 2026-04-14 · ⚛️ physics.optics

Building reliable 3D photonic integrated circuits and cavities at the wafer scale

Yuhao Huang , Yunqi Fu , Yu Xia , Yuemin Li , Zheng Li , Yaoran Huang , Zhaoting Geng , Mingfei Liu

show 1 more author

Chao Xiang

This is my paper

Pith reviewed 2026-05-10 14:31 UTC · model grok-4.3

classification ⚛️ physics.optics

keywords 3D photonic integrated circuitswafer-scale fabricationsilicon nitride waveguideshigh-Q cavitiesinter-layer transitionschemical mechanical polishingoptical cavities

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The pith

Etch-back polishing and a kappa-engineered taper produce reliable wafer-scale 3D photonic circuits with losses of 0.07 dB/cm and the first two-layer high-Q cavities.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes a fabrication route that stacks two silicon nitride waveguide layers into functional 3D photonic circuits across entire wafers while maintaining low and uniform losses. An etch-back chemical mechanical polishing step flattens the spacer layer between the waveguides so that light can move between layers consistently. A new taper design shapes the coupling strength along its length to achieve high transition efficiency in a smaller footprint than conventional straight tapers, raising a reliability metric by 75 percent. The resulting circuits show typical waveguide losses of 0.077 dB/cm and 0.068 dB/cm together with inter-layer transitions of only 6 mdB. These low losses then allow optical cavities to occupy two separate device layers and still reach high quality factors.

Core claim

The central claim is that etch-back assisted chemical mechanical polishing delivers high wafer-scale uniformity of the spacer layer between two silicon nitride waveguide layers, while a kappa-engineered taper overcomes the usual efficiency-footprint trade-off in inter-layer transitions. These advances together yield 3D photonic integrated circuits with typical losses of 0.077 dB/cm and 0.068 dB/cm on the two layers and 3D transition losses as low as 6 mdB. The low transition loss in turn enables the first class of 3D high-Q optical cavities that occupy two distinct device layers.

What carries the argument

The kappa-engineered taper, which varies the coupling coefficient along the transition length to optimize efficiency within a compact footprint, paired with the E-CMP process that planarizes the inter-layer spacer for uniform coupling across the wafer.

If this is right

Reliable 3D PICs become practical at full wafer scale with propagation losses low enough for dense photonic systems.
High-Q cavities that span two device layers become available, expanding the design space for resonators.
The same process and design rules supply a scalable route for applications in photonic interconnects, computing networks, high-density sensors, and nonlinear photonics.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The method could be extended to three or more layers to increase circuit density without a proportional rise in loss.
Full statistical yield data across many wafers would be required to confirm readiness for volume manufacturing.
The low-loss 3D transitions could be combined with other material platforms to address different operating wavelengths or nonlinear effects.

Load-bearing premise

The E-CMP process produces the claimed high uniformity of spacer thickness across the full wafer and the kappa-engineered taper delivers its performance gains without introducing new loss mechanisms or yield drops not captured in the reported typical values.

What would settle it

A wafer-scale map of spacer layer thickness that shows variations exceeding a few nanometers, or repeated measurements of 3D transition loss that average well above 6 mdB across many devices and multiple wafers.

read the original abstract

Three-dimensional (3D) photonic integrated circuits (PIC) are emerging as an indispensable scheme for high density and multifunctional photonic systems. However, the wafer-scale scaling of PICs towards a 3D configuration is constrained by two key factors: (i) the trade-off between inter-layer taper efficiency and footprint, and (ii) wafer-scale uniformity of inter-layer transition loss. In this work, we introduce etch-back assisted chemical mechanical polishing (E-CMP) to achieve high wafer-scale uniformity of the spacer layer. Moreover, we break the efficiency-footprint trade-off by demonstrating a novel $\kappa$-engineered taper, achieving a reliability metric that is 75\% higher than the traditional linearly tapered structure. Building on these design and fabrication developments, we enable reliable 3D PICs with typical loss of 0.077 and 0.068 dB/cm on two silicon nitride (SiN) waveguide layers and typical 3D transition loss as low as 6 mdB. Furthermore, the low 3D transition loss enables the first class of 3D high-Q optical cavities occupying two distinct device layers, providing new design space for high-Q optical cavities. The scalable fabrication process and design methodology provide routes for wafer-scale reliable 3D PICs that are promising in a series of applications ranging from photonic interconnects and computing networks to high-density photonic sensors and nonlinear photonics.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

This paper shows a practical E-CMP plus kappa-taper route to low-loss 3D SiN circuits and two-layer cavities, but the wafer-scale reliability claims rest on typical values without supporting statistics.

read the letter

The main thing to know is that the authors combine etch-back chemical mechanical polishing with a kappa-engineered taper to reach typical propagation losses of 0.077 and 0.068 dB/cm on two SiN layers and 6 mdB interlayer transitions, plus the first two-layer high-Q cavities. That combination looks like a concrete step forward for denser 3D photonic systems. The taper improves their reliability metric by 75 percent over a standard linear design while keeping the footprint manageable, and the polishing step targets spacer uniformity between layers. Those are the parts that feel new relative to earlier 2D work and simple tapers. The cavity demonstration follows directly from the low transition loss and gives designers an extra degree of freedom. The fabrication details are specific enough that someone trying to replicate or extend the process can see what was done. The soft spot is the evidence for the big claims of reliability and wafer-scale uniformity. The paper leans on typical loss numbers and calls the result reliable, yet it does not supply standard deviations, wafer maps, die-to-die histograms, or yield percentages. Without those numbers it is difficult to tell whether the process delivers consistent performance across a full wafer or whether the reported values come from selected good devices. The stress-test note correctly flags this gap, and it directly affects how much weight the title and abstract can carry. This work is aimed at researchers and engineers building photonic interconnects, computing networks, or high-density sensors who need practical 3D stacking methods. A reader focused on fabrication process development or 3D integration will find the loss numbers and design choices useful even if they want more statistical backing. It deserves a serious referee because the experimental results are grounded and the problem it addresses is real for scaling. I would recommend sending it for peer review, with the expectation that reviewers will ask for the missing uniformity data.

Referee Report

2 major / 0 minor

Summary. The manuscript introduces etch-back assisted chemical mechanical polishing (E-CMP) to achieve high wafer-scale uniformity of the spacer layer and a novel κ-engineered taper to overcome the efficiency-footprint trade-off in inter-layer transitions for 3D photonic integrated circuits on silicon nitride. Building on these, the authors report typical propagation losses of 0.077 dB/cm and 0.068 dB/cm on two waveguide layers, 3D transition losses as low as 6 mdB, a 75% improvement in a reliability metric over linear tapers, and the first 3D high-Q cavities spanning two device layers.

Significance. If the wafer-scale uniformity and low-loss performance are confirmed with comprehensive statistics, this work would meaningfully advance scalable 3D PIC fabrication by addressing key barriers to multilayer integration, enabling higher-density systems for photonic interconnects, computing, sensors, and nonlinear optics while also expanding high-Q cavity design options.

major comments (2)

Abstract: The central claims of 'reliable' wafer-scale 3D PICs with the stated typical loss values and 75% reliability improvement rest on 'typical' numbers without reported wafer-scale statistics, standard deviations, die-to-die histograms, yield percentages, or number of devices measured. This directly weakens the ability to substantiate uniformity of the E-CMP spacer and the absence of hidden yield penalties in the κ-taper.
Results (loss and cavity sections): The propagation and transition loss figures are presented only as typical values; without error bars, measurement counts, or wafer maps, it is impossible to distinguish consistent performance from post-selection of best devices, which is load-bearing for the 'reliable' and 'wafer-scale' qualifiers.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback emphasizing the need for statistical rigor to support the wafer-scale and reliability claims. We address each major comment below and have revised the manuscript accordingly.

read point-by-point responses

Referee: Abstract: The central claims of 'reliable' wafer-scale 3D PICs with the stated typical loss values and 75% reliability improvement rest on 'typical' numbers without reported wafer-scale statistics, standard deviations, die-to-die histograms, yield percentages, or number of devices measured. This directly weakens the ability to substantiate uniformity of the E-CMP spacer and the absence of hidden yield penalties in the κ-taper.

Authors: We agree that the presentation of 'typical' values would be strengthened by explicit statistical details. In the revised manuscript, we have updated the abstract and main text to include the number of devices measured for each metric, standard deviations on the reported loss values, die-to-die histograms, and yield percentages. These additions, drawn from our full characterization dataset, substantiate the uniformity of the E-CMP spacer layer and confirm that the κ-engineered tapers do not introduce hidden yield penalties. revision: yes
Referee: Results (loss and cavity sections): The propagation and transition loss figures are presented only as typical values; without error bars, measurement counts, or wafer maps, it is impossible to distinguish consistent performance from post-selection of best devices, which is load-bearing for the 'reliable' and 'wafer-scale' qualifiers.

Authors: We concur that error bars, measurement counts, and wafer maps are necessary to demonstrate consistency. The revised manuscript now includes error bars on all loss and Q-factor plots, specifies the number of devices and wafers measured for each result, and adds wafer maps plus histograms to the supplementary information. These changes show that the reported performance is representative rather than post-selected and support the wafer-scale reliability claims for both the waveguides and the 3D cavities. revision: yes

Circularity Check

0 steps flagged

No circularity: experimental results with no derivation chain

full rationale

The paper reports measured fabrication outcomes (E-CMP spacer uniformity and κ-engineered taper performance) and resulting typical propagation/transition losses. No equations, first-principles derivations, or predictions are presented that reduce to fitted inputs, self-citations, or ansatzes. The central claims rest on direct experimental data rather than any load-bearing theoretical step, so the work is self-contained.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

The central claims rest on standard semiconductor fabrication assumptions (uniform deposition, etch selectivity, CMP removal rates) plus the unverified premise that the new taper shape improves reliability without hidden yield penalties. No free parameters or invented entities are introduced in the abstract.

axioms (2)

domain assumption E-CMP produces wafer-scale spacer uniformity sufficient for low inter-layer loss
Invoked to justify the 3D transition loss of 6 mdB
domain assumption The κ-engineered taper breaks the efficiency-footprint trade-off without new loss channels
Central to the 75% reliability improvement claim

pith-pipeline@v0.9.0 · 5574 in / 1417 out tokens · 31139 ms · 2026-05-10T14:31:56.156188+00:00 · methodology

discussion (0)

Reference graph

Works this paper leans on

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work page 2024

[1] [1]

& Yoo, S

Zhang, Y., Samanta, A., Shang, K. & Yoo, S. B. Scal- able 3d silicon photonic electronic integrated circuits and their applications.IEEE Journal of Selected Topics in Quantum Electronics26, 1–10 (2020)

work page 2020

[2] [2]

Zhu, X.et al.Low-loss and polarization insensitive 32× 4 optical switch for roadm applications.Light: Science & Applications13, 94 (2024)

work page 2024

[3] [3]

In2025 Eu- ropean Conference on Optical Communications (ECOC), 1–4 (2025)

Xia, Y.et al.3d silicon nitride waveguide interposers for high-density scale-up chiplet interconnects. In2025 Eu- ropean Conference on Optical Communications (ECOC), 1–4 (2025)

work page 2025

[4] [4]

Kaur, P.et al.Hybrid and heterogeneous photonic inte- gration.APL photonics6(2021)

work page 2021

[5] [5]

M.et al.Ultra-low crosstalk, cmos compatible waveguide crossings for densely integrated photonic in- terconnection networks.Optics express21, 12002–12013 (2013)

Jones, A. M.et al.Ultra-low crosstalk, cmos compatible waveguide crossings for densely integrated photonic in- terconnection networks.Optics express21, 12002–12013 (2013)

work page 2013

[6] [6]

D.et al.Monolithically integrated multilayer silicon nitride-on-silicon waveguide platforms for 3-d pho- tonic circuits and devices.Proceedings of the IEEE106, 2232–2245 (2018)

Sacher, W. D.et al.Monolithically integrated multilayer silicon nitride-on-silicon waveguide platforms for 3-d pho- tonic circuits and devices.Proceedings of the IEEE106, 2232–2245 (2018)

work page 2018

[7] [7]

Margalit, N.et al.Perspective on the future of silicon photonics and electronics.Applied Physics Letters118, 220501 (2021)

work page 2021

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A.et al.Extending the spectrum of fully inte- grated photonics to submicrometre wavelengths.Nature 610, 54–60 (2022)

Tran, M. A.et al.Extending the spectrum of fully inte- grated photonics to submicrometre wavelengths.Nature 610, 54–60 (2022)

work page 2022

[9] [9]

Churaev, M.et al.A heterogeneously integrated lithium niobate-on-silicon nitride photonic platform.Nature com- munications14, 3499 (2023)

work page 2023

[10] [10]

Xiang, C.et al.3d integration enables ultralow-noise isolator-free lasers in silicon photonics.Nature620, 78– 85 (2023)

work page 2023

[11] [11]

& Yoo, S

Zhang, Y., Ling, Y.-C., Zhang, Y., Shang, K. & Yoo, S. B. High-density wafer-scale 3-d silicon-photonic in- tegrated circuits.IEEE Journal of Selected Topics in Quantum Electronics24, 1–10 (2018)

work page 2018

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IEEE Journal of Selected Topics in Quantum Electronics 20, 317–322 (2014)

Kang, J.et al.Amorphous-silicon inter-layer grating couplers with metal mirrors toward 3-d interconnection. IEEE Journal of Selected Topics in Quantum Electronics 20, 317–322 (2014)

work page 2014

[13] [13]

Sodagar, M., Pourabolghasem, R., Eftekhar, A. A. & Adibi, A. High-efficiency and wideband interlayer grat- ing couplers in multilayer si/sio 2/sin platform for 3d integration of optical functionalities.Optics express22, 16767–16777 (2014)

work page 2014

[14] [14]

Wan, C., Gaylord, T. K. & Bakir, M. S. Grating design for interlayer optical interconnection of in-plane waveg- uides.Applied Optics55, 2601–2610 (2016)

work page 2016

[15] [15]

Xu, P., Zhang, Y., Zhang, S., Chen, Y. & Yu, S. Sin x–si interlayer coupler using a gradient index metamaterial. Optics letters44, 1230–1233 (2019)

work page 2019

[16] [16]

& Yoo, S

Shang, K., Pathak, S., Guan, B., Liu, G. & Yoo, S. Low- loss compact multilayer silicon nitride platform for 3d photonic integrated circuits.Optics Express23, 21334– 21342 (2015)

work page 2015

[17] [17]

D.et al.Tri-layer silicon nitride-on-silicon photonic platform for ultra-low-loss crossings and inter- layer transitions.Optics express25, 30862–30875 (2017)

Sacher, W. D.et al.Tri-layer silicon nitride-on-silicon photonic platform for ultra-low-loss crossings and inter- layer transitions.Optics express25, 30862–30875 (2017)

work page 2017

[18] [18]

& Yan, J

Zhang, L., Guo, Y., Wang, J., Li, J. & Yan, J. 3d het- erogeneous integration of silicon nitride and aluminum nitride on sapphire toward ultrawideband photonics in- tegrated circuits.ACS Photonics12, 2538–2547 (2025)

work page 2025

[19] [19]

Niels, M.et al.A high-speed heterogeneous lithium tan- talate silicon photonics platform.Nature Photonics1–7 (2026). 9

work page 2026

[20] [20]

F.et al.Ultra-low-loss single-mode si3n4 waveguides with 0.7 db/m propagation loss

Bauters, J. F.et al.Ultra-low-loss single-mode si3n4 waveguides with 0.7 db/m propagation loss. InEuro- pean conference and exposition on optical communica- tions, Th–12 (Optica Publishing Group, 2011)

work page 2011

[21] [21]

Jin, W.et al.Hertz-linewidth semiconductor lasers using cmos-ready ultra-high-q microresonators.Nature Pho- tonics15, 346–353 (2021)

work page 2021

[22] [22]

Communications Physics5, 84 (2022)

Ji, X.et al.Compact, spatial-mode-interaction-free, ultralow-loss, nonlinear photonic integrated circuits. Communications Physics5, 84 (2022)

work page 2022

[23] [23]

Ji, X.et al.Efficient mass manufacturing of high-density, ultra-low-loss si3n4 photonic integrated circuits.Optica 11, 1397–1407 (2024)

work page 2024

[24] [24]

Liang, T.-L.et al.A fully numerical method for designing efficient adiabatic mode evolution structures (adiabatic taper, coupler, splitter, mode converter) applicable to complex geometries.Journal of Lightwave Technology 39, 5531–5547 (2021)

work page 2021

[25] [25]

K.et al.Shortcuts to adiabaticity in waveg- uide couplers–theory and implementation.Advances in Physics: X6, 1894978 (2021)

Taras, A. K.et al.Shortcuts to adiabaticity in waveg- uide couplers–theory and implementation.Advances in Physics: X6, 1894978 (2021)

work page 2021

[26] [26]

& Penty, R

Yao, C., Cheng, Q., Roelkens, G. & Penty, R. Bridging the gap between resonance and adiabaticity: a compact and highly tolerant vertical coupling structure.Photonics Research10, 2081–2090 (2022)

work page 2081

[27] [27]

Van Asch, J.et al.A methodical approach to design adi- abatic waveguide couplers for heterogeneous integrated photonics.Journal of Physics: Photonics6, 045013 (2024)

work page 2024

[28] [28]

Pfeiffer, M. H. P.et al.Photonic damascene process for integrated high-q microresonator based nonlinear pho- tonics.Optica3, 20–25 (2016)

work page 2016

[29] [29]

Liu, J.et al.High-yield, wafer-scale fabrication of ultralow-loss, dispersion-engineered silicon nitride pho- tonic circuits.Nature communications12, 2236 (2021)

work page 2021

[30] [30]

Pfeiffer, M. H. P.et al.Photonic damascene process for low-loss, high-confinement silicon nitride waveguides. IEEE Journal of selected topics in quantum electronics 24, 1–11 (2018)

work page 2018

[31] [31]

& Poon, A

Wu, K. & Poon, A. W. Stress-released si3n4 fabrication process for dispersion-engineered integrated silicon pho- tonics.Optics Express28, 17708–17722 (2020)

work page 2020

[32] [32]

& Zhang, Z

Liu, S., Zhang, Y., Hariri, A., Al-Hallak, A.-R. & Zhang, Z. Fabrication of ultra-low-loss, dispersion-engineered sil- icon nitride photonic integrated circuits via silicon hard- mask etching.ACS Photonics12, 1039–1046 (2025)

work page 2025

[33] [33]

Zhang, S.et al.Low-temperature sputtered ultralow-loss silicon nitride for hybrid photonic integration.Laser & Photonics Reviews18, 2300642 (2024)

work page 2024

[34] [34]

Optics Letters43, 1527–1530 (2018)

Chiles, J.et al.Deuterated silicon nitride photonic de- vices for broadband optical frequency comb generation. Optics Letters43, 1527–1530 (2018)

work page 2018

[35] [35]

Bose, D.et al.Anneal-free ultra-low loss silicon nitride integrated photonics.Light: Science & Applications13, 156 (2024). METHODS Comparison of SiN deposition method and fabrication process flow To release stress and reduce the wafer bow, process flow based on low-pressure chemical vapor deposition (LPCVD) SiN usually demands complicated processes, such ...

work page 2024